case ARM::fixup_t2_condbranch:
return COFF::IMAGE_REL_ARM_BRANCH20T;
case ARM::fixup_t2_uncondbranch:
- return COFF::IMAGE_REL_ARM_BRANCH24T;
case ARM::fixup_arm_thumb_bl:
+ return COFF::IMAGE_REL_ARM_BRANCH24T;
case ARM::fixup_arm_thumb_blx:
return COFF::IMAGE_REL_ARM_BLX23T;
case ARM::fixup_t2_movw_lo16:
.global target
.thumb_func
-branch24t:
+branch24t_0:
b target
-@ CHECK-ENCODING-LABEL: branch24t:
+@ CHECK-ENCODING-LABEL: branch24t_0:
@ CHECK-ENCODING-NEXT: b.w #0
.thumb_func
+branch24t_1:
+ bl target
+
+@ CHECK-ENCODING-LABEL: branch24t_1:
+@ CHECK-ENCODING-NEXR: bl #0
+
+ .thumb_func
branch20t:
bcc target
.thumb_func
blx23t:
- bl target
+ blx target
@ CHECK-ENCODING-LABEL: blx23t:
-@ CHECK-ENCODING-NEXT: bl #0
+@ CHECK-ENCODING-NEXT: blx #0
.thumb_func
mov32t:
@ CHECK-RELOCATION: Relocations [
@ CHECK-RELOCATION: Section (1) .text {
@ CHECK-RELOCATION: 0x0 IMAGE_REL_ARM_BRANCH24T
-@ CHECK-RELOCATION: 0x4 IMAGE_REL_ARM_BRANCH20T
-@ CHECK-RELOCATION: 0x8 IMAGE_REL_ARM_BLX23T
-@ CHECK-RELOCATION: 0xC IMAGE_REL_ARM_MOV32T
-@ CHECK-RELOCATION: 0x1C IMAGE_REL_ARM_ADDR32
-@ CHECK-RELOCATION: 0x28 IMAGE_REL_ARM_ADDR32NB
-@ CHECK-RELOCATION: 0x34 IMAGE_REL_ARM_SECREL
+@ CHECK-RELOCATION: 0x4 IMAGE_REL_ARM_BRANCH24T
+@ CHECK-RELOCATION: 0x8 IMAGE_REL_ARM_BRANCH20T
+@ CHECK-RELOCATION: 0xC IMAGE_REL_ARM_BLX23T
+@ CHECK-RELOCATION: 0x10 IMAGE_REL_ARM_MOV32T
+@ CHECK-RELOCATION: 0x20 IMAGE_REL_ARM_ADDR32
+@ CHECK-RELOCATION: 0x2C IMAGE_REL_ARM_ADDR32NB
+@ CHECK-RELOCATION: 0x38 IMAGE_REL_ARM_SECREL
@ CHECK-RELOCATION: }
@ CHECK-RELOCATION: ]