arm64: tegra: Fix #address-cells/#size-cells for SRAM on Tegra186

The standard mmio-sram bindings require the #address- and #size-cells
properties to be 1.

Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 58100fb..373f575 100644 (file)
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -1216,20 +1216,20 @@
        sysram@30000000 {
                compatible = "nvidia,tegra186-sysram", "mmio-sram";
                reg = <0x0 0x30000000 0x0 0x50000>;
-               #address-cells = <2>;
-               #size-cells = <2>;
-               ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0x0 0x0 0x30000000 0x50000>;
 
                cpu_bpmp_tx: shmem@4e000 {
                        compatible = "nvidia,tegra186-bpmp-shmem";
-                       reg = <0x0 0x4e000 0x0 0x1000>;
+                       reg = <0x4e000 0x1000>;
                        label = "cpu-bpmp-tx";
                        pool;
                };
 
                cpu_bpmp_rx: shmem@4f000 {
                        compatible = "nvidia,tegra186-bpmp-shmem";
-                       reg = <0x0 0x4f000 0x0 0x1000>;
+                       reg = <0x4f000 0x1000>;
                        label = "cpu-bpmp-rx";
                        pool;
                };