drm/amd/display: Set TMZ and DCC for secondary surface

Add register programming to support TMZ and DCC on
secondary surfaces.

Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
index d2ab78b..c28085b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
@@ -396,11 +396,15 @@ bool hubp1_program_surface_flip_and_addr(
                if (address->grph_stereo.right_addr.quad_part == 0)
                        break;
 
-               REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
+               REG_UPDATE_8(DCSURF_SURFACE_CONTROL,
                                PRIMARY_SURFACE_TMZ, address->tmz_surface,
                                PRIMARY_SURFACE_TMZ_C, address->tmz_surface,
                                PRIMARY_META_SURFACE_TMZ, address->tmz_surface,
-                               PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface);
+                               PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface,
+                               SECONDARY_SURFACE_TMZ, address->tmz_surface,
+                               SECONDARY_SURFACE_TMZ_C, address->tmz_surface,
+                               SECONDARY_META_SURFACE_TMZ, address->tmz_surface,
+                               SECONDARY_META_SURFACE_TMZ_C, address->tmz_surface);
 
                if (address->grph_stereo.right_meta_addr.quad_part != 0) {
 
@@ -459,9 +463,11 @@ void hubp1_dcc_control(struct hubp *hubp, bool enable,
        uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0;
        struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 
-       REG_UPDATE_2(DCSURF_SURFACE_CONTROL,
+       REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
                        PRIMARY_SURFACE_DCC_EN, dcc_en,
-                       PRIMARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk);
+                       PRIMARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk,
+                       SECONDARY_SURFACE_DCC_EN, dcc_en,
+                       SECONDARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk);
 }
 
 void hubp1_program_surface_config(

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
index af38403..d901d50 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
@@ -312,6 +312,12 @@
        HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_META_SURFACE_TMZ_C, mask_sh),\
        HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_EN, mask_sh),\
        HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_IND_64B_BLK, mask_sh),\
+       HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_TMZ, mask_sh),\
+       HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_TMZ_C, mask_sh),\
+       HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_META_SURFACE_TMZ, mask_sh),\
+       HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_META_SURFACE_TMZ_C, mask_sh),\
+       HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_EN, mask_sh),\
+       HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_IND_64B_BLK, mask_sh),\
        HUBP_SF(HUBPRET0_HUBPRET_CONTROL, DET_BUF_PLANE1_BASE_ADDRESS, mask_sh),\
        HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CB_B, mask_sh),\
        HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CR_R, mask_sh),\
@@ -489,6 +495,8 @@
        type SECONDARY_META_SURFACE_TMZ_C;\
        type PRIMARY_SURFACE_DCC_EN;\
        type PRIMARY_SURFACE_DCC_IND_64B_BLK;\
+       type SECONDARY_SURFACE_DCC_EN;\
+       type SECONDARY_SURFACE_DCC_IND_64B_BLK;\
        type DET_BUF_PLANE1_BASE_ADDRESS;\
        type CROSSBAR_SRC_CB_B;\
        type CROSSBAR_SRC_CR_R;\