x86/resctrl: Move all the macros to resctrl/internal.h

Move all the macros to resctrl/internal.h and rename the registers with
MSR_ prefix for consistency.

 [bp: align MSR definitions vertically ]

Signed-off-by: Babu Moger <babu.moger@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Cc: "Chang S. Bae" <chang.seok.bae@intel.com>
Cc: David Miller <davem@davemloft.net>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Dmitry Safonov <dima@arista.com>
Cc: Fenghua Yu <fenghua.yu@intel.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jann Horn <jannh@google.com>
Cc: Joerg Roedel <jroedel@suse.de>
Cc: Jonathan Corbet <corbet@lwn.net>
Cc: Josh Poimboeuf <jpoimboe@redhat.com>
Cc: Kate Stewart <kstewart@linuxfoundation.org>
Cc: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
Cc: <linux-doc@vger.kernel.org>
Cc: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Philippe Ombredanne <pombredanne@nexb.com>
Cc: Pu Wen <puwen@hygon.cn>
Cc: <qianyue.zj@alibaba-inc.com>
Cc: "Rafael J. Wysocki" <rafael@kernel.org>
Cc: Reinette Chatre <reinette.chatre@intel.com>
Cc: Rian Hunter <rian@alum.mit.edu>
Cc: Sherry Hurwitz <sherry.hurwitz@amd.com>
Cc: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Thomas Lendacky <Thomas.Lendacky@amd.com>
Cc: Tony Luck <tony.luck@intel.com>
Cc: Vitaly Kuznetsov <vkuznets@redhat.com>
Cc: <xiaochen.shen@intel.com>
Link: https://lkml.kernel.org/r/20181121202811.4492-5-babu.moger@amd.com

diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c
index 4038073..cf6491e 100644 (file)
--- a/arch/x86/kernel/cpu/resctrl/core.c
+++ b/arch/x86/kernel/cpu/resctrl/core.c
@@ -33,9 +33,6 @@
 #include <asm/resctrl_sched.h>
 #include "internal.h"
 
-#define MBA_IS_LINEAR  0x4
-#define MBA_MAX_MBPS   U32_MAX
-
 /* Mutex to protect rdtgroup access. */
 DEFINE_MUTEX(rdtgroup_mutex);
 
@@ -72,7 +69,7 @@ struct rdt_resource rdt_resources_all[] = {
                .rid                    = RDT_RESOURCE_L3,
                .name                   = "L3",
                .domains                = domain_init(RDT_RESOURCE_L3),
-               .msr_base               = IA32_L3_CBM_BASE,
+               .msr_base               = MSR_IA32_L3_CBM_BASE,
                .msr_update             = cat_wrmsr,
                .cache_level            = 3,
                .cache = {
@@ -89,7 +86,7 @@ struct rdt_resource rdt_resources_all[] = {
                .rid                    = RDT_RESOURCE_L3DATA,
                .name                   = "L3DATA",
                .domains                = domain_init(RDT_RESOURCE_L3DATA),
-               .msr_base               = IA32_L3_CBM_BASE,
+               .msr_base               = MSR_IA32_L3_CBM_BASE,
                .msr_update             = cat_wrmsr,
                .cache_level            = 3,
                .cache = {
@@ -106,7 +103,7 @@ struct rdt_resource rdt_resources_all[] = {
                .rid                    = RDT_RESOURCE_L3CODE,
                .name                   = "L3CODE",
                .domains                = domain_init(RDT_RESOURCE_L3CODE),
-               .msr_base               = IA32_L3_CBM_BASE,
+               .msr_base               = MSR_IA32_L3_CBM_BASE,
                .msr_update             = cat_wrmsr,
                .cache_level            = 3,
                .cache = {
@@ -123,7 +120,7 @@ struct rdt_resource rdt_resources_all[] = {
                .rid                    = RDT_RESOURCE_L2,
                .name                   = "L2",
                .domains                = domain_init(RDT_RESOURCE_L2),
-               .msr_base               = IA32_L2_CBM_BASE,
+               .msr_base               = MSR_IA32_L2_CBM_BASE,
                .msr_update             = cat_wrmsr,
                .cache_level            = 2,
                .cache = {
@@ -140,7 +137,7 @@ struct rdt_resource rdt_resources_all[] = {
                .rid                    = RDT_RESOURCE_L2DATA,
                .name                   = "L2DATA",
                .domains                = domain_init(RDT_RESOURCE_L2DATA),
-               .msr_base               = IA32_L2_CBM_BASE,
+               .msr_base               = MSR_IA32_L2_CBM_BASE,
                .msr_update             = cat_wrmsr,
                .cache_level            = 2,
                .cache = {
@@ -157,7 +154,7 @@ struct rdt_resource rdt_resources_all[] = {
                .rid                    = RDT_RESOURCE_L2CODE,
                .name                   = "L2CODE",
                .domains                = domain_init(RDT_RESOURCE_L2CODE),
-               .msr_base               = IA32_L2_CBM_BASE,
+               .msr_base               = MSR_IA32_L2_CBM_BASE,
                .msr_update             = cat_wrmsr,
                .cache_level            = 2,
                .cache = {
@@ -174,7 +171,7 @@ struct rdt_resource rdt_resources_all[] = {
                .rid                    = RDT_RESOURCE_MBA,
                .name                   = "MB",
                .domains                = domain_init(RDT_RESOURCE_MBA),
-               .msr_base               = IA32_MBA_THRTL_BASE,
+               .msr_base               = MSR_IA32_MBA_THRTL_BASE,
                .msr_update             = mba_wrmsr,
                .cache_level            = 3,
                .parse_ctrlval          = parse_bw,
@@ -211,9 +208,10 @@ static inline void cache_alloc_hsw_probe(void)
        struct rdt_resource *r  = &rdt_resources_all[RDT_RESOURCE_L3];
        u32 l, h, max_cbm = BIT_MASK(20) - 1;
 
-       if (wrmsr_safe(IA32_L3_CBM_BASE, max_cbm, 0))
+       if (wrmsr_safe(MSR_IA32_L3_CBM_BASE, max_cbm, 0))
                return;
-       rdmsr(IA32_L3_CBM_BASE, l, h);
+
+       rdmsr(MSR_IA32_L3_CBM_BASE, l, h);
 
        /* If all the bits were set in MSR, return success */
        if (l != max_cbm)

diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/resctrl/internal.h
index eeaee05..fb26d34 100644 (file)
--- a/arch/x86/kernel/cpu/resctrl/internal.h
+++ b/arch/x86/kernel/cpu/resctrl/internal.h
@@ -6,15 +6,18 @@
 #include <linux/kernfs.h>
 #include <linux/jump_label.h>
 
-#define IA32_L3_QOS_CFG                0xc81
-#define IA32_L2_QOS_CFG                0xc82
-#define IA32_L3_CBM_BASE       0xc90
-#define IA32_L2_CBM_BASE       0xd10
-#define IA32_MBA_THRTL_BASE    0xd50
+#define MSR_IA32_L3_QOS_CFG            0xc81
+#define MSR_IA32_L2_QOS_CFG            0xc82
+#define MSR_IA32_L3_CBM_BASE           0xc90
+#define MSR_IA32_L2_CBM_BASE           0xd10
+#define MSR_IA32_MBA_THRTL_BASE                0xd50
 
-#define L3_QOS_CDP_ENABLE      0x01ULL
+#define MSR_IA32_QM_CTR                        0x0c8e
+#define MSR_IA32_QM_EVTSEL             0x0c8d
 
-#define L2_QOS_CDP_ENABLE      0x01ULL
+#define L3_QOS_CDP_ENABLE              0x01ULL
+
+#define L2_QOS_CDP_ENABLE              0x01ULL
 
 /*
  * Event IDs are used to program IA32_QM_EVTSEL before reading event
@@ -29,6 +32,8 @@
 #define MBM_CNTR_WIDTH                 24
 #define MBM_OVERFLOW_INTERVAL          1000
 #define MAX_MBA_BW                     100u
+#define MBA_IS_LINEAR                  0x4
+#define MBA_MAX_MBPS                   U32_MAX
 
 #define RMID_VAL_ERROR                 BIT_ULL(63)
 #define RMID_VAL_UNAVAIL               BIT_ULL(62)

diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/resctrl/monitor.c
index ebf408d..f33f11f 100644 (file)
--- a/arch/x86/kernel/cpu/resctrl/monitor.c
+++ b/arch/x86/kernel/cpu/resctrl/monitor.c
@@ -28,9 +28,6 @@
 #include <asm/cpu_device_id.h>
 #include "internal.h"
 
-#define MSR_IA32_QM_CTR                0x0c8e
-#define MSR_IA32_QM_EVTSEL             0x0c8d
-
 struct rmid_entry {
        u32                             rmid;
        int                             busy;

diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/resctrl/rdtgroup.c
index 2bf1f32..cf15909 100644 (file)
--- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c
+++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c
@@ -1722,14 +1722,14 @@ static void l3_qos_cfg_update(void *arg)
 {
        bool *enable = arg;
 
-       wrmsrl(IA32_L3_QOS_CFG, *enable ? L3_QOS_CDP_ENABLE : 0ULL);
+       wrmsrl(MSR_IA32_L3_QOS_CFG, *enable ? L3_QOS_CDP_ENABLE : 0ULL);
 }
 
 static void l2_qos_cfg_update(void *arg)
 {
        bool *enable = arg;
 
-       wrmsrl(IA32_L2_QOS_CFG, *enable ? L2_QOS_CDP_ENABLE : 0ULL);
+       wrmsrl(MSR_IA32_L2_QOS_CFG, *enable ? L2_QOS_CDP_ENABLE : 0ULL);
 }
 
 static inline bool is_mba_linear(void)