MIPS: smp-cps: Disable coherence setup for unsupported ISA

We don't know how to do coherence setup on ISA before MIPS
Release 1.

As CPS support only servers simulation purpose on those cores,
and simulators are always coherent, just disable initialization
code and provide user a warning in case coherence is not setup
properly.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S
index 8ef492d..64ecfda 100644 (file)
--- a/arch/mips/kernel/cps-vec.S
+++ b/arch/mips/kernel/cps-vec.S
@@ -116,6 +116,8 @@ not_nmi:
        li      t0, ST0_CU1 | ST0_CU0 | ST0_BEV | STATUS_BITDEPS
        mtc0    t0, CP0_STATUS
 
+       /* We don't know how to do coherence setup on earlier ISA */
+#if MIPS_ISA_REV > 0
        /* Skip cache & coherence setup if we're already coherent */
        lw      s7, GCR_CL_COHERENCE_OFS(s1)
        bnez    s7, 1f
@@ -129,6 +131,7 @@ not_nmi:
        li      t0, 0xff
        sw      t0, GCR_CL_COHERENCE_OFS(s1)
        ehb
+#endif /* MIPS_ISA_REV > 0 */
 
        /* Set Kseg0 CCA to that in s0 */
 1:     mfc0    t0, CP0_CONFIG
@@ -515,6 +518,7 @@ LEAF(mips_cps_boot_vpes)
         nop
        END(mips_cps_boot_vpes)
 
+#if MIPS_ISA_REV > 0
 LEAF(mips_cps_cache_init)
        /*
         * Clear the bits used to index the caches. Note that the architecture
@@ -588,6 +592,7 @@ dcache_done:
        jr      ra
         nop
        END(mips_cps_cache_init)
+#endif /* MIPS_ISA_REV > 0 */
 
 #if defined(CONFIG_MIPS_CPS_PM) && defined(CONFIG_CPU_PM)
 

diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c
index 4fc288b..f968a31 100644 (file)
--- a/arch/mips/kernel/smp-cps.c
+++ b/arch/mips/kernel/smp-cps.c
@@ -361,6 +361,8 @@ out:
 
 static void cps_init_secondary(void)
 {
+       int core = cpu_core(&current_cpu_data);
+
        /* Disable MT - we only want to run 1 TC per VPE */
        if (cpu_has_mipsmt)
                dmt();
@@ -376,6 +378,9 @@ static void cps_init_secondary(void)
                BUG_ON(ident != mips_cm_vp_id(smp_processor_id()));
        }
 
+       if (core > 0 && !read_gcr_cl_coherence())
+               pr_warn("Core %u is not in coherent domain\n", core);
+
        if (cpu_has_veic)
                clear_c0_status(ST0_IM);
        else