wifi/bt: add wifi bt config [1/1]

PD#156734: wifi/bt: add wifi bt config

1. add wifi/bt configure

2. set pwm e for 32k clock

3. enable cts/rts of uart_a

Change-Id: I94800030a95119ed8ff0c60171faa2cca8eca287
Signed-off-by: Weiguang.ruan <Weiguang.ruan@amlogic.com>

diff --git a/arch/arm64/boot/dts/amlogic/g12a_skt.dts b/arch/arm64/boot/dts/amlogic/g12a_skt.dts
index 2433a87..550e640 100644 (file)
--- a/arch/arm64/boot/dts/amlogic/g12a_skt.dts
+++ b/arch/arm64/boot/dts/amlogic/g12a_skt.dts
@@ -136,6 +136,39 @@
                };
        };
 
+       bt-dev{
+               compatible = "amlogic, bt-dev";
+               dev_name = "bt-dev";
+               status = "okay";
+               gpio_reset = <&gpio       GPIOX_17       GPIO_ACTIVE_HIGH>;
+       };
+
+       wifi{
+               compatible = "amlogic, aml_wifi";
+               dev_name = "aml_wifi";
+               status = "okay";
+               interrupt_pin = <&gpio       GPIOX_7       GPIO_ACTIVE_HIGH>;
+               irq_trigger_type = "GPIO_IRQ_LOW";
+               power_on_pin = <&gpio       GPIOX_6       GPIO_ACTIVE_HIGH>;
+               dhd_static_buf; //if use bcm wifi, config dhd_static_buf
+               pinctrl-names = "default";
+               pinctrl-0 = <&wifi_32k_pins>;
+               pwm_config = <&wifi_pwm_conf>;
+       };
+
+       wifi_pwm_conf:wifi_pwm_conf{
+               pwm_channel1_conf {
+                       pwms = <&pwm_ef MESON_PWM_0 30040 0>;
+                       duty-cycle = <15020>;
+                       times = <10>;
+               };
+               pwm_channel2_conf {
+                       pwms = <&pwm_ef MESON_PWM_2 30030 0>;
+                       duty-cycle = <15015>;
+                       times = <12>;
+               };
+       };
+
        sd_emmc_b:sd@ffe05000 {
                status = "okay";
                compatible = "amlogic, meson-mmc-g12a";
@@ -274,7 +307,7 @@
                compatible = "amlogic, meson-uart";
                reg = <0x0 0xffd24000 0x0 0x18>;
                interrupts = <0 26 1>;
-               status = "disable";
+               status = "okay";
                clocks = <&xtal
                        &clkc CLKID_UART0>;
                clock-names = "clk_uart",
@@ -900,3 +933,7 @@
                pinctrl-0 = <&ao_b_uart_pins>;
        };
 };
+
+&pwm_ef {
+       status = "okay";
+};

diff --git a/arch/arm64/boot/dts/amlogic/mesong12a.dtsi b/arch/arm64/boot/dts/amlogic/mesong12a.dtsi
index 1ed8f65..8706294 100644 (file)
--- a/arch/arm64/boot/dts/amlogic/mesong12a.dtsi
+++ b/arch/arm64/boot/dts/amlogic/mesong12a.dtsi
@@ -621,7 +621,9 @@
        a_uart_pins:a_uart {
                mux {
                        groups = "uart_tx_a",
-                               "uart_rx_a";
+                               "uart_rx_a",
+                               "uart_cts_a",
+                               "uart_rts_a";
                        function = "uart_a";
                };
        };
@@ -641,4 +643,11 @@
                        function = "uart_c";
                };
        };
+
+       wifi_32k_pins:wifi_32k_pins {
+               mux {
+                       groups = "pwm_e";
+                       function = "pwm_e";
+               };
+       };
 };