drm/amdgpu: add xgmi perfmons for arcturus
authorJonathan Kim <jonathan.kim@amd.com>
Wed, 2 Sep 2020 03:59:21 +0000 (23:59 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 7 Oct 2020 18:44:40 +0000 (14:44 -0400)
Add xgmi perfmons for Arcturus.

v4: Align with patch 2 with struct improvements
v3: Align with patch 2 streamlining perf types versus event config types.
v2: Resend for re-review with alignment for v3 in patch 2.

Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
Tested-by: Chris Freehill <chris.freehill@amd.com>
Reviewed-by: Harish Kasiviswanathan <harish.kasiviswanathan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c
drivers/gpu/drm/amd/amdgpu/df_v3_6.c

index 6624e80..1b213c4 100644 (file)
@@ -33,6 +33,9 @@
 #define NUM_EVENT_TYPES_VEGA20         1
 #define NUM_EVENTS_VEGA20_XGMI         2
 #define NUM_EVENTS_VEGA20_MAX          NUM_EVENTS_VEGA20_XGMI
+#define NUM_EVENT_TYPES_ARCTURUS       1
+#define NUM_EVENTS_ARCTURUS_XGMI       6
+#define NUM_EVENTS_ARCTURUS_MAX                NUM_EVENTS_ARCTURUS_XGMI
 
 struct amdgpu_pmu_event_attribute {
        struct device_attribute attr;
@@ -172,6 +175,36 @@ static struct amdgpu_pmu_config df_vega20_config = {
        .num_types = 0
 };
 
+/* Arcturus events */
+static struct amdgpu_pmu_attr arcturus_events[NUM_EVENTS_ARCTURUS_MAX] = {
+       { .name = "xgmi_link0_data_outbound",
+                       .config = "event=0x7,instance=0x4b,umask=0x2" },
+       { .name = "xgmi_link1_data_outbound",
+                       .config = "event=0x7,instance=0x4c,umask=0x2" },
+       { .name = "xgmi_link2_data_outbound",
+                       .config = "event=0x7,instance=0x4d,umask=0x2" },
+       { .name = "xgmi_link3_data_outbound",
+                       .config = "event=0x7,instance=0x4e,umask=0x2" },
+       { .name = "xgmi_link4_data_outbound",
+                       .config = "event=0x7,instance=0x4f,umask=0x2" },
+       { .name = "xgmi_link5_data_outbound",
+                       .config = "event=0x7,instance=0x50,umask=0x2" }
+};
+
+static struct amdgpu_pmu_type arcturus_types[NUM_EVENT_TYPES_ARCTURUS] = {
+       { .type = AMDGPU_PMU_EVENT_CONFIG_TYPE_XGMI,
+                               .num_of_type = NUM_EVENTS_ARCTURUS_XGMI }
+};
+
+static struct amdgpu_pmu_config arcturus_config = {
+       .formats = amdgpu_pmu_formats,
+       .num_formats = ARRAY_SIZE(amdgpu_pmu_formats),
+       .events = arcturus_events,
+       .num_events = ARRAY_SIZE(arcturus_events),
+       .types = arcturus_types,
+       .num_types = ARRAY_SIZE(arcturus_types)
+};
+
 /* initialize perf counter */
 static int amdgpu_perf_event_init(struct perf_event *event)
 {
@@ -603,6 +636,22 @@ int amdgpu_pmu_init(struct amdgpu_device *adev)
                }
 
                break;
+       case CHIP_ARCTURUS:
+               pmu_entry = create_pmu_entry(adev, AMDGPU_PMU_PERF_TYPE_ALL,
+                                               "", "amdgpu");
+               if (!pmu_entry)
+                       return -ENOMEM;
+
+               ret = init_pmu_entry_by_type_and_add(pmu_entry,
+                                                       &arcturus_config);
+
+               if (ret) {
+                       kfree(pmu_entry);
+                       return -ENOMEM;
+               }
+
+               break;
+
        default:
                return 0;
        };
index 6e57ae9..6b4b30a 100644 (file)
@@ -513,6 +513,7 @@ static int df_v3_6_pmc_start(struct amdgpu_device *adev, uint64_t config,
 
        switch (adev->asic_type) {
        case CHIP_VEGA20:
+       case CHIP_ARCTURUS:
                if (is_add)
                        return df_v3_6_pmc_add_cntr(adev, config);
 
@@ -554,6 +555,7 @@ static int df_v3_6_pmc_stop(struct amdgpu_device *adev, uint64_t config,
 
        switch (adev->asic_type) {
        case CHIP_VEGA20:
+       case CHIP_ARCTURUS:
                ret = df_v3_6_pmc_get_ctrl_settings(adev,
                        config,
                        counter_idx,
@@ -590,6 +592,7 @@ static void df_v3_6_pmc_get_count(struct amdgpu_device *adev,
 
        switch (adev->asic_type) {
        case CHIP_VEGA20:
+       case CHIP_ARCTURUS:
                df_v3_6_pmc_get_read_settings(adev, config, counter_idx,
                                                &lo_base_addr, &hi_base_addr);