@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 universal samsung s5pc100
@echo "CONFIG_ONENAND_U_BOOT = y" >> $(obj)include/config.mk
+s5pc100_smdkc100_config: unconfig
+# @echo "#define CONFIG_ONENAND_U_BOOT" > $(obj)include/config.h
+ @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 smdkc100 samsung s5pc100
+# @echo "CONFIG_ONENAND_U_BOOT = y" >> $(obj)include/config.mk
+
#########################################################################
## XScale Systems
#########################################################################
--- /dev/null
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y := smdkc100.o onenand.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(SOBJS) $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(SOBJS) $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+#
+# SAMSUNG SMDK6400 board with mDirac3 (ARM1176) cpu
+#
+# see http://www.samsung.com/ for more information on SAMSUNG
+
+# On SMDK6400 we use the 64 MB SDRAM bank at
+#
+# 0x50000000 to 0x58000000
+#
+# Linux-Kernel is expected to be at 0x50008000, entry 0x50008000
+#
+# we load ourselves to 0x57e00000 without MMU
+# with MMU, load address is changed to 0xc7e00000
+#
+# download area is 0x5000c000
+
+TEXT_BASE = 0x24800000
--- /dev/null
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 2009 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/cpu.h>
+
+#ifdef CONFIG_SERIAL0
+#define UART_CONSOLE_BASE UARTx_OFFSET(0)
+#elif defined(CONFIG_SERIAL1)
+#define UART_CONSOLE_BASE UARTx_OFFSET(1)
+#elif defined(CONFIG_SERIAL2)
+#define UART_CONSOLE_BASE UARTx_OFFSET(2)
+#else
+#define UART_CONSOLE_BASE UARTx_OFFSET(3)
+#endif
+
+/*
+ * Register usages:
+ *
+ * r5 has zero always
+ */
+
+_TEXT_BASE:
+ .word TEXT_BASE
+
+ .globl lowlevel_init
+lowlevel_init:
+ mov r9, lr
+
+ /* Disable Watchdog */
+ ldr r0, =S5P_WATCHDOG_BASE(0x0) @0xEA200000
+ orr r0, r0, #0x0
+ mov r5, #0
+ str r5, [r0]
+
+#ifndef CONFIG_ONENAND_IPL
+ /* setting SRAM */
+ ldr r0, =S5P_SROMC_BASE(0x0)
+ ldr r1, =0x9
+ str r1, [r0]
+#endif
+
+ /* S5PC100 has 3 groups of interrupt sources */
+ ldr r0, =S5P_VIC0_BASE(0x0) @0xE4000000
+ ldr r1, =S5P_VIC1_BASE(0x0) @0xE4000000
+ ldr r2, =S5P_VIC2_BASE(0x0) @0xE4000000
+
+ /* Disable all interrupts (VIC0, VIC1 and VIC2) */
+ mvn r3, #0x0
+ str r3, [r0, #VIC_INTENCLEAR_OFFSET]
+ str r3, [r1, #VIC_INTENCLEAR_OFFSET]
+ str r3, [r2, #VIC_INTENCLEAR_OFFSET]
+
+#ifndef CONFIG_ONENAND_IPL
+ /* Set all interrupts as IRQ */
+ str r5, [r0, #VIC_INTSELECT_OFFSET]
+ str r5, [r1, #VIC_INTSELECT_OFFSET]
+ str r5, [r2, #VIC_INTSELECT_OFFSET]
+
+ /* Pending Interrupt Clear */
+ str r5, [r0, #VIC_INTADDRESS_OFFSET]
+ str r5, [r1, #VIC_INTADDRESS_OFFSET]
+ str r5, [r2, #VIC_INTADDRESS_OFFSET]
+#endif
+
+ /* init system clock */
+ bl system_clock_init
+
+#ifndef CONFIG_ONENAND_IPL
+ /* for UART */
+ bl uart_asm_init
+#endif
+
+ /* Memory subsystem address 0xe0200200 */
+ ldr r0, =S5P_MEM_SYS_CFG
+ str r5, [r0]
+
+ /* DRAM I/O Drive-Strength */
+ ldr r0, =S5P_MP_0DRV
+ ldr r1, =0x5555
+ str r1, [r0, #S5P_MP_0_OFFSET]
+ str r1, [r0, #S5P_MP_1_OFFSET]
+ str r1, [r0, #S5P_MP_2_OFFSET]
+ str r1, [r0, #S5P_MP_3_OFFSET]
+ str r1, [r0, #S5P_MP_4_OFFSET]
+ str r1, [r0, #S5P_MP_5_OFFSET]
+ str r1, [r0, #S5P_MP_6_OFFSET]
+ str r1, [r0, #S5P_MP_7_OFFSET]
+
+#ifdef CONFIG_ONENAND_IPL
+ bl mem_ctrl_asm_init
+
+ /* Wakeup support. Don't know if it's going to be used, untested. */
+ ldr r0, =S5P_OTHERS_BASE
+ ldr r1, [r0]
+ bic r1, r1, #0xfffffff7
+ cmp r1, #0x8
+ beq wakeup_reset
+#endif
+
+1:
+ mov lr, r9
+ mov pc, lr
+
+#ifdef CONFIG_ONENAND_IPL
+wakeup_reset:
+
+ /* Clear wakeup status register */
+ ldr r0, =S5P_WAKEUP_STAT
+ ldr r1, [r0]
+ str r1, [r0]
+
+ /* Load return address and jump to kernel */
+ ldr r0, =S5P_INFORM0
+
+ /* r1 = physical address of s5pc100_cpu_resume function */
+ ldr r1, [r0]
+
+ /* Jump to kernel (sleep-s5pc100.S) */
+ mov pc, r1
+ nop
+ nop
+#endif
+
+/*
+ * system_clock_init: Initialize core clock and bus clock.
+ * void system_clock_init(void)
+ */
+system_clock_init:
+ ldr r8, =S5P_PA_CLK @ 0xE0100000
+
+ /* Set Clock divider */
+ ldr r1, =0x00011110
+ str r1, [r8, #0x304]
+ ldr r1, =0x1
+ str r1, [r8, #0x308]
+ ldr r1, =0x00011301
+ str r1, [r8, #0x300]
+
+ /* Set Lock Time */
+ ldr r1, =0xe10 @ Locktime : 0xe10 = 3600
+ str r1, [r8, #0x000] @ S5P_APLL_LOCK
+ str r1, [r8, #0x004] @ S5P_MPLL_LOCK
+ str r1, [r8, #0x008] @ S5P_EPLL_LOCK
+
+ /* S5P_APLL_CON */
+ ldr r1, =0x81bc0400 @ SDIV 0, PDIV 4, MDIV 444 (1332MHz)
+ str r1, [r8, #0x100]
+ /* S5P_MPLL_CON */
+ ldr r1, =0x80590201 @ SDIV 1, PDIV 2, MDIV 89 (267MHz)
+ str r1, [r8, #0x104]
+ /* S5P_EPLL_CON */
+ ldr r1, =0x80870303 @ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
+ str r1, [r8, #0x108]
+ /* S5P_HPLL_CON */
+ ldr r1, =0x80600603
+ str r1, [r8, #0x10C]
+
+ /* Set Source Clock */
+ ldr r1, =0x1111 @ A, M, E, HPLL Muxing
+ str r1, [r8, #0x200] @ S5P_CLK_SRC0
+
+ ldr r1, =0x1000001 @ Uart Clock & CLK48M Muxing
+ str r1, [r8, #0x204] @ S5P_CLK_SRC1
+
+ ldr r1, =0x9000 @ ARMCLK/4
+ str r1, [r8, #0x400] @ S5P_CLK_OUT
+
+ /* wait at least 200us to stablize all clock */
+ mov r2, #0x10000
+1: subs r2, r2, #1
+ bne 1b
+
+ mov pc, lr
+
+#ifndef CONFIG_ONENAND_IPL
+/*
+ * uart_asm_init: Initialize UART's pins
+ */
+uart_asm_init:
+ /* set GPIO to enable UART */
+ ldr r0, =S5P_GPIO_A1_CON
+ ldr r1, =0x22
+ str r1, [r0]
+
+ /* uart_sel GPK0[5] */
+ ldr r0, =S5P_GPIO_K0_CON
+ ldr r1, [r0]
+ bic r1, r1, #0xf00000
+ orr r1, r1, #0x100000
+ str r1, [r0]
+
+ ldr r0, =S5P_GPIO_K0_PULL
+ ldr r1, [r0]
+ bic r1, r1, #0xc00
+ orr r1, r1, #0x800
+ str r1, [r0]
+
+ ldr r0, =S5P_GPIO_K0_DAT
+ ldr r1, [r0]
+ orr r1, r1, #0x20
+ str r1, [r0]
+
+ mov pc, lr
+#endif
--- /dev/null
+/*
+ * OneNAND initialization at U-Boot
+ */
+
+#include <common.h>
+#include <linux/mtd/compat.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/onenand.h>
+
+#include <onenand_uboot.h>
+
+#include <s5pc1xx-onenand.h>
+
+#include <asm/io.h>
+
+#define DPRINTK(format, args...) \
+do { \
+ printk("%s[%d]: " format "\n", __func__, __LINE__, ##args); \
+} while (0)
+
+void onenand_board_init(struct mtd_info *mtd)
+{
+ struct onenand_chip *this = mtd->priv;
+ int value;
+
+ this->base = (void *)CONFIG_SYS_ONENAND_BASE;
+
+ s3c_onenand_init(mtd);
+
+ /* D0 Domain clock gating */
+ value = S5P_CLK_GATE_D00_REG;
+ value &= ~(1 << 2);
+ value |= (1 << 2);
+ S5P_CLK_GATE_D00_REG = value;
+
+ value = S5P_CLK_SRC0_REG;
+ value &= ~(1 << 24);
+ value &= ~(1 << 20);
+ S5P_CLK_SRC0_REG = value;
+
+ /* SYSCON */
+ value = S5P_CLK_DIV1_REG;
+ value &= ~(3 << 16);
+ value |= (1 << 16);
+ S5P_CLK_DIV1_REG = value;
+
+ WATCHDOG_CNT_LOW_REG = 0xffff;
+ WATCHDOG_CNT_HI_REG = 0xffff;
+
+ INT_ERR_MASK0_REG = 0x1fff;
+// INT_PIN_ENABLE0_REG = (1 << 0); /* Enable */
+
+ MEM_RESET0_REG = ONENAND_MEM_RESET_COLD;
+
+ while (!(INT_ERR_STAT0_REG & RST_CMP))
+ continue;
+
+ INT_ERR_ACK0_REG |= RST_CMP;
+ INT_ERR_ACK0_REG = INT_ERR_STAT0_REG;
+
+ ACC_CLOCK0_REG = 0x3;
+
+#if 0
+ /* MEM_CFG0_REG = 0xf0e0; */
+ MEM_CFG0_REG =
+#ifdef CONFIG_SYNC_MODE
+#error not yet supported...
+ ONENAND_SYS_CFG1_SYNC_READ |
+#endif
+ ONENAND_SYS_CFG1_BRL_4 |
+ ONENAND_SYS_CFG1_BL_16 |
+ ONENAND_SYS_CFG1_RDY |
+ ONENAND_SYS_CFG1_INT |
+ ONENAND_SYS_CFG1_IOBE
+ ;
+#else
+ MEM_CFG0_REG &= ~ONENAND_SYS_CFG1_SYNC_READ;
+ MEM_CFG0_REG |= ONENAND_SYS_CFG1_BL_16;
+ MEM_CFG0_REG |= ONENAND_SYS_CFG1_HF;
+#endif
+
+ s3c_set_width_regs(this);
+}
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+static inline void delay(unsigned long loops)
+{
+ __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
+ "bne 1b"
+ : "=r" (loops) : "0" (loops));
+}
+
+int board_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_arch_number = MACH_TYPE;
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ return 0;
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+ printf("Board:\tSMDKC100(S5PC100)\n");
+ return 0;
+}
+#endif
+
+void raise(void)
+{
+}
+
+#ifdef CONFIG_CMD_USBDOWN
+#include <i2c.h>
+
+int usb_board_init(void)
+{
+ uchar val[2] ={0,};
+
+ /* PMIC */
+ if (i2c_read(0x66, 0, 1, val, 2)) {
+ printf("i2c_read error\n");
+ return 1;
+ }
+
+ val[0] |= (1 << 3);
+ val[1] |= (1 << 5);
+
+ if (i2c_write(0x66, 0, 1, val, 2)) {
+ printf("i2c_write error\n");
+ return 1;
+ }
+}
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/arm_cortexa8/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) }
+ __exidx_start = .;
+ .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) }
+ __exidx_end = .;
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Gary Jennejohn <gj@denx.de>
+ * David Mueller <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ *
+ * (C) Copyright 2009
+ * Inki Dae, SAMSUNG Electronics, <inki.dae@samsung.com>
+ * Minkyu Kang, SAMSUNG Electronics, <mk7.kang@samsung.com>
+ *
+ * Configuation settings for the SAMSUNG SMDK6400(mDirac-III) board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+#include <asm/sizes.h>
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
+#define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */
+#define CONFIG_S5PC1XX 1 /* which is in a S5PC1XX Family */
+#define CONFIG_S5PC100 1 /* which is in a S5PC100 */
+#define CONFIG_TICKERTAPE 1 /* working with TickerTape */
+
+#include <asm/arch/cpu.h> /* get chip and board defs */
+
+/*
+ * Architecture magic and machine type
+ */
+#define MACH_TYPE 1826
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#undef CONFIG_SKIP_RELOCATE_UBOOT
+
+/* input clock of PLL: TickerTape has 12MHz input clock */
+#define CONFIG_SYS_CLK_FREQ 12000000
+
+/* DRAM Base */
+#define CONFIG_SYS_SDRAM_BASE 0x20000000
+
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_EDITING
+
+/*
+ * Size of malloc() pool
+ * 1MB = 0x100000, 0x100000 = 1024 * 1024
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_1M)
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes for initial data */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL0 1 /* we use SERIAL 0 on SMDKC100 */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_L2_OFF
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_BOOTD
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_XIMG
+#undef CONFIG_CMD_NAND
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_NET
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_ONENAND
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_MTDPARTS
+
+#define CONFIG_BOOTDELAY 10
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#define CONFIG_MTD_PARTITIONS
+
+#define MTDIDS_DEFAULT "onenand0=s3c-onenand"
+#define MTDPARTS_DEFAULT "mtdparts=s3c-onenand:256k(bootloader)"\
+ ",128k@0x40000(params)"\
+ ",2m@0x60000(kernel)"\
+ ",16m@0x260000(test)"\
+ ",-(UBI)"
+
+#define NORMAL_MTDPARTS_DEFAULT MTDPARTS_DEFAULT
+
+#if 1
+#define CONFIG_BOOTCOMMAND "run ubifsboot"
+#else
+#define CONFIG_BOOTCOMMAND "bootm 0x21008000"
+#endif
+
+#define CONFIG_COMMON_BOOT "console=ttySAC2,115200n8" \
+ " mem=128M " \
+ " " MTDPARTS_DEFAULT
+
+#define CONFIG_BOOTARGS "root=/dev/mtdblock5 ubi.mtd=4" \
+ " rootfstype=cramfs " CONFIG_COMMON_BOOT
+
+#ifdef CONFIG_USE_BIG_UBOOT
+#define CONFIG_UPDATEB "updateb=onenand erase 0x0 0x40000;" \
+ " onenand write 0x22008000 0x0 0x40000\0"
+#else
+#define CONFIG_UPDATEB "updateb=onenand erase 0x0 0x40000;" \
+ " onenand write 0x22008000 0x0 0x20000;" \
+ " onenand write 0x22008000 0x20000 0x20000\0"
+#endif
+
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_UPDATEB \
+ "updatek=onenand erase 0x60000 0x200000;" \
+ " onenand write 0x21008000 0x60000 0x200000\0" \
+ "updateu=onenand erase block 147-4095;" \
+ " onenand write 0x22000000 0x1260000 0x8C0000\0" \
+ "bootk=onenand read 0x20007FC0 0x60000 0x200000;" \
+ " bootm 0x20007FC0\0" \
+ "flashboot=set bootargs root=/dev/mtdblock${bootblock}" \
+ " rootfstype=${rootfstype}" \
+ " ubi.mtd=${ubiblock} ${opts} " CONFIG_COMMON_BOOT "; run bootk\0" \
+ "ubifsboot=set bootargs root=ubi0!initrd.ubifs rootfstype=ubifs" \
+ " ubi.mtd=${ubiblock} ${opts} " CONFIG_COMMON_BOOT "; run bootk\0" \
+ "boottrace=setenv opts initcall_debug; run bootcmd\0" \
+ "android=set bootargs root=ubi0!ramdisk ubi.mtd=${ubiblock}" \
+ " rootfstype=ubifs init=/init.sh " CONFIG_COMMON_BOOT "; run bootk\0" \
+ "nfsboot=set bootargs root=/dev/nfs ubi.mtd=${ubiblock}" \
+ " nfsroot=${nfsroot},nolock ip=${ipaddr}:${serverip}:${gatewayip}:" \
+ "${netmask}:nowplus:usb0:off " CONFIG_COMMON_BOOT "; run bootk\0" \
+ "rootfstype=cramfs\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "meminfo=mem=128M\0" \
+ "nfsroot=/nfsroot/arm\0" \
+ "bootblock=5\0" \
+ "ubiblock=4\0" \
+ "ubi=enabled"
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_PROMPT "SMDKC100 # " /* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5e00000)
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x5e00000)
+
+#define CONFIG_SYS_HZ 2085900 /* at PCLK 66.75MHz */
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE SZ_256K /* regular stack 256KB, 0x40000 */
+
+/* TickerTape has 1 banks of DRAM, we use only one in U-Boot */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE SZ_128M /* 0x8000000, 128 MB in Bank #1 */
+
+#define CONFIG_SYS_MONITOR_BASE 0x00000000
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_NO_FLASH 1
+
+#define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */
+
+#define CONFIG_IDENT_STRING " for SMDKC100"
+
+#if !defined(CONFIG_NAND_SPL) && (TEXT_BASE >= 0xc0000000)
+#define CONFIG_ENABLE_MMU
+#endif
+
+#ifdef CONFIG_ENABLE_MMU
+#define CONFIG_SYS_MAPPED_RAM_BASE 0xc0000000
+#else
+#define CONFIG_SYS_MAPPED_RAM_BASE CONFIG_SYS_SDRAM_BASE
+#endif
+
+/*-----------------------------------------------------------------------
+ * Boot configuration (define only one of next 3)
+ */
+#define CONFIG_ENV_IS_IN_ONENAND 1
+#define CONFIG_ENV_SIZE SZ_128K /* 128KB, 0x20000 */
+#define CONFIG_ENV_ADDR SZ_256K /* 256KB, 0x40000 */
+#define CONFIG_ENV_OFFSET SZ_256K /* 256KB, 0x40000 */
+
+#define CONFIG_USE_ONENAND_BOARD_INIT
+#define CONFIG_SYS_ONENAND_BASE 0x00000000
+
+#define CONFIG_DOS_PARTITION 1
+
+/* I2C */
+#define CONFIG_DRIVER_S5PC1XX_I2C
+#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C_SPEED 50000
+#define CONFIG_SYS_I2C_SLAVE 0xFE
+#define CONFIG_SYS_I2C_0 1
+
+/* USB Downloader */
+#define CONFIG_CMD_USBDOWN
+#define CONFIG_SAMSUNG_USB
+#define CONFIG_OTG_CLK_OSCC
+#define USBDOWN_RAM_START CONFIG_SYS_SDRAM_BASE
+
+#endif /* __CONFIG_H */
/*
* select serial console configuration
*/
-#define CONFIG_SERIAL2 1 /* we use SERIAL 2 on S5PC100 */
+#define CONFIG_SERIAL0 1 /* we use SERIAL 2 on S5PC100 */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#ifdef CONFIG_SYS_HUSH_PARSER
--- /dev/null
+#
+# Samsung TickerTape(S5PC100) board OneNAND IPL
+#
+# Copyright (C) 2009 Samsung Electronics
+# Minkyu Kang <mk7.kang@samsung.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+
+include $(TOPDIR)/config.mk
+#TEXT_BASE = 0x22008000
+#TEXT_BASE = 0x00034000
+TEXT_BASE = 0xD0034000
+TEXT_BASE2K = 0xD0034800
+TEXT_BASE4K = 0xD0035000
+
+LDSCRIPT= $(TOPDIR)/onenand_ipl/board/$(BOARDDIR)/u-boot-onenand.lds
+LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
+AFLAGS += -DCONFIG_ONENAND_IPL -g
+CFLAGS += -DCONFIG_ONENAND_IPL -g
+OBJCFLAGS += --gap-fill=0x00
+
+SOBJS := lowlevel_init.o
+SOBJS += start.o cpu_init.o
+COBJS += onenand_read.o
+COBJS += onenand_boot.o
+
+SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+__OBJS := $(SOBJS) $(COBJS)
+LNDIR := $(OBJTREE)/onenand_ipl/board/$(BOARDDIR)
+
+onenandobj := $(OBJTREE)/onenand_ipl/
+
+ALL = $(onenandobj)onenand-ipl $(onenandobj)onenand-ipl.bin $(onenandobj)onenand-ipl-2k.bin $(onenandobj)onenand-ipl-4k.bin
+
+all: $(obj).depend $(ALL)
+
+$(onenandobj)onenand-ipl-2k.bin: $(onenandobj)onenand-ipl
+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(TEXT_BASE2K) -O binary $< $@
+
+$(onenandobj)onenand-ipl-4k.bin: $(onenandobj)onenand-ipl
+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(TEXT_BASE4K) -O binary $< $@
+
+$(onenandobj)onenand-ipl.bin: $(onenandobj)onenand-ipl
+ $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+
+$(onenandobj)onenand-ipl: $(OBJS)
+ cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
+ -Map $@.map -o $@
+
+# create symbolic links from common files
+
+# from cpu directory
+$(obj)start.S:
+ @rm -f $@
+ ln -s $(SRCTREE)/cpu/$(CPU)/start.S $@
+
+$(obj)cpu_init.S:
+ ln -s $(SRCTREE)/cpu/$(CPU)/s5pc100/cpu_init.S $@
+
+$(obj)lowlevel_init.S:
+ ln -sf $(SRCTREE)/board/$(BOARDDIR)/lowlevel_init.S $@
+
+# from onenand_ipl directory
+$(obj)onenand_ipl.h:
+ @rm -f $@
+ ln -s $(SRCTREE)/onenand_ipl/onenand_ipl.h $@
+
+$(obj)onenand_boot.c: $(obj)onenand_ipl.h
+ @rm -f $@
+ ln -s $(SRCTREE)/onenand_ipl/onenand_boot.c $@
+
+$(obj)onenand_read.c: $(obj)onenand_ipl.h
+ @rm -f $@
+ ln -s $(SRCTREE)/onenand_ipl/onenand_read.c $@
+
+#########################################################################
+
+$(obj)%.o: $(obj)%.S
+ $(CC) $(AFLAGS) -c -o $@ $<
+
+$(obj)%.o: $(obj)$.c
+ $(CC) $(CFLAGS) -c -o $@ $<
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+clean:
+ rm onenand_boot.c onenand_read.c
+
+#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2005-2008 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * Derived from X-loader
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
projects / kernel / u-boot.git / commitdiff