mei: add support for graphics system controller (gsc) devices
authorTomas Winkler <tomas.winkler@intel.com>
Tue, 19 Apr 2022 19:33:09 +0000 (12:33 -0700)
committerDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Thu, 21 Apr 2022 18:34:09 +0000 (11:34 -0700)
GSC is a graphics system controller, based on CSE, it provides
a chassis controller for graphics discrete cards, as well as it
supports media protection on selected devices.

mei_gsc binds to a auxiliary devices exposed by Intel discrete
driver i915.

v2: fix error check in mei_gsc_probe
v3: update MODULE_LICENSE ("GPL" is preferred over "GPL v2" and they
    both map to GPL version 2)

Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> #v3
Link: https://patchwork.freedesktop.org/patch/msgid/20220419193314.526966-3-daniele.ceraolospurio@intel.com
drivers/misc/mei/Kconfig
drivers/misc/mei/Makefile
drivers/misc/mei/gsc-me.c [new file with mode: 0644]
drivers/misc/mei/hw-me.c
drivers/misc/mei/hw-me.h

index 0e0bcd0..d21486d 100644 (file)
@@ -46,6 +46,20 @@ config INTEL_MEI_TXE
          Supported SoCs:
          Intel Bay Trail
 
+config INTEL_MEI_GSC
+       tristate "Intel MEI GSC embedded device"
+       depends on INTEL_MEI
+       depends on INTEL_MEI_ME
+       depends on X86 && PCI
+       depends on DRM_I915
+       help
+         Intel auxiliary driver for GSC devices embedded in Intel graphics devices.
+
+         An MEI device here called GSC can be embedded in an
+         Intel graphics devices, to support a range of chassis
+         tasks such as graphics card firmware update and security
+         tasks.
+
 source "drivers/misc/mei/hdcp/Kconfig"
 source "drivers/misc/mei/pxp/Kconfig"
 
index d8e5165..fb740d7 100644 (file)
@@ -18,6 +18,9 @@ obj-$(CONFIG_INTEL_MEI_ME) += mei-me.o
 mei-me-objs := pci-me.o
 mei-me-objs += hw-me.o
 
+obj-$(CONFIG_INTEL_MEI_GSC) += mei-gsc.o
+mei-gsc-objs := gsc-me.o
+
 obj-$(CONFIG_INTEL_MEI_TXE) += mei-txe.o
 mei-txe-objs := pci-txe.o
 mei-txe-objs += hw-txe.o
diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c
new file mode 100644 (file)
index 0000000..c474094
--- /dev/null
@@ -0,0 +1,194 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright(c) 2019-2022, Intel Corporation. All rights reserved.
+ *
+ * Intel Management Engine Interface (Intel MEI) Linux driver
+ */
+
+#include <linux/module.h>
+#include <linux/mei_aux.h>
+#include <linux/device.h>
+#include <linux/irqreturn.h>
+#include <linux/jiffies.h>
+#include <linux/ktime.h>
+#include <linux/delay.h>
+#include <linux/pm_runtime.h>
+
+#include "mei_dev.h"
+#include "hw-me.h"
+#include "hw-me-regs.h"
+
+#include "mei-trace.h"
+
+#define MEI_GSC_RPM_TIMEOUT 500
+
+static int mei_gsc_read_hfs(const struct mei_device *dev, int where, u32 *val)
+{
+       struct mei_me_hw *hw = to_me_hw(dev);
+
+       *val = ioread32(hw->mem_addr + where + 0xC00);
+
+       return 0;
+}
+
+static int mei_gsc_probe(struct auxiliary_device *aux_dev,
+                        const struct auxiliary_device_id *aux_dev_id)
+{
+       struct mei_aux_device *adev = auxiliary_dev_to_mei_aux_dev(aux_dev);
+       struct mei_device *dev;
+       struct mei_me_hw *hw;
+       struct device *device;
+       const struct mei_cfg *cfg;
+       int ret;
+
+       cfg = mei_me_get_cfg(aux_dev_id->driver_data);
+       if (!cfg)
+               return -ENODEV;
+
+       device = &aux_dev->dev;
+
+       dev = mei_me_dev_init(device, cfg);
+       if (!dev) {
+               ret = -ENOMEM;
+               goto err;
+       }
+
+       hw = to_me_hw(dev);
+       hw->mem_addr = devm_ioremap_resource(device, &adev->bar);
+       if (IS_ERR(hw->mem_addr)) {
+               dev_err(device, "mmio not mapped\n");
+               ret = PTR_ERR(hw->mem_addr);
+               goto err;
+       }
+
+       hw->irq = adev->irq;
+       hw->read_fws = mei_gsc_read_hfs;
+
+       dev_set_drvdata(device, dev);
+
+       ret = devm_request_threaded_irq(device, hw->irq,
+                                       mei_me_irq_quick_handler,
+                                       mei_me_irq_thread_handler,
+                                       IRQF_ONESHOT, KBUILD_MODNAME, dev);
+       if (ret) {
+               dev_err(device, "irq register failed %d\n", ret);
+               goto err;
+       }
+
+       pm_runtime_get_noresume(device);
+       pm_runtime_set_active(device);
+       pm_runtime_enable(device);
+
+       if (mei_start(dev)) {
+               dev_err(device, "init hw failure.\n");
+               ret = -ENODEV;
+               goto irq_err;
+       }
+
+       pm_runtime_set_autosuspend_delay(device, MEI_GSC_RPM_TIMEOUT);
+       pm_runtime_use_autosuspend(device);
+
+       ret = mei_register(dev, device);
+       if (ret)
+               goto register_err;
+
+       pm_runtime_put_noidle(device);
+       return 0;
+
+register_err:
+       mei_stop(dev);
+irq_err:
+       devm_free_irq(device, hw->irq, dev);
+
+err:
+       dev_err(device, "probe failed: %d\n", ret);
+       dev_set_drvdata(device, NULL);
+       return ret;
+}
+
+static void mei_gsc_remove(struct auxiliary_device *aux_dev)
+{
+       struct mei_device *dev;
+       struct mei_me_hw *hw;
+
+       dev = dev_get_drvdata(&aux_dev->dev);
+       if (!dev)
+               return;
+
+       hw = to_me_hw(dev);
+
+       mei_stop(dev);
+
+       mei_deregister(dev);
+
+       pm_runtime_disable(&aux_dev->dev);
+
+       mei_disable_interrupts(dev);
+       devm_free_irq(&aux_dev->dev, hw->irq, dev);
+}
+
+static int __maybe_unused mei_gsc_pm_suspend(struct device *device)
+{
+       struct mei_device *dev = dev_get_drvdata(device);
+
+       if (!dev)
+               return -ENODEV;
+
+       mei_stop(dev);
+
+       mei_disable_interrupts(dev);
+
+       return 0;
+}
+
+static int __maybe_unused mei_gsc_pm_resume(struct device *device)
+{
+       struct mei_device *dev = dev_get_drvdata(device);
+       int err;
+
+       if (!dev)
+               return -ENODEV;
+
+       err = mei_restart(dev);
+       if (err)
+               return err;
+
+       /* Start timer if stopped in suspend */
+       schedule_delayed_work(&dev->timer_work, HZ);
+
+       return 0;
+}
+
+static SIMPLE_DEV_PM_OPS(mei_gsc_pm_ops, mei_gsc_pm_suspend, mei_gsc_pm_resume);
+
+static const struct auxiliary_device_id mei_gsc_id_table[] = {
+       {
+               .name = "i915.mei-gsc",
+               .driver_data = MEI_ME_GSC_CFG,
+
+       },
+       {
+               .name = "i915.mei-gscfi",
+               .driver_data = MEI_ME_GSCFI_CFG,
+       },
+       {
+               /* sentinel */
+       }
+};
+MODULE_DEVICE_TABLE(auxiliary, mei_gsc_id_table);
+
+static struct auxiliary_driver mei_gsc_driver = {
+       .probe  = mei_gsc_probe,
+       .remove = mei_gsc_remove,
+       .driver = {
+               /* auxiliary_driver_register() sets .name to be the modname */
+               .pm = &mei_gsc_pm_ops,
+       },
+       .id_table = mei_gsc_id_table
+};
+module_auxiliary_driver(mei_gsc_driver);
+
+MODULE_AUTHOR("Intel Corporation");
+MODULE_ALIAS("auxiliary:i915.mei-gsc");
+MODULE_ALIAS("auxiliary:i915.mei-gscfi");
+MODULE_LICENSE("GPL");
index 719fee9..03945d3 100644 (file)
@@ -1226,6 +1226,7 @@ irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id)
        me_intr_disable(dev, hcsr);
        return IRQ_WAKE_THREAD;
 }
+EXPORT_SYMBOL_GPL(mei_me_irq_quick_handler);
 
 /**
  * mei_me_irq_thread_handler - function called after ISR to handle the interrupt
@@ -1326,6 +1327,7 @@ end:
        mutex_unlock(&dev->device_lock);
        return IRQ_HANDLED;
 }
+EXPORT_SYMBOL_GPL(mei_me_irq_thread_handler);
 
 static const struct mei_hw_ops mei_me_hw_ops = {
 
@@ -1440,6 +1442,12 @@ static bool mei_me_fw_type_sps_ign(const struct pci_dev *pdev)
 #define MEI_CFG_KIND_ITOUCH                     \
        .kind = "itouch"
 
+#define MEI_CFG_TYPE_GSC                        \
+       .kind = "gsc"
+
+#define MEI_CFG_TYPE_GSCFI                      \
+       .kind = "gscfi"
+
 #define MEI_CFG_FW_SPS_IGN                      \
        .quirk_probe = mei_me_fw_type_sps_ign
 
@@ -1572,6 +1580,18 @@ static const struct mei_cfg mei_me_pch15_sps_cfg = {
        MEI_CFG_FW_SPS_IGN,
 };
 
+/* Graphics System Controller */
+static const struct mei_cfg mei_me_gsc_cfg = {
+       MEI_CFG_TYPE_GSC,
+       MEI_CFG_PCH8_HFS,
+};
+
+/* Graphics System Controller Firmware Interface */
+static const struct mei_cfg mei_me_gscfi_cfg = {
+       MEI_CFG_TYPE_GSCFI,
+       MEI_CFG_PCH8_HFS,
+};
+
 /*
  * mei_cfg_list - A list of platform platform specific configurations.
  * Note: has to be synchronized with  enum mei_cfg_idx.
@@ -1592,6 +1612,8 @@ static const struct mei_cfg *const mei_cfg_list[] = {
        [MEI_ME_PCH12_SPS_ITOUCH_CFG] = &mei_me_pch12_itouch_sps_cfg,
        [MEI_ME_PCH15_CFG] = &mei_me_pch15_cfg,
        [MEI_ME_PCH15_SPS_CFG] = &mei_me_pch15_sps_cfg,
+       [MEI_ME_GSC_CFG] = &mei_me_gsc_cfg,
+       [MEI_ME_GSCFI_CFG] = &mei_me_gscfi_cfg,
 };
 
 const struct mei_cfg *mei_me_get_cfg(kernel_ulong_t idx)
@@ -1602,7 +1624,8 @@ const struct mei_cfg *mei_me_get_cfg(kernel_ulong_t idx)
                return NULL;
 
        return mei_cfg_list[idx];
-};
+}
+EXPORT_SYMBOL_GPL(mei_me_get_cfg);
 
 /**
  * mei_me_dev_init - allocates and initializes the mei device structure
@@ -1637,4 +1660,4 @@ struct mei_device *mei_me_dev_init(struct device *parent,
 
        return dev;
 }
-
+EXPORT_SYMBOL_GPL(mei_me_dev_init);
index 00a7132..a071c64 100644 (file)
@@ -112,6 +112,8 @@ enum mei_cfg_idx {
        MEI_ME_PCH12_SPS_ITOUCH_CFG,
        MEI_ME_PCH15_CFG,
        MEI_ME_PCH15_SPS_CFG,
+       MEI_ME_GSC_CFG,
+       MEI_ME_GSCFI_CFG,
        MEI_ME_NUM_CFG,
 };