#define LINK_SPEC "\
-melf" XLEN_SPEC "lriscv \
%{mno-relax:--no-relax} \
+%{mbig-endian:-EB} \
+%{mlittle-endian:-EL} \
%{shared}"
/* Link against Newlib libraries, because the ELF backend assumes Newlib.
%{p:%nconsider using `-pg' instead of `-p' with gprof (1)} \
%{v:-V} \
%{assert*} %{R*} %{rpath*} %{defsym*} \
+ %{mbig-endian:-EB} \
+ %{mlittle-endian:-EL} \
%{shared:-Bshareable %{h*} %{soname*}} \
%{symbolic:-Bsymbolic} \
%{static:-Bstatic} \
#define LINK_SPEC "\
-melf" XLEN_SPEC "lriscv" LD_EMUL_SUFFIX " \
%{mno-relax:--no-relax} \
+%{mbig-endian:-EB} \
+%{mlittle-endian:-EL} \
%{shared} \
%{!shared: \
%{!static: \
%{" FPIE_OR_FPIC_SPEC ":-fpic} \
%{march=*} \
%{mabi=*} \
+%{mbig-endian} \
+%{mlittle-endian} \
%(subtarget_asm_spec)" \
ASM_MISA_SPEC
/* Target machine storage layout */
#define BITS_BIG_ENDIAN 0
-#define BYTES_BIG_ENDIAN 0
-#define WORDS_BIG_ENDIAN 0
+#define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
+#define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN)
#define MAX_BITS_PER_WORD 64
HeaderInclude
config/riscv/riscv-opts.h
+mbig-endian
+Target RejectNegative Mask(BIG_ENDIAN)
+Assume target CPU is configured as big endian.
+
+mlittle-endian
+Target RejectNegative InverseMask(BIG_ENDIAN)
+Assume target CPU is configured as little endian.
+
mbranch-cost=
Target RejectNegative Joined UInteger Var(riscv_branch_cost)
-mbranch-cost=N Set the cost of branches to roughly N instructions.
-mrelax -mno-relax @gol
-mriscv-attribute -mmo-riscv-attribute @gol
-malign-data=@var{type} @gol
+-mbig-endian -mlittle-endian @gol
+-mstack-protector-guard=@var{guard} -mstack-protector-guard-reg=@var{reg} @gol
+-mstack-protector-guard-offset=@var{offset}}
width as the alignment value, and @samp{natural} which uses natural alignment.
@samp{xlen} is the default.
+@item -mbig-endian
+@opindex mbig-endian
+Generate big-endian code. This is the default when GCC is configured for a
+@samp{riscv64be-*-*} or @samp{riscv32be-*-*} target.
+
+@item -mlittle-endian
+@opindex mlittle-endian
+Generate little-endian code. This is the default when GCC is configured for a
+@samp{riscv64-*-*} or @samp{riscv32-*-*} but not a @samp{riscv64be-*-*} or
+@samp{riscv32be-*-*} target.
+
@item -mstack-protector-guard=@var{guard}
@itemx -mstack-protector-guard-reg=@var{reg}
@itemx -mstack-protector-guard-offset=@var{offset}