* sh.h (OVERRIDE_OPTIONS): Fix code that clears 'e' register class.
* sh.md (binary_sf_op): Use extra constant operand instead of
negating constant operand 4.
* sh.c (sh_expand_binop_v2sf): Supply it.
From-SVN: r63243
+Fri Feb 21 20:41:29 2003 J"orn Rennecke <joern.rennecke@superh.com>
+
+ * sh.h (OVERRIDE_OPTIONS): Fix code that clears 'e' register class.
+
+ * sh.md (binary_sf_op): Use extra constant operand instead of
+ negating constant operand 4.
+ * sh.c (sh_expand_binop_v2sf): Supply it.
+
2003-02-21 Zack Weinberg <zack@codesourcery.com>
* cpphash.h (struct lexer_state): Add directive_wants_padding.
/* Provide reg_class from a letter such as appears in the machine
description. *: target independently reserved letter.
- reg_class_from_letter['e'] is set to NO_REGS for TARGET_FMOVD. */
+ reg_class_from_letter['e' - 'a'] is set to NO_REGS for TARGET_FMOVD. */
enum reg_class reg_class_from_letter[] =
{
/* Code to generate prologue and epilogue sequences */
-/* PUSHED is the number of bytes that are bing pushed on the
+/* PUSHED is the number of bytes that are being pushed on the
stack for register saves. Return the frame size, padded
appropriately so that the stack stays properly aligned. */
static HOST_WIDE_INT
{
rtx sel0 = const0_rtx;
rtx sel1 = const1_rtx;
- rtx (*fn) PARAMS ((rtx, rtx, rtx, rtx, rtx, rtx, rtx)) = gen_binary_sf_op;
+ rtx (*fn) PARAMS ((rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx))
+ = gen_binary_sf_op;
rtx op = gen_rtx_fmt_ee (code, SFmode, op1, op2);
- emit_insn ((*fn) (op0, op1, op2, op, sel0, sel0, sel0));
- emit_insn ((*fn) (op0, op1, op2, op, sel1, sel1, sel1));
+ emit_insn ((*fn) (op0, op1, op2, op, sel0, sel0, sel0, sel1));
+ emit_insn ((*fn) (op0, op1, op2, op, sel1, sel1, sel1, sel0));
}
/* Return the class of registers for which a mode change from FROM to TO
targetm.asm_out.unaligned_op.di = NULL; \
} \
if (TARGET_FMOVD) \
- reg_class_from_letter['e'] = NO_REGS; \
+ reg_class_from_letter['e' - 'a'] = NO_REGS; \
\
for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
if (! VALID_REGISTER_P (regno)) \
(vec_concat:V2SF
(vec_select:SF
(match_dup 0)
- (parallel [(not:BI (match_operand 4 "const_int_operand" "n"))]))
+ (parallel [(match_operand 7 "const_int_operand" "n")]))
(match_operator:SF 3 "binary_float_operator"
[(vec_select:SF (match_operand:V2SF 1 "fp_arith_reg_operand" "f")
(parallel [(match_operand 5
(vec_select:SF (match_operand:V2SF 2 "fp_arith_reg_operand" "f")
(parallel [(match_operand 6
"const_int_operand" "n")]))]))
- (parallel [(not:BI (match_dup 4)) (match_dup 4)])))]
- "TARGET_SHMEDIA_FPU"
+ (parallel [(match_dup 7) (match_operand 4 "const_int_operand" "n")])))]
+ "TARGET_SHMEDIA_FPU && INTVAL (operands[4]) != INTVAL (operands[7])"
"#"
- "TARGET_SHMEDIA_FPU && reload_completed"
- [(set (match_dup 7) (match_dup 8))]
+ "&& reload_completed"
+ [(set (match_dup 8) (match_dup 9))]
"
{
int endian = TARGET_LITTLE_ENDIAN ? 0 : 1;
(true_regnum (operands[2])
+ (INTVAL (operands[6]) ^ endian)));
- operands[7] = gen_rtx_REG (SFmode,
+ operands[8] = gen_rtx_REG (SFmode,
(true_regnum (operands[0])
+ (INTVAL (operands[4]) ^ endian)));
- operands[8] = gen_rtx (GET_CODE (operands[3]), SFmode, op1, op2);
+ operands[9] = gen_rtx (GET_CODE (operands[3]), SFmode, op1, op2);
}"
[(set_attr "type" "fparith_media")])