;; Insn type.
(define_attr "type"
- "ialu,compare,shift,load,sload,store,uncond_branch,branch,call,sibcall,call_no_delay_slot,return,imul,fpload,fpstore,fp,fpmove,fpcmove,fpcmp,fpmul,fpdivs,fpdivd,fpsqrts,fpsqrtd,cmove,multi,misc"
+ "ialu,compare,shift,load,sload,store,uncond_branch,branch,call,sibcall,call_no_delay_slot,return,imul,idiv,fpload,fpstore,fp,fpmove,fpcmove,fpcmp,fpmul,fpdivs,fpdivd,fpsqrts,fpsqrtd,cmove,multi,misc"
(const_string "ialu"))
;; Length (in # of insns).
-(define_attr "length" ""
- (cond [(eq_attr "type" "load,sload,fpload")
- (if_then_else (match_operand 1 "symbolic_memory_operand" "")
- (const_int 2) (const_int 1))
+(define_attr "length" "" (const_int 1))
- (eq_attr "type" "store,fpstore")
- (if_then_else (match_operand 0 "symbolic_memory_operand" "")
- (const_int 2) (const_int 1))
-
- (eq_attr "type" "ialu")
- (if_then_else (ior (match_operand 2 "arith_operand" "")
- (match_operand 2 "arith_double_operand" ""))
- (const_int 1) (const_int 3))
-
- (eq_attr "type" "multi") (const_int 2)
-
- (eq_attr "type" "ialu")
- (if_then_else (ior (match_operand 1 "arith_operand" "")
- (match_operand 1 "arith_double_operand" ""))
- (const_int 1) (const_int 2))]
-
- (const_int 1)))
+;; FP precision.
+(define_attr "fptype" "single,double" (const_string "single"))
(define_asm_attributes
- [(set_attr "length" "1")
+ [(set_attr "length" "2")
(set_attr "type" "multi")])
;; Attributes for instruction and branch scheduling
return \"fcmped\\t%0, %1, %2\";
return \"fcmped\\t%1, %2\";
}"
- [(set_attr "type" "fpcmp")])
+ [(set_attr "type" "fpcmp")
+ (set_attr "fptype" "double")])
(define_insn "*cmptf_fpe"
[(set (match_operand:CCFPE 0 "fcc_reg_operand" "=c")
return \"fcmpd\\t%0, %1, %2\";
return \"fcmpd\\t%1, %2\";
}"
- [(set_attr "type" "fpcmp")])
+ [(set_attr "type" "fpcmp")
+ (set_attr "fptype" "double")])
(define_insn "*cmptf_fp"
[(set (match_operand:CCFP 0 "fcc_reg_operand" "=c")
(const_int 0)))]
"TARGET_ARCH64"
"#"
- [(set_attr "type" "cmove")
- (set_attr "length" "2")])
+ [(set_attr "length" "2")])
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(const_int 0))))]
"TARGET_ARCH64"
"#"
- [(set_attr "type" "cmove")
- (set_attr "length" "2")])
+ [(set_attr "length" "2")])
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(const_int 0)))]
"TARGET_ARCH64"
"#"
- [(set_attr "type" "cmove")
- (set_attr "length" "2")])
+ [(set_attr "length" "2")])
(define_split
[(set (match_operand:SI 0 "register_operand" "")
(const_int 0)))]
"TARGET_ARCH64"
"#"
- [(set_attr "type" "cmove")
- (set_attr "length" "2")])
+ [(set_attr "length" "2")])
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(const_int 0))))]
"TARGET_ARCH64"
"#"
- [(set_attr "type" "cmove")
- (set_attr "length" "2")])
+ [(set_attr "length" "2")])
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(const_int 0)))]
"TARGET_ARCH64"
"#"
- [(set_attr "type" "cmove")
- (set_attr "length" "2")])
+ [(set_attr "length" "2")])
(define_split
[(set (match_operand:SI 0 "register_operand" "")
(ltu:SI (reg:CC 100) (const_int 0)))]
""
"addx\\t%%g0, 0, %0"
- [(set_attr "type" "misc")
- (set_attr "length" "1")])
+ [(set_attr "type" "misc")])
(define_insn "*neg_sltu_insn"
[(set (match_operand:SI 0 "register_operand" "=r")
(neg:SI (ltu:SI (reg:CC 100) (const_int 0))))]
""
"subx\\t%%g0, 0, %0"
- [(set_attr "type" "misc")
- (set_attr "length" "1")])
+ [(set_attr "type" "misc")])
;; ??? Combine should canonicalize these next two to the same pattern.
(define_insn "*neg_sltu_minus_x"
(match_operand:SI 1 "arith_operand" "rI")))]
""
"subx\\t%%g0, %1, %0"
- [(set_attr "type" "misc")
- (set_attr "length" "1")])
+ [(set_attr "type" "misc")])
(define_insn "*neg_sltu_plus_x"
[(set (match_operand:SI 0 "register_operand" "=r")
(match_operand:SI 1 "arith_operand" "rI"))))]
""
"subx\\t%%g0, %1, %0"
- [(set_attr "type" "misc")
- (set_attr "length" "1")])
+ [(set_attr "type" "misc")])
(define_insn "*sgeu_insn"
[(set (match_operand:SI 0 "register_operand" "=r")
(geu:SI (reg:CC 100) (const_int 0)))]
""
"subx\\t%%g0, -1, %0"
- [(set_attr "type" "misc")
- (set_attr "length" "1")])
+ [(set_attr "type" "misc")])
(define_insn "*neg_sgeu_insn"
[(set (match_operand:SI 0 "register_operand" "=r")
(neg:SI (geu:SI (reg:CC 100) (const_int 0))))]
""
"addx\\t%%g0, -1, %0"
- [(set_attr "type" "misc")
- (set_attr "length" "1")])
+ [(set_attr "type" "misc")])
;; We can also do (x + ((unsigned) i >= 0)) and related, so put them in.
;; ??? The addx/subx insns use the 32 bit carry flag so there are no DImode
(match_operand:SI 1 "arith_operand" "rI")))]
""
"addx\\t%%g0, %1, %0"
- [(set_attr "type" "misc")
- (set_attr "length" "1")])
+ [(set_attr "type" "misc")])
(define_insn "*sltu_plus_x_plus_y"
[(set (match_operand:SI 0 "register_operand" "=r")
(match_operand:SI 2 "arith_operand" "rI"))))]
""
"addx\\t%1, %2, %0"
- [(set_attr "type" "misc")
- (set_attr "length" "1")])
+ [(set_attr "type" "misc")])
(define_insn "*x_minus_sltu"
[(set (match_operand:SI 0 "register_operand" "=r")
(ltu:SI (reg:CC 100) (const_int 0))))]
""
"subx\\t%1, 0, %0"
- [(set_attr "type" "misc")
- (set_attr "length" "1")])
+ [(set_attr "type" "misc")])
;; ??? Combine should canonicalize these next two to the same pattern.
(define_insn "*x_minus_y_minus_sltu"
(ltu:SI (reg:CC 100) (const_int 0))))]
""
"subx\\t%r1, %2, %0"
- [(set_attr "type" "misc")
- (set_attr "length" "1")])
+ [(set_attr "type" "misc")])
(define_insn "*x_minus_sltu_plus_y"
[(set (match_operand:SI 0 "register_operand" "=r")
(match_operand:SI 2 "arith_operand" "rI"))))]
""
"subx\\t%r1, %2, %0"
- [(set_attr "type" "misc")
- (set_attr "length" "1")])
+ [(set_attr "type" "misc")])
(define_insn "*sgeu_plus_x"
[(set (match_operand:SI 0 "register_operand" "=r")
(match_operand:SI 1 "register_operand" "r")))]
""
"subx\\t%1, -1, %0"
- [(set_attr "type" "misc")
- (set_attr "length" "1")])
+ [(set_attr "type" "misc")])
(define_insn "*x_minus_sgeu"
[(set (match_operand:SI 0 "register_operand" "=r")
(geu:SI (reg:CC 100) (const_int 0))))]
""
"addx\\t%1, -1, %0"
- [(set_attr "type" "misc")
- (set_attr "length" "1")])
+ [(set_attr "type" "misc")])
(define_split
[(set (match_operand:SI 0 "register_operand" "")
(unspec [(match_operand 1 "" "") (match_operand 2 "" "")] 2))]
"flag_pic && REGNO (operands[0]) == 23"
"sethi\\t%%hi(%a1-4), %0\\n\\tcall\\t%a2\\n\\tadd\\t%0, %%lo(%a1+4), %0"
- [(set_attr "length" "3")])
+ [(set_attr "type" "multi")
+ (set_attr "length" "3")])
;; Currently unused...
;; (define_insn "get_pc_via_rdpc"
mov\\t%1, %0
ldub\\t%1, %0
stb\\t%r1, %0"
- [(set_attr "type" "*,load,store")
- (set_attr "length" "1")])
+ [(set_attr "type" "*,load,store")])
(define_expand "movhi"
[(set (match_operand:HI 0 "general_operand" "")
[(set (match_operand:HI 0 "register_operand" "=r")
(match_operand:HI 1 "const64_high_operand" ""))]
"TARGET_ARCH64"
- "sethi\\t%%hi(%a1), %0"
- [(set_attr "length" "1")])
+ "sethi\\t%%hi(%a1), %0")
(define_insn "*movhi_insn"
[(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
sethi\\t%%hi(%a1), %0
lduh\\t%1, %0
sth\\t%r1, %0"
- [(set_attr "type" "*,*,load,store")
- (set_attr "length" "1")])
+ [(set_attr "type" "*,*,load,store")])
;; We always work with constants here.
(define_insn "*movhi_lo_sum"
(ior:HI (match_operand:HI 1 "arith_operand" "%r")
(match_operand:HI 2 "arith_operand" "I")))]
""
- "or\\t%1, %2, %0"
- [(set_attr "type" "ialu")
- (set_attr "length" "1")])
+ "or\\t%1, %2, %0")
(define_expand "movsi"
[(set (match_operand:SI 0 "general_operand" "")
[(set (match_operand:SI 0 "register_operand" "=r")
(match_operand:SI 1 "const64_high_operand" ""))]
"TARGET_ARCH64"
- "sethi\\t%%hi(%a1), %0"
- [(set_attr "length" "1")])
+ "sethi\\t%%hi(%a1), %0")
(define_insn "*movsi_insn"
[(set (match_operand:SI 0 "nonimmediate_operand" "=r,f,r,r,r,f,m,m,d")
st\\t%r1, %0
st\\t%1, %0
fzeros\\t%0"
- [(set_attr "type" "*,fpmove,*,*,load,fpload,store,fpstore,fpmove")
- (set_attr "length" "1")])
+ [(set_attr "type" "*,fpmove,*,*,load,fpload,store,fpstore,fpmove")])
(define_insn "*movsi_lo_sum"
[(set (match_operand:SI 0 "register_operand" "=r")
(lo_sum:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "immediate_operand" "in")))]
""
- "or\\t%1, %%lo(%a2), %0"
- [(set_attr "type" "ialu")
- (set_attr "length" "1")])
+ "or\\t%1, %%lo(%a2), %0")
(define_insn "*movsi_high"
[(set (match_operand:SI 0 "register_operand" "=r")
(high:SI (match_operand:SI 1 "immediate_operand" "in")))]
""
- "sethi\\t%%hi(%a1), %0"
- [(set_attr "length" "1")])
+ "sethi\\t%%hi(%a1), %0")
;; The next two patterns must wrap the SYMBOL_REF in an UNSPEC
;; so that CSE won't optimize the address computation away.
(lo_sum:SI (match_operand:SI 1 "register_operand" "r")
(unspec:SI [(match_operand:SI 2 "immediate_operand" "in")] 0)))]
"flag_pic"
- "or\\t%1, %%lo(%a2), %0"
- [(set_attr "type" "ialu")
- (set_attr "length" "1")])
+ "or\\t%1, %%lo(%a2), %0")
(define_insn "movsi_high_pic"
[(set (match_operand:SI 0 "register_operand" "=r")
(high:SI (unspec:SI [(match_operand 1 "" "")] 0)))]
"flag_pic && check_pic (1)"
- "sethi\\t%%hi(%a1), %0"
- [(set_attr "length" "1")])
+ "sethi\\t%%hi(%a1), %0")
(define_expand "movsi_pic_label_ref"
[(set (match_dup 3) (high:SI
(unspec:SI [(match_operand:SI 1 "label_ref_operand" "")
(match_operand:SI 2 "" "")] 5)))]
"flag_pic"
- "sethi\\t%%hi(%a2-(%a1-.)), %0"
- [(set_attr "length" "1")])
+ "sethi\\t%%hi(%a2-(%a1-.)), %0")
(define_insn "*movsi_lo_sum_pic_label_ref"
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI [(match_operand:SI 2 "label_ref_operand" "")
(match_operand:SI 3 "" "")] 5)))]
"flag_pic"
- "or\\t%1, %%lo(%a3-(%a2-.)), %0"
- [(set_attr "type" "ialu")
- (set_attr "length" "1")])
+ "or\\t%1, %%lo(%a3-(%a2-.)), %0")
(define_expand "movdi"
[(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand" "")
#
#"
[(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,*,*,*")
- (set_attr "length" "1,1,2,2,2,2,1,1,2,2,2")])
+ (set_attr "length" "*,*,2,2,2,2,*,*,2,2,2")])
;; The following are generated by sparc_emit_set_const64
(define_insn "*movdi_sp64_dbl"
(match_operand:DI 1 "const64_operand" ""))]
"(TARGET_ARCH64
&& HOST_BITS_PER_WIDE_INT != 64)"
- "mov\\t%1, %0"
- [(set_attr "length" "1")])
+ "mov\\t%1, %0")
;; This is needed to show CSE exactly which bits are set
;; in a 64-bit register by sethi instructions.
[(set (match_operand:DI 0 "register_operand" "=r")
(match_operand:DI 1 "const64_high_operand" ""))]
"TARGET_ARCH64"
- "sethi\\t%%hi(%a1), %0"
- [(set_attr "length" "1")])
+ "sethi\\t%%hi(%a1), %0")
(define_insn "*movdi_insn_sp64_novis"
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,m,?e,?e,?m")
ldd\\t%1, %0
std\\t%1, %0"
[(set_attr "type" "*,*,*,load,store,fpmove,fpload,fpstore")
- (set_attr "length" "1")])
+ (set_attr "fptype" "*,*,*,*,*,double,*,*")])
(define_insn "*movdi_insn_sp64_vis"
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,m,?e,?e,?m,b")
std\\t%1, %0
fzero\\t%0"
[(set_attr "type" "*,*,*,load,store,fpmove,fpload,fpstore,fpmove")
- (set_attr "length" "1")])
+ (set_attr "fptype" "*,*,*,*,*,double,*,*,double")])
(define_expand "movdi_pic_label_ref"
[(set (match_dup 3) (high:DI
(unspec:DI [(match_operand:DI 1 "label_ref_operand" "")
(match_operand:DI 2 "" "")] 5)))]
"TARGET_ARCH64 && flag_pic"
- "sethi\\t%%hi(%a2-(%a1-.)), %0"
- [(set_attr "length" "1")])
+ "sethi\\t%%hi(%a2-(%a1-.)), %0")
(define_insn "*movdi_lo_sum_pic_label_ref"
[(set (match_operand:DI 0 "register_operand" "=r")
(unspec:DI [(match_operand:DI 2 "label_ref_operand" "")
(match_operand:DI 3 "" "")] 5)))]
"TARGET_ARCH64 && flag_pic"
- "or\\t%1, %%lo(%a3-(%a2-.)), %0"
- [(set_attr "type" "ialu")
- (set_attr "length" "1")])
+ "or\\t%1, %%lo(%a3-(%a2-.)), %0")
;; Sparc-v9 code model support insns. See sparc_emit_set_symbolic_const64
;; in sparc.c to see what is going on here... PIC stuff comes first.
(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
(unspec:DI [(match_operand:DI 2 "immediate_operand" "in")] 0)))]
"TARGET_ARCH64 && flag_pic"
- "or\\t%1, %%lo(%a2), %0"
- [(set_attr "type" "ialu")
- (set_attr "length" "1")])
+ "or\\t%1, %%lo(%a2), %0")
(define_insn "movdi_high_pic"
[(set (match_operand:DI 0 "register_operand" "=r")
(high:DI (unspec:DI [(match_operand 1 "" "")] 0)))]
"TARGET_ARCH64 && flag_pic && check_pic (1)"
- "sethi\\t%%hi(%a1), %0"
- [(set_attr "length" "1")])
+ "sethi\\t%%hi(%a1), %0")
(define_insn "*sethi_di_medlow_embmedany_pic"
[(set (match_operand:DI 0 "register_operand" "=r")
(high:DI (match_operand:DI 1 "sp64_medium_pic_operand" "")))]
"(TARGET_CM_MEDLOW || TARGET_CM_EMBMEDANY) && check_pic (1)"
- "sethi\\t%%hi(%a1), %0"
- [(set_attr "length" "1")])
+ "sethi\\t%%hi(%a1), %0")
(define_insn "*sethi_di_medlow"
[(set (match_operand:DI 0 "register_operand" "=r")
(high:DI (match_operand:DI 1 "symbolic_operand" "")))]
"TARGET_CM_MEDLOW && check_pic (1)"
- "sethi\\t%%hi(%a1), %0"
- [(set_attr "length" "1")])
+ "sethi\\t%%hi(%a1), %0")
(define_insn "*losum_di_medlow"
[(set (match_operand:DI 0 "register_operand" "=r")
(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
(match_operand:DI 2 "symbolic_operand" "")))]
"TARGET_CM_MEDLOW"
- "or\\t%1, %%lo(%a2), %0"
- [(set_attr "type" "ialu")
- (set_attr "length" "1")])
+ "or\\t%1, %%lo(%a2), %0")
(define_insn "seth44"
[(set (match_operand:DI 0 "register_operand" "=r")
(high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] 6)))]
"TARGET_CM_MEDMID"
- "sethi\\t%%h44(%a1), %0"
- [(set_attr "length" "1")])
+ "sethi\\t%%h44(%a1), %0")
(define_insn "setm44"
[(set (match_operand:DI 0 "register_operand" "=r")
(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
(unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] 7)))]
"TARGET_CM_MEDMID"
- "or\\t%1, %%m44(%a2), %0"
- [(set_attr "length" "1")])
+ "or\\t%1, %%m44(%a2), %0")
(define_insn "setl44"
[(set (match_operand:DI 0 "register_operand" "=r")
(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
(match_operand:DI 2 "symbolic_operand" "")))]
"TARGET_CM_MEDMID"
- "or\\t%1, %%l44(%a2), %0"
- [(set_attr "type" "ialu")
- (set_attr "length" "1")])
+ "or\\t%1, %%l44(%a2), %0")
(define_insn "sethh"
[(set (match_operand:DI 0 "register_operand" "=r")
(high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] 9)))]
"TARGET_CM_MEDANY"
- "sethi\\t%%hh(%a1), %0"
- [(set_attr "length" "1")])
+ "sethi\\t%%hh(%a1), %0")
(define_insn "setlm"
[(set (match_operand:DI 0 "register_operand" "=r")
(high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] 10)))]
"TARGET_CM_MEDANY"
- "sethi\\t%%lm(%a1), %0"
- [(set_attr "length" "1")])
+ "sethi\\t%%lm(%a1), %0")
(define_insn "sethm"
[(set (match_operand:DI 0 "register_operand" "=r")
(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
(unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] 18)))]
"TARGET_CM_MEDANY"
- "or\\t%1, %%hm(%a2), %0"
- [(set_attr "type" "ialu")
- (set_attr "length" "1")])
+ "or\\t%1, %%hm(%a2), %0")
(define_insn "setlo"
[(set (match_operand:DI 0 "register_operand" "=r")
(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
(match_operand:DI 2 "symbolic_operand" "")))]
"TARGET_CM_MEDANY"
- "or\\t%1, %%lo(%a2), %0"
- [(set_attr "type" "ialu")
- (set_attr "length" "1")])
+ "or\\t%1, %%lo(%a2), %0")
(define_insn "embmedany_sethi"
[(set (match_operand:DI 0 "register_operand" "=r")
(high:DI (unspec:DI [(match_operand:DI 1 "data_segment_operand" "")] 11)))]
"TARGET_CM_EMBMEDANY && check_pic (1)"
- "sethi\\t%%hi(%a1), %0"
- [(set_attr "length" "1")])
+ "sethi\\t%%hi(%a1), %0")
(define_insn "embmedany_losum"
[(set (match_operand:DI 0 "register_operand" "=r")
(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
(match_operand:DI 2 "data_segment_operand" "")))]
"TARGET_CM_EMBMEDANY"
- "add\\t%1, %%lo(%a2), %0"
- [(set_attr "type" "ialu")
- (set_attr "length" "1")])
+ "add\\t%1, %%lo(%a2), %0")
(define_insn "embmedany_brsum"
[(set (match_operand:DI 0 "register_operand" "=r")
(unspec:DI [(match_operand:DI 1 "register_operand" "r")] 11))]
"TARGET_CM_EMBMEDANY"
- "add\\t%1, %_, %0"
- [(set_attr "length" "1")])
+ "add\\t%1, %_, %0")
(define_insn "embmedany_textuhi"
[(set (match_operand:DI 0 "register_operand" "=r")
(high:DI (unspec:DI [(match_operand:DI 1 "text_segment_operand" "")] 13)))]
"TARGET_CM_EMBMEDANY && check_pic (1)"
- "sethi\\t%%uhi(%a1), %0"
- [(set_attr "length" "1")])
+ "sethi\\t%%uhi(%a1), %0")
(define_insn "embmedany_texthi"
[(set (match_operand:DI 0 "register_operand" "=r")
(high:DI (unspec:DI [(match_operand:DI 1 "text_segment_operand" "")] 14)))]
"TARGET_CM_EMBMEDANY && check_pic (1)"
- "sethi\\t%%hi(%a1), %0"
- [(set_attr "length" "1")])
+ "sethi\\t%%hi(%a1), %0")
(define_insn "embmedany_textulo"
[(set (match_operand:DI 0 "register_operand" "=r")
(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
(unspec:DI [(match_operand:DI 2 "text_segment_operand" "")] 15)))]
"TARGET_CM_EMBMEDANY"
- "or\\t%1, %%ulo(%a2), %0"
- [(set_attr "type" "ialu")
- (set_attr "length" "1")])
+ "or\\t%1, %%ulo(%a2), %0")
(define_insn "embmedany_textlo"
[(set (match_operand:DI 0 "register_operand" "=r")
(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
(match_operand:DI 2 "text_segment_operand" "")))]
"TARGET_CM_EMBMEDANY"
- "or\\t%1, %%lo(%a2), %0"
- [(set_attr "type" "ialu")
- (set_attr "length" "1")])
+ "or\\t%1, %%lo(%a2), %0")
;; Now some patterns to help reload out a bit.
(define_expand "reload_indi"
abort();
}
}"
- [(set_attr "type" "fpmove,*,*,*,*,load,fpload,fpstore,store")
- (set_attr "length" "1")])
+ [(set_attr "type" "fpmove,*,*,*,*,load,fpload,fpstore,store")])
(define_insn "*movsf_insn_vis"
[(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,*r,*r,*r,f,m,m")
abort();
}
}"
- [(set_attr "type" "fpmove,fpmove,*,*,*,*,load,fpload,fpstore,store")
- (set_attr "length" "1")])
+ [(set_attr "type" "fpmove,fpmove,*,*,*,*,load,fpload,fpstore,store")])
;; Exactly the same as above, except that all `f' cases are deleted.
;; This is necessary to prevent reload from ever trying to use a `f' reg
abort();
}
}"
- [(set_attr "type" "*,*,*,*,load,store")
- (set_attr "length" "1")])
+ [(set_attr "type" "*,*,*,*,load,store")])
(define_insn "*movsf_lo_sum"
[(set (match_operand:SF 0 "register_operand" "=r")
REAL_VALUE_TO_TARGET_SINGLE (r, i);
operands[2] = GEN_INT (i);
return \"or\\t%1, %%lo(%a2), %0\";
-}"
- [(set_attr "type" "ialu")
- (set_attr "length" "1")])
+}")
(define_insn "*movsf_high"
[(set (match_operand:SF 0 "register_operand" "=r")
REAL_VALUE_TO_TARGET_SINGLE (r, i);
operands[1] = GEN_INT (i);
return \"sethi\\t%%hi(%1), %0\";
-}"
- [(set_attr "length" "1")])
+}")
(define_split
[(set (match_operand:SF 0 "register_operand" "")
#
#"
[(set_attr "type" "fpload,fpstore,load,store,*,*,*,*,*,*")
- (set_attr "length" "1,1,1,1,2,2,2,2,2,2")])
+ (set_attr "length" "*,*,*,*,2,2,2,2,2,2")])
(define_insn "*movdf_no_e_insn_sp32"
[(set (match_operand:DF 0 "nonimmediate_operand" "=U,T,o,r,o")
#
#"
[(set_attr "type" "load,store,*,*,*")
- (set_attr "length" "1,1,2,2,2")])
+ (set_attr "length" "*,*,2,2,2")])
(define_insn "*movdf_no_e_insn_v9_sp32"
[(set (match_operand:DF 0 "nonimmediate_operand" "=U,T,T,r,o")
#
#"
[(set_attr "type" "load,store,store,*,*")
- (set_attr "length" "1,1,1,2,2")])
+ (set_attr "length" "*,*,*,2,2")])
;; We have available v9 double floats but not 64-bit
;; integer registers and no VIS.
#
#"
[(set_attr "type" "fpmove,load,store,store,load,store,*,*,*")
- (set_attr "length" "1,1,1,1,1,1,2,2,2")])
+ (set_attr "length" "*,*,*,*,*,*,2,2,2")
+ (set_attr "fptype" "double,*,*,*,*,*,*,*,*")])
;; We have available v9 double floats but not 64-bit
;; integer registers but we have VIS.
#
#"
[(set_attr "type" "fpmove,fpmove,load,store,store,load,store,*,*,*")
- (set_attr "length" "1,1,1,1,1,1,1,2,2,2")])
+ (set_attr "length" "*,*,*,*,*,*,*,2,2,2")
+ (set_attr "fptype" "double,double,*,*,*,*,*,*,*,*")])
;; We have available both v9 double floats and 64-bit
;; integer registers. No VIS though.
stx\\t%r1, %0
#"
[(set_attr "type" "fpmove,load,store,*,load,store,*")
- (set_attr "length" "1,1,1,1,1,1,2")])
+ (set_attr "length" "*,*,*,*,*,*,2")
+ (set_attr "fptype" "double,*,*,*,*,*,*")])
;; We have available both v9 double floats and 64-bit
;; integer registers. And we have VIS.
stx\\t%r1, %0
#"
[(set_attr "type" "fpmove,fpmove,load,store,*,load,store,*")
- (set_attr "length" "1,1,1,1,1,1,1,2")])
+ (set_attr "length" "*,*,*,*,*,*,*,2")
+ (set_attr "fptype" "double,double,*,*,*,*,*,*")])
(define_insn "*movdf_no_e_insn_sp64"
[(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")
mov\\t%1, %0
ldx\\t%1, %0
stx\\t%r1, %0"
- [(set_attr "type" "*,load,store")
- (set_attr "length" "1")])
+ [(set_attr "type" "*,load,store")])
(define_split
[(set (match_operand:DF 0 "register_operand" "")
#
#"
[(set_attr "type" "fpmove,fpload,fpstore,*,*")
- (set_attr "length" "1,1,1,2,2")])
+ (set_attr "length" "*,*,*,2,2")])
(define_insn "*movtf_insn_hq_vis_sp64"
[(set (match_operand:TF 0 "nonimmediate_operand" "=e,e,m,eo,r,o")
#
#"
[(set_attr "type" "fpmove,fpload,fpstore,*,*,*")
- (set_attr "length" "1,1,1,2,2,2")])
+ (set_attr "length" "*,*,*,2,2,2")])
;; Now we allow the integer register cases even when
;; only arch64 is true.
"@
mov%C1\\t%x2, %3, %0
mov%c1\\t%x2, %4, %0"
- [(set_attr "type" "cmove")
- (set_attr "length" "1")])
+ [(set_attr "type" "cmove")])
(define_insn "*movhi_cc_sp64"
[(set (match_operand:HI 0 "register_operand" "=r,r")
"@
mov%C1\\t%x2, %3, %0
mov%c1\\t%x2, %4, %0"
- [(set_attr "type" "cmove")
- (set_attr "length" "1")])
+ [(set_attr "type" "cmove")])
(define_insn "*movsi_cc_sp64"
[(set (match_operand:SI 0 "register_operand" "=r,r")
"@
mov%C1\\t%x2, %3, %0
mov%c1\\t%x2, %4, %0"
- [(set_attr "type" "cmove")
- (set_attr "length" "1")])
+ [(set_attr "type" "cmove")])
;; ??? The constraints of operands 3,4 need work.
(define_insn "*movdi_cc_sp64"
"@
mov%C1\\t%x2, %3, %0
mov%c1\\t%x2, %4, %0"
- [(set_attr "type" "cmove")
- (set_attr "length" "1")])
+ [(set_attr "type" "cmove")])
(define_insn "*movdi_cc_sp64_trunc"
[(set (match_operand:SI 0 "register_operand" "=r,r")
"@
mov%C1\\t%x2, %3, %0
mov%c1\\t%x2, %4, %0"
- [(set_attr "type" "cmove")
- (set_attr "length" "1")])
+ [(set_attr "type" "cmove")])
(define_insn "*movsf_cc_sp64"
[(set (match_operand:SF 0 "register_operand" "=f,f")
"@
fmovs%C1\\t%x2, %3, %0
fmovs%c1\\t%x2, %4, %0"
- [(set_attr "type" "fpcmove")
- (set_attr "length" "1")])
+ [(set_attr "type" "fpcmove")])
(define_insn "movdf_cc_sp64"
[(set (match_operand:DF 0 "register_operand" "=e,e")
fmovd%C1\\t%x2, %3, %0
fmovd%c1\\t%x2, %4, %0"
[(set_attr "type" "fpcmove")
- (set_attr "length" "1")])
+ (set_attr "fptype" "double")])
(define_insn "*movtf_cc_hq_sp64"
[(set (match_operand:TF 0 "register_operand" "=e,e")
"@
fmovq%C1\\t%x2, %3, %0
fmovq%c1\\t%x2, %4, %0"
- [(set_attr "type" "fpcmove")
- (set_attr "length" "1")])
+ [(set_attr "type" "fpcmove")])
(define_insn "*movtf_cc_sp64"
[(set (match_operand:TF 0 "register_operand" "=e,e")
(match_operand:TF 4 "register_operand" "0,e")))]
"TARGET_V9 && TARGET_FPU && !TARGET_HARD_QUAD"
"#"
- [(set_attr "type" "fpcmove")
- (set_attr "length" "2")])
+ [(set_attr "length" "2")])
(define_split
[(set (match_operand:TF 0 "register_operand" "")
"@
movr%D1\\t%2, %r3, %0
movr%d1\\t%2, %r4, %0"
- [(set_attr "type" "cmove")
- (set_attr "length" "1")])
+ [(set_attr "type" "cmove")])
(define_insn "*movhi_cc_reg_sp64"
[(set (match_operand:HI 0 "register_operand" "=r,r")
"@
movr%D1\\t%2, %r3, %0
movr%d1\\t%2, %r4, %0"
- [(set_attr "type" "cmove")
- (set_attr "length" "1")])
+ [(set_attr "type" "cmove")])
(define_insn "*movsi_cc_reg_sp64"
[(set (match_operand:SI 0 "register_operand" "=r,r")
"@
movr%D1\\t%2, %r3, %0
movr%d1\\t%2, %r4, %0"
- [(set_attr "type" "cmove")
- (set_attr "length" "1")])
+ [(set_attr "type" "cmove")])
;; ??? The constraints of operands 3,4 need work.
(define_insn "*movdi_cc_reg_sp64"
"@
movr%D1\\t%2, %r3, %0
movr%d1\\t%2, %r4, %0"
- [(set_attr "type" "cmove")
- (set_attr "length" "1")])
+ [(set_attr "type" "cmove")])
(define_insn "*movdi_cc_reg_sp64_trunc"
[(set (match_operand:SI 0 "register_operand" "=r,r")
"@
movr%D1\\t%2, %r3, %0
movr%d1\\t%2, %r4, %0"
- [(set_attr "type" "cmove")
- (set_attr "length" "1")])
+ [(set_attr "type" "cmove")])
(define_insn "*movsf_cc_reg_sp64"
[(set (match_operand:SF 0 "register_operand" "=f,f")
"@
fmovrs%D1\\t%2, %3, %0
fmovrs%d1\\t%2, %4, %0"
- [(set_attr "type" "fpcmove")
- (set_attr "length" "1")])
+ [(set_attr "type" "fpcmove")])
(define_insn "movdf_cc_reg_sp64"
[(set (match_operand:DF 0 "register_operand" "=e,e")
fmovrd%D1\\t%2, %3, %0
fmovrd%d1\\t%2, %4, %0"
[(set_attr "type" "fpcmove")
- (set_attr "length" "1")])
+ (set_attr "fptype" "double")])
(define_insn "*movtf_cc_reg_hq_sp64"
[(set (match_operand:TF 0 "register_operand" "=e,e")
"@
fmovrq%D1\\t%2, %3, %0
fmovrq%d1\\t%2, %4, %0"
- [(set_attr "type" "fpcmove")
- (set_attr "length" "1")])
+ [(set_attr "type" "fpcmove")])
(define_insn "*movtf_cc_reg_sp64"
[(set (match_operand:TF 0 "register_operand" "=e,e")
(match_operand:TF 4 "register_operand" "0,e")))]
"TARGET_ARCH64 && TARGET_FPU && ! TARGET_HARD_QUAD"
"#"
- [(set_attr "type" "fpcmove")
- (set_attr "length" "2")])
+ [(set_attr "length" "2")])
(define_split
[(set (match_operand:TF 0 "register_operand" "")
(zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
""
"lduh\\t%1, %0"
- [(set_attr "type" "load")
- (set_attr "length" "1")])
+ [(set_attr "type" "load")])
(define_expand "zero_extendqihi2"
[(set (match_operand:HI 0 "register_operand" "")
"@
and\\t%1, 0xff, %0
ldub\\t%1, %0"
- [(set_attr "type" "ialu,load")
- (set_attr "length" "1")])
+ [(set_attr "type" "*,load")])
(define_expand "zero_extendqisi2"
[(set (match_operand:SI 0 "register_operand" "")
"@
and\\t%1, 0xff, %0
ldub\\t%1, %0"
- [(set_attr "type" "ialu,load")
- (set_attr "length" "1")])
+ [(set_attr "type" "*,load")])
(define_expand "zero_extendqidi2"
[(set (match_operand:DI 0 "register_operand" "")
"@
and\\t%1, 0xff, %0
ldub\\t%1, %0"
- [(set_attr "type" "ialu,load")
- (set_attr "length" "1")])
+ [(set_attr "type" "*,load")])
(define_expand "zero_extendhidi2"
[(set (match_operand:DI 0 "register_operand" "")
(zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
"TARGET_ARCH64"
"lduh\\t%1, %0"
- [(set_attr "type" "load")
- (set_attr "length" "1")])
+ [(set_attr "type" "load")])
;; ??? Write truncdisi pattern using sra?
"@
srl\\t%1, 0, %0
lduw\\t%1, %0"
- [(set_attr "type" "shift,load")
- (set_attr "length" "1")])
+ [(set_attr "type" "shift,load")])
(define_insn "*zero_extendsidi2_insn_sp32"
[(set (match_operand:DI 0 "register_operand" "=r")
(const_int 0)))]
""
"andcc\\t%0, 0xff, %%g0"
- [(set_attr "type" "compare")
- (set_attr "length" "1")])
+ [(set_attr "type" "compare")])
(define_insn "*cmp_zero_qi"
[(set (reg:CC 100)
(const_int 0)))]
""
"andcc\\t%0, 0xff, %%g0"
- [(set_attr "type" "compare")
- (set_attr "length" "1")])
+ [(set_attr "type" "compare")])
(define_insn "*cmp_zero_extendqisi2_set"
[(set (reg:CC 100)
(zero_extend:SI (match_dup 1)))]
""
"andcc\\t%1, 0xff, %0"
- [(set_attr "type" "compare")
- (set_attr "length" "1")])
+ [(set_attr "type" "compare")])
(define_insn "*cmp_zero_extendqisi2_andcc_set"
[(set (reg:CC 100)
(zero_extend:SI (subreg:QI (match_dup 1) 0)))]
""
"andcc\\t%1, 0xff, %0"
- [(set_attr "type" "compare")
- (set_attr "length" "1")])
+ [(set_attr "type" "compare")])
(define_insn "*cmp_zero_extendqidi2"
[(set (reg:CCX 100)
(const_int 0)))]
"TARGET_ARCH64"
"andcc\\t%0, 0xff, %%g0"
- [(set_attr "type" "compare")
- (set_attr "length" "1")])
+ [(set_attr "type" "compare")])
(define_insn "*cmp_zero_qi_sp64"
[(set (reg:CCX 100)
(const_int 0)))]
"TARGET_ARCH64"
"andcc\\t%0, 0xff, %%g0"
- [(set_attr "type" "compare")
- (set_attr "length" "1")])
+ [(set_attr "type" "compare")])
(define_insn "*cmp_zero_extendqidi2_set"
[(set (reg:CCX 100)
(zero_extend:DI (match_dup 1)))]
"TARGET_ARCH64"
"andcc\\t%1, 0xff, %0"
- [(set_attr "type" "compare")
- (set_attr "length" "1")])
+ [(set_attr "type" "compare")])
(define_insn "*cmp_zero_extendqidi2_andcc_set"
[(set (reg:CCX 100)
(zero_extend:DI (subreg:QI (match_dup 1) 0)))]
"TARGET_ARCH64"
"andcc\\t%1, 0xff, %0"
- [(set_attr "type" "compare")
- (set_attr "length" "1")])
+ [(set_attr "type" "compare")])
;; Similarly, handle {SI,DI}->QI mode truncation followed by a compare.
(const_int 0)))]
""
"andcc\\t%0, 0xff, %%g0"
- [(set_attr "type" "compare")
- (set_attr "length" "1")])
+ [(set_attr "type" "compare")])
(define_insn "*cmp_siqi_trunc_set"
[(set (reg:CC 100)
(subreg:QI (match_dup 1) 3))]
""
"andcc\\t%1, 0xff, %0"
- [(set_attr "type" "compare")
- (set_attr "length" "1")])
+ [(set_attr "type" "compare")])
(define_insn "*cmp_diqi_trunc"
[(set (reg:CC 100)
(const_int 0)))]
"TARGET_ARCH64"
"andcc\\t%0, 0xff, %%g0"
- [(set_attr "type" "compare")
- (set_attr "length" "1")])
+ [(set_attr "type" "compare")])
(define_insn "*cmp_diqi_trunc_set"
[(set (reg:CC 100)
(subreg:QI (match_dup 1) 7))]
"TARGET_ARCH64"
"andcc\\t%1, 0xff, %0"
- [(set_attr "type" "compare")
- (set_attr "length" "1")])
+ [(set_attr "type" "compare")])
\f
;;- sign extension instructions
(sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
""
"ldsh\\t%1, %0"
- [(set_attr "type" "sload")
- (set_attr "length" "1")])
+ [(set_attr "type" "sload")])
(define_expand "extendqihi2"
[(set (match_operand:HI 0 "register_operand" "")
(sign_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
""
"ldsb\\t%1, %0"
- [(set_attr "type" "sload")
- (set_attr "length" "1")])
+ [(set_attr "type" "sload")])
(define_expand "extendqisi2"
[(set (match_operand:SI 0 "register_operand" "")
(sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
""
"ldsb\\t%1, %0"
- [(set_attr "type" "sload")
- (set_attr "length" "1")])
+ [(set_attr "type" "sload")])
(define_expand "extendqidi2"
[(set (match_operand:DI 0 "register_operand" "")
(sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
"TARGET_ARCH64"
"ldsb\\t%1, %0"
- [(set_attr "type" "sload")
- (set_attr "length" "1")])
+ [(set_attr "type" "sload")])
(define_expand "extendhidi2"
[(set (match_operand:DI 0 "register_operand" "")
(sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
"TARGET_ARCH64"
"ldsh\\t%1, %0"
- [(set_attr "type" "sload")
- (set_attr "length" "1")])
+ [(set_attr "type" "sload")])
(define_expand "extendsidi2"
[(set (match_operand:DI 0 "register_operand" "")
"@
sra\\t%1, 0, %0
ldsw\\t%1, %0"
- [(set_attr "type" "shift,sload")
- (set_attr "length" "1")])
+ [(set_attr "type" "shift,sload")])
\f
;; Special pattern for optimizing bit-field compares. This is needed
;; because combine uses this as a canonical form.
operands[1] = GEN_INT (mask);
return \"andcc\\t%0, %1, %%g0\";
}"
- [(set_attr "type" "compare")
- (set_attr "length" "1")])
+ [(set_attr "type" "compare")])
(define_insn "*cmp_zero_extract_sp64"
[(set (reg:CCX 100)
operands[1] = GEN_INT (mask);
return \"andcc\\t%0, %1, %%g0\";
}"
- [(set_attr "type" "compare")
- (set_attr "length" "1")])
+ [(set_attr "type" "compare")])
\f
;; Conversions between float, double and long double.
"TARGET_FPU"
"fstod\\t%1, %0"
[(set_attr "type" "fp")
- (set_attr "length" "1")])
+ (set_attr "fptype" "double")])
(define_expand "extendsftf2"
[(set (match_operand:TF 0 "register_operand" "=e")
(match_operand:SF 1 "register_operand" "f")))]
"TARGET_FPU && TARGET_HARD_QUAD"
"fstoq\\t%1, %0"
- [(set_attr "type" "fp")
- (set_attr "length" "1")])
+ [(set_attr "type" "fp")])
(define_expand "extenddftf2"
[(set (match_operand:TF 0 "register_operand" "=e")
(match_operand:DF 1 "register_operand" "e")))]
"TARGET_FPU && TARGET_HARD_QUAD"
"fdtoq\\t%1, %0"
- [(set_attr "type" "fp")
- (set_attr "length" "1")])
+ [(set_attr "type" "fp")])
(define_insn "truncdfsf2"
[(set (match_operand:SF 0 "register_operand" "=f")
"TARGET_FPU"
"fdtos\\t%1, %0"
[(set_attr "type" "fp")
- (set_attr "length" "1")])
+ (set_attr "fptype" "double")])
(define_expand "trunctfsf2"
[(set (match_operand:SF 0 "register_operand" "=f")
(match_operand:TF 1 "register_operand" "e")))]
"TARGET_FPU && TARGET_HARD_QUAD"
"fqtos\\t%1, %0"
- [(set_attr "type" "fp")
- (set_attr "length" "1")])
+ [(set_attr "type" "fp")])
(define_expand "trunctfdf2"
[(set (match_operand:DF 0 "register_operand" "=f")
(match_operand:TF 1 "register_operand" "e")))]
"TARGET_FPU && TARGET_HARD_QUAD"
"fqtod\\t%1, %0"
- [(set_attr "type" "fp")
- (set_attr "length" "1")])
+ [(set_attr "type" "fp")])
\f
;; Conversion between fixed point and floating point.
"TARGET_FPU"
"fitos\\t%1, %0"
[(set_attr "type" "fp")
- (set_attr "length" "1")])
+ (set_attr "fptype" "double")])
(define_insn "floatsidf2"
[(set (match_operand:DF 0 "register_operand" "=e")
"TARGET_FPU"
"fitod\\t%1, %0"
[(set_attr "type" "fp")
- (set_attr "length" "1")])
+ (set_attr "fptype" "double")])
(define_expand "floatsitf2"
[(set (match_operand:TF 0 "register_operand" "=e")
(float:TF (match_operand:SI 1 "register_operand" "f")))]
"TARGET_FPU && TARGET_HARD_QUAD"
"fitoq\\t%1, %0"
- [(set_attr "type" "fp")
- (set_attr "length" "1")])
+ [(set_attr "type" "fp")])
(define_expand "floatunssitf2"
[(set (match_operand:TF 0 "register_operand" "=e")
"TARGET_V9 && TARGET_FPU"
"fxtos\\t%1, %0"
[(set_attr "type" "fp")
- (set_attr "length" "1")])
+ (set_attr "fptype" "double")])
(define_insn "floatdidf2"
[(set (match_operand:DF 0 "register_operand" "=e")
"TARGET_V9 && TARGET_FPU"
"fxtod\\t%1, %0"
[(set_attr "type" "fp")
- (set_attr "length" "1")])
+ (set_attr "fptype" "double")])
(define_expand "floatditf2"
[(set (match_operand:TF 0 "register_operand" "=e")
(float:TF (match_operand:DI 1 "register_operand" "e")))]
"TARGET_V9 && TARGET_FPU && TARGET_HARD_QUAD"
"fxtoq\\t%1, %0"
- [(set_attr "type" "fp")
- (set_attr "length" "1")])
+ [(set_attr "type" "fp")])
(define_expand "floatunsditf2"
[(set (match_operand:TF 0 "register_operand" "=e")
"TARGET_FPU"
"fstoi\\t%1, %0"
[(set_attr "type" "fp")
- (set_attr "length" "1")])
+ (set_attr "fptype" "double")])
(define_insn "fix_truncdfsi2"
[(set (match_operand:SI 0 "register_operand" "=f")
"TARGET_FPU"
"fdtoi\\t%1, %0"
[(set_attr "type" "fp")
- (set_attr "length" "1")])
+ (set_attr "fptype" "double")])
(define_expand "fix_trunctfsi2"
[(set (match_operand:SI 0 "register_operand" "=f")
(fix:SI (fix:TF (match_operand:TF 1 "register_operand" "e"))))]
"TARGET_FPU && TARGET_HARD_QUAD"
"fqtoi\\t%1, %0"
- [(set_attr "type" "fp")
- (set_attr "length" "1")])
+ [(set_attr "type" "fp")])
(define_expand "fixuns_trunctfsi2"
[(set (match_operand:SI 0 "register_operand" "=f")
"TARGET_V9 && TARGET_FPU"
"fstox\\t%1, %0"
[(set_attr "type" "fp")
- (set_attr "length" "1")])
+ (set_attr "fptype" "double")])
(define_insn "fix_truncdfdi2"
[(set (match_operand:DI 0 "register_operand" "=e")
"TARGET_V9 && TARGET_FPU"
"fdtox\\t%1, %0"
[(set_attr "type" "fp")
- (set_attr "length" "1")])
+ (set_attr "fptype" "double")])
(define_expand "fix_trunctfdi2"
[(set (match_operand:DI 0 "register_operand" "=e")
(fix:DI (fix:TF (match_operand:TF 1 "register_operand" "e"))))]
"TARGET_V9 && TARGET_FPU && TARGET_HARD_QUAD"
"fqtox\\t%1, %0"
- [(set_attr "type" "fp")
- (set_attr "length" "1")])
+ [(set_attr "type" "fp")])
(define_expand "fixuns_trunctfdi2"
[(set (match_operand:DI 0 "register_operand" "=f")
(ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
""
"addx\\t%1, %2, %0"
- [(set_attr "length" "1")])
+ [(set_attr "type" "misc")])
(define_insn "*addx_extend_sp32"
[(set (match_operand:DI 0 "register_operand" "=r")
(ltu:SI (reg:CC_NOOV 100) (const_int 0)))))]
"TARGET_ARCH64"
"addx\\t%r1, %2, %0"
- [(set_attr "type" "misc")
- (set_attr "length" "1")])
+ [(set_attr "type" "misc")])
(define_insn "subx"
[(set (match_operand:SI 0 "register_operand" "=r")
(ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
""
"subx\\t%r1, %2, %0"
- [(set_attr "type" "misc")
- (set_attr "length" "1")])
+ [(set_attr "type" "misc")])
(define_insn "*subx_extend_sp64"
[(set (match_operand:DI 0 "register_operand" "=r")
(ltu:SI (reg:CC_NOOV 100) (const_int 0)))))]
"TARGET_ARCH64"
"subx\\t%r1, %2, %0"
- [(set_attr "type" "misc")
- (set_attr "length" "1")])
+ [(set_attr "type" "misc")])
(define_insn "*subx_extend"
[(set (match_operand:DI 0 "register_operand" "=r")
(clobber (reg:CC 100))]
"! TARGET_ARCH64"
"#"
- [(set_attr "type" "multi")
- (set_attr "length" "2")])
+ [(set_attr "length" "2")])
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(plus:DI (match_operand:DI 1 "arith_double_operand" "%r")
(match_operand:DI 2 "arith_double_operand" "rHI")))]
"TARGET_ARCH64"
- "add\\t%1, %2, %0"
- [(set_attr "length" "1")])
+ "add\\t%1, %2, %0")
(define_expand "addsi3"
[(set (match_operand:SI 0 "register_operand" "=r,d")
"@
add\\t%1, %2, %0
fpadd32s\\t%1, %2, %0"
- [(set_attr "type" "ialu,fp")
- (set_attr "length" "1")])
+ [(set_attr "type" "*,fp")])
(define_insn "*cmp_cc_plus"
[(set (reg:CC_NOOV 100)
(const_int 0)))]
""
"addcc\\t%0, %1, %%g0"
- [(set_attr "type" "compare")
- (set_attr "length" "1")])
+ [(set_attr "type" "compare")])
(define_insn "*cmp_ccx_plus"
[(set (reg:CCX_NOOV 100)
(const_int 0)))]
"TARGET_ARCH64"
"addcc\\t%0, %1, %%g0"
- [(set_attr "type" "compare")
- (set_attr "length" "1")])
+ [(set_attr "type" "compare")])
(define_insn "*cmp_cc_plus_set"
[(set (reg:CC_NOOV 100)
(plus:SI (match_dup 1) (match_dup 2)))]
""
"addcc\\t%1, %2, %0"
- [(set_attr "type" "compare")
- (set_attr "length" "1")])
+ [(set_attr "type" "compare")])
(define_insn "*cmp_ccx_plus_set"
[(set (reg:CCX_NOOV 100)
(plus:DI (match_dup 1) (match_dup 2)))]
"TARGET_ARCH64"
"addcc\\t%1, %2, %0"
- [(set_attr "type" "compare")
- (set_attr "length" "1")])
+ [(set_attr "type" "compare")])
(define_expand "subdi3"
[(set (match_operand:DI 0 "register_operand" "=r")
(clobber (reg:CC 100))]
"! TARGET_ARCH64"
"#"
- [(set_attr "type" "multi")
- (set_attr "length" "2")])
+ [(set_attr "length" "2")])
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(minus:DI (match_operand:DI 1 "register_operand" "r")
(match_operand:DI 2 "arith_double_operand" "rHI")))]
"TARGET_ARCH64"
- "sub\\t%1, %2, %0"
- [(set_attr "length" "1")])
+ "sub\\t%1, %2, %0")
(define_expand "subsi3"
[(set (match_operand:SI 0 "register_operand" "=r,d")
"@
sub\\t%1, %2, %0
fpsub32s\\t%1, %2, %0"
- [(set_attr "type" "ialu,fp")
- (set_attr "length" "1")])
+ [(set_attr "type" "*,fp")])
(define_insn "*cmp_minus_cc"
[(set (reg:CC_NOOV 100)
(const_int 0)))]
""
"subcc\\t%r0, %1, %%g0"
- [(set_attr "type" "compare")
- (set_attr "length" "1")])
+ [(set_attr "type" "compare")])
(define_insn "*cmp_minus_ccx"
[(set (reg:CCX_NOOV 100)
(const_int 0)))]
"TARGET_ARCH64"
"subcc\\t%0, %1, %%g0"
- [(set_attr "type" "compare")
- (set_attr "length" "1")])
+ [(set_attr "type" "compare")])
(define_insn "cmp_minus_cc_set"
[(set (reg:CC_NOOV 100)
(minus:SI (match_dup 1) (match_dup 2)))]
""
"subcc\\t%r1, %2, %0"
- [(set_attr "type" "compare")
- (set_attr "length" "1")])
+ [(set_attr "type" "compare")])
(define_insn "*cmp_minus_ccx_set"
[(set (reg:CCX_NOOV 100)
(minus:DI (match_dup 1) (match_dup 2)))]
"TARGET_ARCH64"
"subcc\\t%1, %2, %0"
- [(set_attr "type" "compare")
- (set_attr "length" "1")])
+ [(set_attr "type" "compare")])
\f
;; Integer Multiply/Divide.
(match_operand:SI 2 "arith_operand" "rI")))]
"TARGET_HARD_MUL"
"smul\\t%1, %2, %0"
- [(set_attr "type" "imul")
- (set_attr "length" "1")])
+ [(set_attr "type" "imul")])
(define_expand "muldi3"
[(set (match_operand:DI 0 "register_operand" "=r")
(match_operand:DI 2 "arith_double_operand" "rHI")))]
"TARGET_ARCH64"
"mulx\\t%1, %2, %0"
- [(set_attr "type" "imul")
- (set_attr "length" "1")])
+ [(set_attr "type" "imul")])
;; V8plus wide multiply.
;; XXX
else
return \"sllx\\t%H1, 32, %3\\n\\tsllx\\t%H2, 32, %4\\n\\tor\\t%L1, %3, %3\\n\\tor\\t%L2, %4, %4\\n\\tmulx\\t%3, %4, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0\";
}"
- [(set_attr "length" "9,8")])
+ [(set_attr "type" "multi")
+ (set_attr "length" "9,8")])
(define_insn "*cmp_mul_set"
[(set (reg:CC 100)
(mult:SI (match_dup 1) (match_dup 2)))]
"TARGET_V8 || TARGET_SPARCLITE || TARGET_DEPRECATED_V8_INSNS"
"smulcc\\t%1, %2, %0"
- [(set_attr "type" "imul")
- (set_attr "length" "1")])
+ [(set_attr "type" "imul")])
(define_expand "mulsidi3"
[(set (match_operand:DI 0 "register_operand" "")
"@
smul\\t%1, %2, %L0\\n\\tsrlx\\t%L0, 32, %H0
smul\\t%1, %2, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0"
- [(set_attr "length" "2,3")])
+ [(set_attr "type" "multi")
+ (set_attr "length" "2,3")])
;; XXX
(define_insn "const_mulsidi3_v8plus"
"@
smul\\t%1, %2, %L0\\n\\tsrlx\\t%L0, 32, %H0
smul\\t%1, %2, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0"
- [(set_attr "length" "2,3")])
+ [(set_attr "type" "multi")
+ (set_attr "length" "2,3")])
;; XXX
(define_insn "*mulsidi3_sp32"
{
return TARGET_SPARCLET ? \"smuld\\t%1, %2, %L0\" : \"smul\\t%1, %2, %L0\\n\\trd\\t%%y, %H0\";
}"
- [(set (attr "length")
+ [(set (attr "type")
+ (if_then_else (eq_attr "isa" "sparclet")
+ (const_string "imul") (const_string "multi")))
+ (set (attr "length")
(if_then_else (eq_attr "isa" "sparclet")
(const_int 1) (const_int 2)))])
(sign_extend:DI (match_operand:SI 2 "register_operand" "r"))))]
"TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64"
"smul\\t%1, %2, %0"
- [(set_attr "length" "1")])
+ [(set_attr "type" "imul")])
;; Extra pattern, because sign_extend of a constant isn't valid.
{
return TARGET_SPARCLET ? \"smuld\\t%1, %2, %L0\" : \"smul\\t%1, %2, %L0\\n\\trd\\t%%y, %H0\";
}"
- [(set (attr "length")
+ [(set (attr "type")
+ (if_then_else (eq_attr "isa" "sparclet")
+ (const_string "imul") (const_string "multi")))
+ (set (attr "length")
(if_then_else (eq_attr "isa" "sparclet")
(const_int 1) (const_int 2)))])
(match_operand:SI 2 "small_int" "I")))]
"TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64"
"smul\\t%1, %2, %0"
- [(set_attr "length" "1")])
+ [(set_attr "type" "imul")])
(define_expand "smulsi3_highpart"
[(set (match_operand:SI 0 "register_operand" "")
"@
smul\\t%1, %2, %0\;srlx\\t%0, %3, %0
smul\\t%1, %2, %4\;srlx\\t%4, %3, %0"
- [(set_attr "length" "2")])
+ [(set_attr "type" "multi")
+ (set_attr "length" "2")])
;; The combiner changes TRUNCATE in the previous pattern to SUBREG.
;; XXX
"@
smul\\t%1, %2, %0\\n\\tsrlx\\t%0, %3, %0
smul\\t%1, %2, %4\\n\\tsrlx\\t%4, %3, %0"
- [(set_attr "length" "2")])
+ [(set_attr "type" "multi")
+ (set_attr "length" "2")])
;; XXX
(define_insn "const_smulsi3_highpart_v8plus"
"@
smul\\t%1, %2, %0\\n\\tsrlx\\t%0, %3, %0
smul\\t%1, %2, %4\\n\\tsrlx\\t%4, %3, %0"
- [(set_attr "length" "2")])
+ [(set_attr "type" "multi")
+ (set_attr "length" "2")])
;; XXX
(define_insn "*smulsi3_highpart_sp32"
(const_int 32))))]
"TARGET_HARD_MUL32"
"smul\\t%1, %2, %%g0\\n\\trd\\t%%y, %0"
- [(set_attr "length" "2")])
+ [(set_attr "type" "multi")
+ (set_attr "length" "2")])
;; XXX
(define_insn "const_smulsi3_highpart"
(const_int 32))))]
"TARGET_HARD_MUL32"
"smul\\t%1, %2, %%g0\\n\\trd\\t%%y, %0"
- [(set_attr "length" "2")])
+ [(set_attr "type" "multi")
+ (set_attr "length" "2")])
(define_expand "umulsidi3"
[(set (match_operand:DI 0 "register_operand" "")
"@
umul\\t%1, %2, %L0\\n\\tsrlx\\t%L0, 32, %H0
umul\\t%1, %2, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0"
- [(set_attr "length" "2,3")])
+ [(set_attr "type" "multi")
+ (set_attr "length" "2,3")])
;; XXX
(define_insn "*umulsidi3_sp32"
{
return TARGET_SPARCLET ? \"umuld\\t%1, %2, %L0\" : \"umul\\t%1, %2, %L0\\n\\trd\\t%%y, %H0\";
}"
- [(set (attr "length")
+ [(set (attr "type")
+ (if_then_else (eq_attr "isa" "sparclet")
+ (const_string "imul") (const_string "multi")))
+ (set (attr "length")
(if_then_else (eq_attr "isa" "sparclet")
(const_int 1) (const_int 2)))])
(zero_extend:DI (match_operand:SI 2 "register_operand" "r"))))]
"TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64"
"umul\\t%1, %2, %0"
- [(set_attr "length" "1")])
+ [(set_attr "type" "imul")])
;; Extra pattern, because sign_extend of a constant isn't valid.
{
return TARGET_SPARCLET ? \"umuld\\t%1, %2, %L0\" : \"umul\\t%1, %2, %L0\\n\\trd\\t%%y, %H0\";
}"
- [(set (attr "length")
+ [(set (attr "type")
+ (if_then_else (eq_attr "isa" "sparclet")
+ (const_string "imul") (const_string "multi")))
+ (set (attr "length")
(if_then_else (eq_attr "isa" "sparclet")
(const_int 1) (const_int 2)))])
(match_operand:SI 2 "uns_small_int" "")))]
"TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64"
"umul\\t%1, %2, %0"
- [(set_attr "length" "1")])
+ [(set_attr "type" "imul")])
;; XXX
(define_insn "const_umulsidi3_v8plus"
"@
umul\\t%1, %2, %L0\\n\\tsrlx\\t%L0, 32, %H0
umul\\t%1, %2, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0"
- [(set_attr "length" "2,3")])
+ [(set_attr "type" "multi")
+ (set_attr "length" "2,3")])
(define_expand "umulsi3_highpart"
[(set (match_operand:SI 0 "register_operand" "")
"@
umul\\t%1, %2, %0\\n\\tsrlx\\t%0, %3, %0
umul\\t%1, %2, %4\\n\\tsrlx\\t%4, %3, %0"
- [(set_attr "length" "2")])
+ [(set_attr "type" "multi")
+ (set_attr "length" "2")])
;; XXX
(define_insn "const_umulsi3_highpart_v8plus"
"@
umul\\t%1, %2, %0\\n\\tsrlx\\t%0, %3, %0
umul\\t%1, %2, %4\\n\\tsrlx\\t%4, %3, %0"
- [(set_attr "length" "2")])
+ [(set_attr "type" "multi")
+ (set_attr "length" "2")])
;; XXX
(define_insn "*umulsi3_highpart_sp32"
(const_int 32))))]
"TARGET_HARD_MUL32"
"umul\\t%1, %2, %%g0\\n\\trd\\t%%y, %0"
- [(set_attr "length" "2")])
+ [(set_attr "type" "multi")
+ (set_attr "length" "2")])
;; XXX
(define_insn "const_umulsi3_highpart"
(const_int 32))))]
"TARGET_HARD_MUL32"
"umul\\t%1, %2, %%g0\\n\\trd\\t%%y, %0"
- [(set_attr "length" "2")])
+ [(set_attr "type" "multi")
+ (set_attr "length" "2")])
;; The v8 architecture specifies that there must be 3 instructions between
;; a y register write and a use of it for correct results.
else
return \"sra\\t%1, 31, %3\\n\\twr\\t%3, 0, %%y\\n\\tld\\t%2, %3\\n\\tnop\\n\\tnop\\n\\tsdiv\\t%1, %3, %0\";
}"
- [(set (attr "length")
+ [(set_attr "type" "multi")
+ (set (attr "length")
(if_then_else (eq_attr "isa" "v9")
(const_int 4) (const_int 7)))])
(use (match_operand:SI 3 "register_operand" "r"))]
"TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64"
"wr\\t%%g0, %3, %%y\\n\\tsdiv\\t%1, %2, %0"
- [(set_attr "length" "2")])
+ [(set_attr "type" "multi")
+ (set_attr "length" "2")])
(define_insn "divdi3"
[(set (match_operand:DI 0 "register_operand" "=r")
(div:DI (match_operand:DI 1 "register_operand" "r")
(match_operand:DI 2 "arith_double_operand" "rHI")))]
"TARGET_ARCH64"
- "sdivx\\t%1, %2, %0")
+ "sdivx\\t%1, %2, %0"
+ [(set_attr "type" "idiv")])
(define_insn "*cmp_sdiv_cc_set"
[(set (reg:CC 100)
else
return \"sra\\t%1, 31, %3\\n\\twr\\t%3, 0, %%y\\n\\tnop\\n\\tnop\\n\\tnop\\n\\tsdivcc\\t%1, %2, %0\";
}"
- [(set (attr "length")
+ [(set_attr "type" "multi")
+ (set (attr "length")
(if_then_else (eq_attr "isa" "v9")
(const_int 3) (const_int 6)))])
return \"ld\\t%1, %0\\n\\tnop\\n\\tnop\\n\\tudiv\\t%0, %2, %0\";
}
}"
- [(set_attr "length" "5")])
+ [(set_attr "type" "multi")
+ (set_attr "length" "5")])
(define_insn "udivsi3_sp64"
[(set (match_operand:SI 0 "register_operand" "=r")
(match_operand:SI 2 "input_operand" "rI")))]
"TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64"
"wr\\t%%g0, 0, %%y\\n\\tudiv\\t%1, %2, %0"
- [(set_attr "length" "2")])
+ [(set_attr "type" "multi")
+ (set_attr "length" "2")])
(define_insn "udivdi3"
[(set (match_operand:DI 0 "register_operand" "=r")
(udiv:DI (match_operand:DI 1 "register_operand" "r")
(match_operand:DI 2 "arith_double_operand" "rHI")))]
"TARGET_ARCH64"
- "udivx\\t%1, %2, %0")
+ "udivx\\t%1, %2, %0"
+ [(set_attr "type" "idiv")])
(define_insn "*cmp_udiv_cc_set"
[(set (reg:CC 100)
else
return \"wr\\t%%g0, %%g0, %%y\\n\\tnop\\n\\tnop\\n\\tnop\\n\\tudivcc\\t%1, %2, %0\";
}"
- [(set (attr "length")
+ [(set_attr "type" "multi")
+ (set (attr "length")
(if_then_else (eq_attr "isa" "v9")
(const_int 2) (const_int 5)))])
(match_operand:SI 3 "register_operand" "0")))]
"TARGET_SPARCLET"
"smac\\t%1, %2, %0"
- [(set_attr "type" "imul")
- (set_attr "length" "1")])
+ [(set_attr "type" "imul")])
(define_insn "*smacdi"
[(set (match_operand:DI 0 "register_operand" "=r")
(match_operand:DI 3 "register_operand" "0")))]
"TARGET_SPARCLET"
"smacd\\t%1, %2, %L0"
- [(set_attr "type" "imul")
- (set_attr "length" "1")])
+ [(set_attr "type" "imul")])
(define_insn "*umacdi"
[(set (match_operand:DI 0 "register_operand" "=r")
(match_operand:DI 3 "register_operand" "0")))]
"TARGET_SPARCLET"
"umacd\\t%1, %2, %L0"
- [(set_attr "type" "imul")
- (set_attr "length" "1")])
+ [(set_attr "type" "imul")])
\f
;;- Boolean instructions
;; We define DImode `and' so with DImode `not' we can get
"@
#
fand\\t%1, %2, %0"
- [(set_attr "type" "ialu,fp")
- (set_attr "length" "2,1")])
+ [(set_attr "type" "*,fp")
+ (set_attr "length" "2,*")
+ (set_attr "fptype" "double")])
(define_insn "*anddi3_sp64"
[(set (match_operand:DI 0 "register_operand" "=r,b")
"@
and\\t%1, %2, %0
fand\\t%1, %2, %0"
- [(set_attr "type" "ialu,fp")
- (set_attr "length" "1,1")])
+ [(set_attr "type" "*,fp")
+ (set_attr "fptype" "double")])
(define_insn "andsi3"
[(set (match_operand:SI 0 "register_operand" "=r,d")
"@
and\\t%1, %2, %0
fands\\t%1, %2, %0"
- [(set_attr "type" "ialu,fp")
- (set_attr "length" "1,1")])
+ [(set_attr "type" "*,fp")])
(define_split
[(set (match_operand:SI 0 "register_operand" "")
"@
#
fandnot1\\t%1, %2, %0"
- [(set_attr "type" "ialu,fp")
- (set_attr "length" "2,1")])
+ [(set_attr "type" "*,fp")
+ (set_attr "length" "2,*")
+ (set_attr "fptype" "double")])
(define_split
[(set (match_operand:DI 0 "register_operand" "")
"@
andn\\t%2, %1, %0
fandnot1\\t%1, %2, %0"
- [(set_attr "type" "ialu,fp")
- (set_attr "length" "1,1")])
+ [(set_attr "type" "*,fp")
+ (set_attr "fptype" "double")])
(define_insn "*and_not_si"
[(set (match_operand:SI 0 "register_operand" "=r,d")
"@
andn\\t%2, %1, %0
fandnot1s\\t%1, %2, %0"
- [(set_attr "type" "ialu,fp")
- (set_attr "length" "1,1")])
+ [(set_attr "type" "*,fp")])
(define_expand "iordi3"
[(set (match_operand:DI 0 "register_operand" "")
"@
#
for\\t%1, %2, %0"
- [(set_attr "type" "ialu,fp")
- (set_attr "length" "2,1")])
+ [(set_attr "type" "*,fp")
+ (set_attr "length" "2,*")
+ (set_attr "fptype" "double")])
(define_insn "*iordi3_sp64"
[(set (match_operand:DI 0 "register_operand" "=r,b")
"@
or\\t%1, %2, %0
for\\t%1, %2, %0"
- [(set_attr "type" "ialu,fp")
- (set_attr "length" "1,1")])
+ [(set_attr "type" "*,fp")
+ (set_attr "fptype" "double")])
(define_insn "iorsi3"
[(set (match_operand:SI 0 "register_operand" "=r,d")
"@
or\\t%1, %2, %0
fors\\t%1, %2, %0"
- [(set_attr "type" "ialu,fp")
- (set_attr "length" "1,1")])
+ [(set_attr "type" "*,fp")])
(define_split
[(set (match_operand:SI 0 "register_operand" "")
"@
#
fornot1\\t%1, %2, %0"
- [(set_attr "type" "ialu,fp")
- (set_attr "length" "2,1")])
+ [(set_attr "type" "*,fp")
+ (set_attr "length" "2,*")
+ (set_attr "fptype" "double")])
(define_split
[(set (match_operand:DI 0 "register_operand" "")
"@
orn\\t%2, %1, %0
fornot1\\t%1, %2, %0"
- [(set_attr "type" "ialu,fp")
- (set_attr "length" "1,1")])
+ [(set_attr "type" "*,fp")
+ (set_attr "fptype" "double")])
(define_insn "*or_not_si"
[(set (match_operand:SI 0 "register_operand" "=r,d")
"@
orn\\t%2, %1, %0
fornot1s\\t%1, %2, %0"
- [(set_attr "type" "ialu,fp")
- (set_attr "length" "1,1")])
+ [(set_attr "type" "*,fp")])
(define_expand "xordi3"
[(set (match_operand:DI 0 "register_operand" "")
"@
#
fxor\\t%1, %2, %0"
- [(set_attr "length" "2,1")
- (set_attr "type" "ialu,fp")])
+ [(set_attr "type" "*,fp")
+ (set_attr "length" "2,*")
+ (set_attr "fptype" "double")])
(define_insn "*xordi3_sp64"
[(set (match_operand:DI 0 "register_operand" "=r,b")
"@
xor\\t%r1, %2, %0
fxor\\t%1, %2, %0"
- [(set_attr "type" "ialu,fp")
- (set_attr "length" "1,1")])
+ [(set_attr "type" "*,fp")
+ (set_attr "fptype" "double")])
(define_insn "*xordi3_sp64_dbl"
[(set (match_operand:DI 0 "register_operand" "=r")
(match_operand:DI 2 "const64_operand" "")))]
"(TARGET_ARCH64
&& HOST_BITS_PER_WIDE_INT != 64)"
- "xor\\t%1, %2, %0"
- [(set_attr "type" "ialu")
- (set_attr "length" "1")])
+ "xor\\t%1, %2, %0")
(define_insn "xorsi3"
[(set (match_operand:SI 0 "register_operand" "=r,d")
"@
xor\\t%r1, %2, %0
fxors\\t%1, %2, %0"
- [(set_attr "type" "ialu,fp")
- (set_attr "length" "1,1")])
+ [(set_attr "type" "*,fp")])
(define_split
[(set (match_operand:SI 0 "register_operand" "")
"@
#
fxnor\\t%1, %2, %0"
- [(set_attr "length" "2,1")
- (set_attr "type" "ialu,fp")])
+ [(set_attr "type" "*,fp")
+ (set_attr "length" "2,*")
+ (set_attr "fptype" "double")])
(define_split
[(set (match_operand:DI 0 "register_operand" "")
"@
xnor\\t%r1, %2, %0
fxnor\\t%1, %2, %0"
- [(set_attr "type" "ialu,fp")
- (set_attr "length" "1,1")])
+ [(set_attr "type" "*,fp")
+ (set_attr "fptype" "double")])
(define_insn "*xor_not_si"
[(set (match_operand:SI 0 "register_operand" "=r,d")
"@
xnor\\t%r1, %2, %0
fxnors\\t%1, %2, %0"
- [(set_attr "type" "ialu,fp")
- (set_attr "length" "1,1")])
+ [(set_attr "type" "*,fp")])
;; These correspond to the above in the case where we also (or only)
;; want to set the condition code.
(const_int 0)))]
""
"%A2cc\\t%0, %1, %%g0"
- [(set_attr "type" "compare")
- (set_attr "length" "1")])
+ [(set_attr "type" "compare")])
(define_insn "*cmp_ccx_arith_op"
[(set (reg:CCX 100)
(const_int 0)))]
"TARGET_ARCH64"
"%A2cc\\t%0, %1, %%g0"
- [(set_attr "type" "compare")
- (set_attr "length" "1")])
+ [(set_attr "type" "compare")])
(define_insn "*cmp_cc_arith_op_set"
[(set (reg:CC 100)
(match_operator:SI 4 "cc_arithop" [(match_dup 1) (match_dup 2)]))]
"GET_CODE (operands[3]) == GET_CODE (operands[4])"
"%A3cc\\t%1, %2, %0"
- [(set_attr "type" "compare")
- (set_attr "length" "1")])
+ [(set_attr "type" "compare")])
(define_insn "*cmp_ccx_arith_op_set"
[(set (reg:CCX 100)
(match_operator:DI 4 "cc_arithop" [(match_dup 1) (match_dup 2)]))]
"TARGET_ARCH64 && GET_CODE (operands[3]) == GET_CODE (operands[4])"
"%A3cc\\t%1, %2, %0"
- [(set_attr "type" "compare")
- (set_attr "length" "1")])
+ [(set_attr "type" "compare")])
(define_insn "*cmp_cc_xor_not"
[(set (reg:CC 100)
(const_int 0)))]
""
"xnorcc\\t%r0, %1, %%g0"
- [(set_attr "type" "compare")
- (set_attr "length" "1")])
+ [(set_attr "type" "compare")])
(define_insn "*cmp_ccx_xor_not"
[(set (reg:CCX 100)
(const_int 0)))]
"TARGET_ARCH64"
"xnorcc\\t%r0, %1, %%g0"
- [(set_attr "type" "compare")
- (set_attr "length" "1")])
+ [(set_attr "type" "compare")])
(define_insn "*cmp_cc_xor_not_set"
[(set (reg:CC 100)
(not:SI (xor:SI (match_dup 1) (match_dup 2))))]
""
"xnorcc\\t%r1, %2, %0"
- [(set_attr "type" "compare")
- (set_attr "length" "1")])
+ [(set_attr "type" "compare")])
(define_insn "*cmp_ccx_xor_not_set"
[(set (reg:CCX 100)
(not:DI (xor:DI (match_dup 1) (match_dup 2))))]
"TARGET_ARCH64"
"xnorcc\\t%r1, %2, %0"
- [(set_attr "type" "compare")
- (set_attr "length" "1")])
+ [(set_attr "type" "compare")])
(define_insn "*cmp_cc_arith_op_not"
[(set (reg:CC 100)
(const_int 0)))]
""
"%B2cc\\t%r1, %0, %%g0"
- [(set_attr "type" "compare")
- (set_attr "length" "1")])
+ [(set_attr "type" "compare")])
(define_insn "*cmp_ccx_arith_op_not"
[(set (reg:CCX 100)
(const_int 0)))]
"TARGET_ARCH64"
"%B2cc\\t%r1, %0, %%g0"
- [(set_attr "type" "compare")
- (set_attr "length" "1")])
+ [(set_attr "type" "compare")])
(define_insn "*cmp_cc_arith_op_not_set"
[(set (reg:CC 100)
[(not:SI (match_dup 1)) (match_dup 2)]))]
"GET_CODE (operands[3]) == GET_CODE (operands[4])"
"%B3cc\\t%r2, %1, %0"
- [(set_attr "type" "compare")
- (set_attr "length" "1")])
+ [(set_attr "type" "compare")])
(define_insn "*cmp_ccx_arith_op_not_set"
[(set (reg:CCX 100)
[(not:DI (match_dup 1)) (match_dup 2)]))]
"TARGET_ARCH64 && GET_CODE (operands[3]) == GET_CODE (operands[4])"
"%B3cc\\t%r2, %1, %0"
- [(set_attr "type" "compare")
- (set_attr "length" "1")])
+ [(set_attr "type" "compare")])
;; We cannot use the "neg" pseudo insn because the Sun assembler
;; does not know how to make it work for constants.
[(set (match_operand:DI 0 "register_operand" "=r")
(neg:DI (match_operand:DI 1 "register_operand" "r")))]
"TARGET_ARCH64"
- "sub\\t%%g0, %1, %0"
- [(set_attr "length" "1")])
+ "sub\\t%%g0, %1, %0")
(define_insn "negsi2"
[(set (match_operand:SI 0 "register_operand" "=r")
(neg:SI (match_operand:SI 1 "arith_operand" "rI")))]
""
- "sub\\t%%g0, %1, %0"
- [(set_attr "length" "1")])
+ "sub\\t%%g0, %1, %0")
(define_insn "*cmp_cc_neg"
[(set (reg:CC_NOOV 100)
(const_int 0)))]
""
"subcc\\t%%g0, %0, %%g0"
- [(set_attr "type" "compare")
- (set_attr "length" "1")])
+ [(set_attr "type" "compare")])
(define_insn "*cmp_ccx_neg"
[(set (reg:CCX_NOOV 100)
(const_int 0)))]
"TARGET_ARCH64"
"subcc\\t%%g0, %0, %%g0"
- [(set_attr "type" "compare")
- (set_attr "length" "1")])
+ [(set_attr "type" "compare")])
(define_insn "*cmp_cc_set_neg"
[(set (reg:CC_NOOV 100)
(neg:SI (match_dup 1)))]
""
"subcc\\t%%g0, %1, %0"
- [(set_attr "type" "compare")
- (set_attr "length" "1")])
+ [(set_attr "type" "compare")])
(define_insn "*cmp_ccx_set_neg"
[(set (reg:CCX_NOOV 100)
(neg:DI (match_dup 1)))]
"TARGET_ARCH64"
"subcc\\t%%g0, %1, %0"
- [(set_attr "type" "compare")
- (set_attr "length" "1")])
+ [(set_attr "type" "compare")])
;; We cannot use the "not" pseudo insn because the Sun assembler
;; does not know how to make it work for constants.
#
fnot1\\t%1, %0"
[(set_attr "type" "*,fp")
- (set_attr "length" "2,1")])
+ (set_attr "length" "2,*")
+ (set_attr "fptype" "double")])
(define_split
[(set (match_operand:DI 0 "register_operand" "")
xnor\\t%%g0, %1, %0
fnot1\\t%1, %0"
[(set_attr "type" "*,fp")
- (set_attr "length" "1")])
+ (set_attr "fptype" "double")])
(define_insn "one_cmplsi2"
[(set (match_operand:SI 0 "register_operand" "=r,d")
"@
xnor\\t%%g0, %1, %0
fnot1s\\t%1, %0"
- [(set_attr "type" "*,fp")
- (set_attr "length" "1,1")])
+ [(set_attr "type" "*,fp")])
(define_insn "*cmp_cc_not"
[(set (reg:CC 100)
(const_int 0)))]
""
"xnorcc\\t%%g0, %0, %%g0"
- [(set_attr "type" "compare")
- (set_attr "length" "1")])
+ [(set_attr "type" "compare")])
(define_insn "*cmp_ccx_not"
[(set (reg:CCX 100)
(const_int 0)))]
"TARGET_ARCH64"
"xnorcc\\t%%g0, %0, %%g0"
- [(set_attr "type" "compare")
- (set_attr "length" "1")])
+ [(set_attr "type" "compare")])
(define_insn "*cmp_cc_set_not"
[(set (reg:CC 100)
(not:SI (match_dup 1)))]
""
"xnorcc\\t%%g0, %1, %0"
- [(set_attr "type" "compare")
- (set_attr "length" "1")])
+ [(set_attr "type" "compare")])
(define_insn "*cmp_ccx_set_not"
[(set (reg:CCX 100)
(not:DI (match_dup 1)))]
"TARGET_ARCH64"
"xnorcc\\t%%g0, %1, %0"
- [(set_attr "type" "compare")
- (set_attr "length" "1")])
+ [(set_attr "type" "compare")])
\f
;; Floating point arithmetic instructions.
(match_operand:TF 2 "register_operand" "e")))]
"TARGET_FPU && TARGET_HARD_QUAD"
"faddq\\t%1, %2, %0"
- [(set_attr "type" "fp")
- (set_attr "length" "1")])
+ [(set_attr "type" "fp")])
(define_insn "adddf3"
[(set (match_operand:DF 0 "register_operand" "=e")
"TARGET_FPU"
"faddd\\t%1, %2, %0"
[(set_attr "type" "fp")
- (set_attr "length" "1")])
+ (set_attr "fptype" "double")])
(define_insn "addsf3"
[(set (match_operand:SF 0 "register_operand" "=f")
(match_operand:SF 2 "register_operand" "f")))]
"TARGET_FPU"
"fadds\\t%1, %2, %0"
- [(set_attr "type" "fp")
- (set_attr "length" "1")])
+ [(set_attr "type" "fp")])
(define_expand "subtf3"
[(set (match_operand:TF 0 "nonimmediate_operand" "")
(match_operand:TF 2 "register_operand" "e")))]
"TARGET_FPU && TARGET_HARD_QUAD"
"fsubq\\t%1, %2, %0"
- [(set_attr "type" "fp")
- (set_attr "length" "1")])
+ [(set_attr "type" "fp")])
(define_insn "subdf3"
[(set (match_operand:DF 0 "register_operand" "=e")
"TARGET_FPU"
"fsubd\\t%1, %2, %0"
[(set_attr "type" "fp")
- (set_attr "length" "1")])
+ (set_attr "fptype" "double")])
(define_insn "subsf3"
[(set (match_operand:SF 0 "register_operand" "=f")
(match_operand:SF 2 "register_operand" "f")))]
"TARGET_FPU"
"fsubs\\t%1, %2, %0"
- [(set_attr "type" "fp")
- (set_attr "length" "1")])
+ [(set_attr "type" "fp")])
(define_expand "multf3"
[(set (match_operand:TF 0 "nonimmediate_operand" "")
(match_operand:TF 2 "register_operand" "e")))]
"TARGET_FPU && TARGET_HARD_QUAD"
"fmulq\\t%1, %2, %0"
- [(set_attr "type" "fpmul")
- (set_attr "length" "1")])
+ [(set_attr "type" "fpmul")])
(define_insn "muldf3"
[(set (match_operand:DF 0 "register_operand" "=e")
"TARGET_FPU"
"fmuld\\t%1, %2, %0"
[(set_attr "type" "fpmul")
- (set_attr "length" "1")])
+ (set_attr "fptype" "double")])
(define_insn "mulsf3"
[(set (match_operand:SF 0 "register_operand" "=f")
(match_operand:SF 2 "register_operand" "f")))]
"TARGET_FPU"
"fmuls\\t%1, %2, %0"
- [(set_attr "type" "fpmul")
- (set_attr "length" "1")])
+ [(set_attr "type" "fpmul")])
(define_insn "*muldf3_extend"
[(set (match_operand:DF 0 "register_operand" "=e")
"(TARGET_V8 || TARGET_V9) && TARGET_FPU"
"fsmuld\\t%1, %2, %0"
[(set_attr "type" "fpmul")
- (set_attr "length" "1")])
+ (set_attr "fptype" "double")])
(define_insn "*multf3_extend"
[(set (match_operand:TF 0 "register_operand" "=e")
(float_extend:TF (match_operand:DF 2 "register_operand" "e"))))]
"(TARGET_V8 || TARGET_V9) && TARGET_FPU && TARGET_HARD_QUAD"
"fdmulq\\t%1, %2, %0"
- [(set_attr "type" "fpmul")
- (set_attr "length" "1")])
+ [(set_attr "type" "fpmul")])
(define_expand "divtf3"
[(set (match_operand:TF 0 "nonimmediate_operand" "")
(match_operand:TF 2 "register_operand" "e")))]
"TARGET_FPU && TARGET_HARD_QUAD"
"fdivq\\t%1, %2, %0"
- [(set_attr "type" "fpdivd")
- (set_attr "length" "1")])
+ [(set_attr "type" "fpdivd")])
(define_insn "divdf3"
[(set (match_operand:DF 0 "register_operand" "=e")
"TARGET_FPU"
"fdivd\\t%1, %2, %0"
[(set_attr "type" "fpdivd")
- (set_attr "length" "1")])
+ (set_attr "fptype" "double")])
(define_insn "divsf3"
[(set (match_operand:SF 0 "register_operand" "=f")
(match_operand:SF 2 "register_operand" "f")))]
"TARGET_FPU"
"fdivs\\t%1, %2, %0"
- [(set_attr "type" "fpdivs")
- (set_attr "length" "1")])
+ [(set_attr "type" "fpdivs")])
(define_expand "negtf2"
[(set (match_operand:TF 0 "register_operand" "=e,e")
"@
fnegs\\t%0, %0
#"
- [(set_attr "type" "fpmove")
- (set_attr "length" "1,2")])
+ [(set_attr "type" "fpmove,*")
+ (set_attr "length" "*,2")])
(define_split
[(set (match_operand:TF 0 "register_operand" "")
"@
fnegd\\t%0, %0
#"
- [(set_attr "type" "fpmove")
- (set_attr "length" "1,2")])
+ [(set_attr "type" "fpmove,*")
+ (set_attr "length" "*,2")
+ (set_attr "fptype" "double")])
(define_split
[(set (match_operand:TF 0 "register_operand" "")
"@
fnegs\\t%0, %0
#"
- [(set_attr "type" "fpmove")
- (set_attr "length" "1,2")])
+ [(set_attr "type" "fpmove,*")
+ (set_attr "length" "*,2")])
(define_split
[(set (match_operand:DF 0 "register_operand" "")
"TARGET_FPU && TARGET_V9"
"fnegd\\t%1, %0"
[(set_attr "type" "fpmove")
- (set_attr "length" "1")])
+ (set_attr "fptype" "double")])
(define_insn "negsf2"
[(set (match_operand:SF 0 "register_operand" "=f")
(neg:SF (match_operand:SF 1 "register_operand" "f")))]
"TARGET_FPU"
"fnegs\\t%1, %0"
- [(set_attr "type" "fpmove")
- (set_attr "length" "1")])
+ [(set_attr "type" "fpmove")])
(define_expand "abstf2"
[(set (match_operand:TF 0 "register_operand" "")
"@
fabss\\t%0, %0
#"
- [(set_attr "type" "fpmove")
- (set_attr "length" "1,2")])
+ [(set_attr "type" "fpmove,*")
+ (set_attr "length" "*,2")])
(define_split
[(set (match_operand:TF 0 "register_operand" "")
fabsd\\t%0, %0
fabsq\\t%1, %0"
[(set_attr "type" "fpmove")
- (set_attr "length" "1")])
+ (set_attr "fptype" "double,*")])
(define_insn "*abstf2_v9"
[(set (match_operand:TF 0 "register_operand" "=e,e")
"@
fabsd\\t%0, %0
#"
- [(set_attr "type" "fpmove")
- (set_attr "length" "1,2")])
+ [(set_attr "type" "fpmove,*")
+ (set_attr "length" "*,2")
+ (set_attr "fptype" "double,*")])
(define_split
[(set (match_operand:TF 0 "register_operand" "")
"@
fabss\\t%0, %0
#"
- [(set_attr "type" "fpmove")
- (set_attr "length" "1,2")])
+ [(set_attr "type" "fpmove,*")
+ (set_attr "length" "*,2")])
(define_split
[(set (match_operand:DF 0 "register_operand" "")
"TARGET_FPU && TARGET_V9"
"fabsd\\t%1, %0"
[(set_attr "type" "fpmove")
- (set_attr "length" "1")])
+ (set_attr "fptype" "double")])
(define_insn "abssf2"
[(set (match_operand:SF 0 "register_operand" "=f")
(abs:SF (match_operand:SF 1 "register_operand" "f")))]
"TARGET_FPU"
"fabss\\t%1, %0"
- [(set_attr "type" "fpmove")
- (set_attr "length" "1")])
+ [(set_attr "type" "fpmove")])
(define_expand "sqrttf2"
[(set (match_operand:TF 0 "register_operand" "=e")
(sqrt:TF (match_operand:TF 1 "register_operand" "e")))]
"TARGET_FPU && TARGET_HARD_QUAD"
"fsqrtq\\t%1, %0"
- [(set_attr "type" "fpsqrtd")
- (set_attr "length" "1")])
+ [(set_attr "type" "fpsqrtd")])
(define_insn "sqrtdf2"
[(set (match_operand:DF 0 "register_operand" "=e")
"TARGET_FPU"
"fsqrtd\\t%1, %0"
[(set_attr "type" "fpsqrtd")
- (set_attr "length" "1")])
+ (set_attr "fptype" "double")])
(define_insn "sqrtsf2"
[(set (match_operand:SF 0 "register_operand" "=f")
(sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
"TARGET_FPU"
"fsqrts\\t%1, %0"
- [(set_attr "type" "fpsqrts")
- (set_attr "length" "1")])
+ [(set_attr "type" "fpsqrts")])
\f
;;- arithmetic shift instructions
return \"sll\\t%1, %2, %0\";
}"
- [(set_attr "type" "shift")
- (set_attr "length" "1")])
+ [(set_attr "type" "shift")])
;; We special case multiplication by two, as add can be done
;; in both ALUs, while shift only in IEU0 on UltraSPARC.
(ashift:SI (match_operand:SI 1 "register_operand" "r")
(const_int 1)))]
""
- "add\\t%1, %1, %0"
- [(set_attr "length" "1")])
+ "add\\t%1, %1, %0")
(define_expand "ashldi3"
[(set (match_operand:DI 0 "register_operand" "=r")
(ashift:DI (match_operand:DI 1 "register_operand" "r")
(const_int 1)))]
"TARGET_ARCH64"
- "add\\t%1, %1, %0"
- [(set_attr "length" "1")])
+ "add\\t%1, %1, %0")
(define_insn "*ashldi3_sp64"
[(set (match_operand:DI 0 "register_operand" "=r")
return \"sllx\\t%1, %2, %0\";
}"
- [(set_attr "type" "shift")
- (set_attr "length" "1")])
+ [(set_attr "type" "shift")])
;; XXX UGH!
(define_insn "ashldi3_v8plus"
(clobber (match_scratch:SI 3 "=X,X,&h"))]
"TARGET_V8PLUS"
"*return sparc_v8plus_shift (operands, insn, \"sllx\");"
- [(set_attr "length" "5,5,6")])
+ [(set_attr "type" "multi")
+ (set_attr "length" "5,5,6")])
;; Optimize (1LL<<x)-1
;; XXX this also needs to be fixed to handle equal subregs
; return \"mov\\t1, %L0\;sllx\\t%L0, %1, %L0\;sub\\t%L0, 1, %L0\;srlx\\t%L0, 32, %H0\";
; return \"mov\\t1, %H0\;sllx\\t%H0, %1, %L0\;sub\\t%L0, 1, %L0\;srlx\\t%L0, 32, %H0\";
;}"
-; [(set_attr "length" "4")])
+; [(set_attr "type" "multi")
+; (set_attr "length" "4")])
(define_insn "*cmp_cc_ashift_1"
[(set (reg:CC_NOOV 100)
(const_int 0)))]
""
"addcc\\t%0, %0, %%g0"
- [(set_attr "type" "compare")
- (set_attr "length" "1")])
+ [(set_attr "type" "compare")])
(define_insn "*cmp_cc_set_ashift_1"
[(set (reg:CC_NOOV 100)
(ashift:SI (match_dup 1) (const_int 1)))]
""
"addcc\\t%1, %1, %0"
- [(set_attr "type" "compare")
- (set_attr "length" "1")])
+ [(set_attr "type" "compare")])
(define_insn "ashrsi3"
[(set (match_operand:SI 0 "register_operand" "=r")
return \"sra\\t%1, %2, %0\";
}"
- [(set_attr "type" "shift")
- (set_attr "length" "1")])
+ [(set_attr "type" "shift")])
(define_insn "*ashrsi3_extend"
[(set (match_operand:DI 0 "register_operand" "=r")
(match_operand:SI 2 "arith_operand" "r"))))]
"TARGET_ARCH64"
"sra\\t%1, %2, %0"
- [(set_attr "type" "shift")
- (set_attr "length" "1")])
+ [(set_attr "type" "shift")])
;; This handles the case as above, but with constant shift instead of
;; register. Combiner "simplifies" it for us a little bit though.
return \"sra\\t%1, %2, %0\";
}"
- [(set_attr "type" "shift")
- (set_attr "length" "1")])
+ [(set_attr "type" "shift")])
(define_expand "ashrdi3"
[(set (match_operand:DI 0 "register_operand" "=r")
return \"srax\\t%1, %2, %0\";
}"
- [(set_attr "type" "shift")
- (set_attr "length" "1")])
+ [(set_attr "type" "shift")])
;; XXX
(define_insn "ashrdi3_v8plus"
(clobber (match_scratch:SI 3 "=X,X,&h"))]
"TARGET_V8PLUS"
"*return sparc_v8plus_shift (operands, insn, \"srax\");"
- [(set_attr "length" "5,5,6")])
+ [(set_attr "type" "multi")
+ (set_attr "length" "5,5,6")])
(define_insn "lshrsi3"
[(set (match_operand:SI 0 "register_operand" "=r")
return \"srl\\t%1, %2, %0\";
}"
- [(set_attr "type" "shift")
- (set_attr "length" "1")])
+ [(set_attr "type" "shift")])
;; This handles the case where
;; (zero_extend:DI (lshiftrt:SI (match_operand:SI) (match_operand:SI))),
&& GET_CODE (operands[3]) == CONST_INT
&& (unsigned HOST_WIDE_INT) INTVAL (operands[3]) == 0xffffffff))"
"srl\\t%1, %2, %0"
- [(set_attr "type" "shift")
- (set_attr "length" "1")])
+ [(set_attr "type" "shift")])
;; This handles the case where
;; (lshiftrt:DI (zero_extend:DI (match_operand:SI)) (const_int >=0 < 32))
return \"srl\\t%1, %2, %0\";
}"
- [(set_attr "type" "shift")
- (set_attr "length" "1")])
+ [(set_attr "type" "shift")])
(define_expand "lshrdi3"
[(set (match_operand:DI 0 "register_operand" "=r")
return \"srlx\\t%1, %2, %0\";
}"
- [(set_attr "type" "shift")
- (set_attr "length" "1")])
+ [(set_attr "type" "shift")])
;; XXX
(define_insn "lshrdi3_v8plus"
(clobber (match_scratch:SI 3 "=X,X,&h"))]
"TARGET_V8PLUS"
"*return sparc_v8plus_shift (operands, insn, \"srlx\");"
- [(set_attr "length" "5,5,6")])
+ [(set_attr "type" "multi")
+ (set_attr "length" "5,5,6")])
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r")
return \"srax\\t%1, %2, %0\";
}"
- [(set_attr "type" "shift")
- (set_attr "length" "1")])
+ [(set_attr "type" "shift")])
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r")
return \"srlx\\t%1, %2, %0\";
}"
- [(set_attr "type" "shift")
- (set_attr "length" "1")])
+ [(set_attr "type" "shift")])
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r")
return \"srax\\t%1, %2, %0\";
}"
- [(set_attr "type" "shift")
- (set_attr "length" "1")])
+ [(set_attr "type" "shift")])
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r")
return \"srlx\\t%1, %2, %0\";
}"
- [(set_attr "type" "shift")
- (set_attr "length" "1")])
+ [(set_attr "type" "shift")])
\f
;; Unconditional and other jump instructions
;; On the Sparc, by setting the annul bit on an unconditional branch, the
(match_operand:SI 1 "register_operand" "r")] 1)]
"! TARGET_ARCH64"
"cmp\\t%1, 0\;be,a\\t.+8\;add\\t%0, 4, %0"
- [(set_attr "type" "multi")])
+ [(set_attr "type" "multi")
+ (set_attr "length" "3")])
\f
(define_insn "return"
[(return)
(define_insn "nop"
[(const_int 0)]
""
- "nop"
- [(set_attr "type" "ialu")
- (set_attr "length" "1")])
+ "nop")
(define_expand "indirect_jump"
[(set (pc) (match_operand 0 "address_operand" "p"))]
[(unspec_volatile [(const_int 0)] 1)]
""
"* return TARGET_V9 ? \"flushw\" : \"ta\\t3\";"
- [(set_attr "type" "misc")
- (set_attr "length" "1")])
+ [(set_attr "type" "misc")])
(define_insn "goto_handler_and_restore"
[(unspec_volatile [(match_operand 0 "register_operand" "=r")] 2)]
"GET_MODE (operands[0]) == Pmode"
"jmp\\t%0+0\\n\\trestore"
- [(set_attr "type" "misc")
+ [(set_attr "type" "multi")
(set_attr "length" "2")])
;;(define_insn "goto_handler_and_restore_v9"
;; "@
;; return\\t%0+0\\n\\tmov\\t%2, %Y1
;; sethi\\t%%hi(%2), %1\\n\\treturn\\t%0+0\\n\\tor\\t%Y1, %%lo(%2), %Y1"
-;; [(set_attr "type" "misc")
+;; [(set_attr "type" "multi")
;; (set_attr "length" "2,3")])
;;
;;(define_insn "*goto_handler_and_restore_v9_sp64"
;; "@
;; return\\t%0+0\\n\\tmov\\t%2, %Y1
;; sethi\\t%%hi(%2), %1\\n\\treturn\\t%0+0\\n\\tor\\t%Y1, %%lo(%2), %Y1"
-;; [(set_attr "type" "misc")
+;; [(set_attr "type" "multi")
;; (set_attr "length" "2,3")])
;; For __builtin_setjmp we need to flush register windows iff the function
DONE;
}")
+;; ??? Should set length to zero when !current_function_calls_alloca,
+;; ??? but there is no easy way to get at that definition. It would
+;; ??? require including function.h into sparc-protos.h and that is
+;; ??? likely not a good idea. -DaveM
(define_insn "do_builtin_setjmp_setup"
[(unspec_volatile [(const_int 0)] 5)]
""
return \"flushw\";
return \"ta\\t3\";
}"
- [(set_attr "type" "misc")
- (set_attr "length" "1")])
+ [(set_attr "type" "misc")])
;; Pattern for use after a setjmp to store FP and the return register
;; into the stack area.
else
return \"ret\\n\\trestore %%g0, %1, %Y0\";
}"
- [(set_attr "type" "multi")])
+ [(set_attr "type" "multi")
+ (set_attr "length" "2")])
(define_insn "*return_hi"
[(set (match_operand:HI 0 "restore_operand" "")
else
return \"ret\;restore %%g0, %1, %Y0\";
}"
- [(set_attr "type" "multi")])
+ [(set_attr "type" "multi")
+ (set_attr "length" "2")])
(define_insn "*return_si"
[(set (match_operand:SI 0 "restore_operand" "")
else
return \"ret\;restore %%g0, %1, %Y0\";
}"
- [(set_attr "type" "multi")])
+ [(set_attr "type" "multi")
+ (set_attr "length" "2")])
;; The following pattern is only generated by delayed-branch scheduling,
;; when the insn winds up in the epilogue. This can happen not only when
else
return \"ret\;restore %%g0, %1, %Y0\";
}"
- [(set_attr "type" "multi")])
+ [(set_attr "type" "multi")
+ (set_attr "length" "2")])
(define_insn "*return_df_no_fpu"
[(set (match_operand:DF 0 "restore_operand" "=r")
else
return \"ret\;restore %%g0, %1, %Y0\";
}"
- [(set_attr "type" "multi")])
+ [(set_attr "type" "multi")
+ (set_attr "length" "2")])
(define_insn "*return_addsi"
[(set (match_operand:SI 0 "restore_operand" "")
else
return \"ret\;restore %r1, %2, %Y0\";
}"
- [(set_attr "type" "multi")])
+ [(set_attr "type" "multi")
+ (set_attr "length" "2")])
(define_insn "*return_losum_si"
[(set (match_operand:SI 0 "restore_operand" "")
else
return \"ret\;restore %r1, %%lo(%a2), %Y0\";
}"
- [(set_attr "type" "multi")])
+ [(set_attr "type" "multi")
+ (set_attr "length" "2")])
(define_insn "*return_di"
[(set (match_operand:DI 0 "restore_operand" "")
(return)]
"TARGET_ARCH64 && ! TARGET_EPILOGUE"
"ret\;restore %%g0, %1, %Y0"
- [(set_attr "type" "multi")])
+ [(set_attr "type" "multi")
+ (set_attr "length" "2")])
(define_insn "*return_adddi"
[(set (match_operand:DI 0 "restore_operand" "")
(return)]
"TARGET_ARCH64 && ! TARGET_EPILOGUE"
"ret\;restore %r1, %2, %Y0"
- [(set_attr "type" "multi")])
+ [(set_attr "type" "multi")
+ (set_attr "length" "2")])
(define_insn "*return_losum_di"
[(set (match_operand:DI 0 "restore_operand" "")
(return)]
"TARGET_ARCH64 && ! TARGET_EPILOGUE && ! TARGET_CM_MEDMID"
"ret\;restore %r1, %%lo(%a2), %Y0"
- [(set_attr "type" "multi")])
+ [(set_attr "type" "multi")
+ (set_attr "length" "2")])
;; The following pattern is only generated by delayed-branch scheduling,
;; when the insn winds up in the epilogue.
(return)]
"! TARGET_EPILOGUE"
"ret\;fmovs\\t%0, %%f0"
- [(set_attr "type" "multi")])
+ [(set_attr "type" "multi")
+ (set_attr "length" "2")])
;; Now peepholes to do a call followed by a jump.
[(trap_if (const_int 1) (const_int 5))]
""
"ta\\t5"
- [(set_attr "type" "misc")
- (set_attr "length" "1")])
+ [(set_attr "type" "misc")])
(define_expand "conditional_trap"
[(trap_if (match_operator 0 "noov_compare_op"
(match_operand:SI 1 "arith_operand" "rM"))]
""
"t%C0\\t%1"
- [(set_attr "type" "misc")
- (set_attr "length" "1")])
+ [(set_attr "type" "misc")])
(define_insn ""
[(trap_if (match_operator 0 "noov_compare_op" [(reg:CCX 100) (const_int 0)])
(match_operand:SI 1 "arith_operand" "rM"))]
"TARGET_V9"
"t%C0\\t%%xcc, %1"
- [(set_attr "type" "misc")
- (set_attr "length" "1")])
+ [(set_attr "type" "misc")])
projects / platform / upstream / linaro-gcc.git / commitdiff