u32 *reg_state = ce->lrc_reg_state;
GEM_BUG_ON(!IS_ALIGNED(rq->tail, 8));
+ GEM_BUG_ON(rq->tail >= rq->ring->size);
reg_state[CTX_RING_TAIL+1] = rq->tail;
/* True 32b PPGTT with dynamic page allocation: update PDP
intel_ring_wrap(request->ring,
request->wa_tail - WA_TAIL_DWORDS*sizeof(u32));
GEM_BUG_ON(!IS_ALIGNED(request->tail, 8));
+ GEM_BUG_ON(request->tail >= request->ring->size);
}
static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
*cs++ = MI_NOOP;
request->tail = intel_ring_offset(request, cs);
GEM_BUG_ON(!IS_ALIGNED(request->tail, 8));
+ GEM_BUG_ON(request->tail >= request->ring->size);
gen8_emit_wa_tail(request, cs);
}
*cs++ = MI_NOOP;
request->tail = intel_ring_offset(request, cs);
GEM_BUG_ON(!IS_ALIGNED(request->tail, 8));
+ GEM_BUG_ON(request->tail >= request->ring->size);
gen8_emit_wa_tail(request, cs);
}
i915_gem_request_submit(request);
GEM_BUG_ON(!IS_ALIGNED(request->tail, 8));
+ GEM_BUG_ON(request->tail >= request->ring->size);
I915_WRITE_TAIL(request->engine, request->tail);
}
req->tail = intel_ring_offset(req, cs);
GEM_BUG_ON(!IS_ALIGNED(req->tail, 8));
+ GEM_BUG_ON(req->tail >= req->ring->size);
}
static const int i9xx_emit_breadcrumb_sz = 4;
req->tail = intel_ring_offset(req, cs);
GEM_BUG_ON(!IS_ALIGNED(req->tail, 8));
+ GEM_BUG_ON(req->tail >= req->ring->size);
}
static const int gen8_render_emit_breadcrumb_sz = 8;