ARM: dts: Add xo to sdhc clock node on qcom platforms
authorRitesh Harjani <riteshh@codeaurora.org>
Mon, 21 Nov 2016 06:37:14 +0000 (12:07 +0530)
committerAndy Gross <andy.gross@linaro.org>
Thu, 24 Nov 2016 06:31:02 +0000 (00:31 -0600)
Add xo entry to sdhc clock node on all qcom platforms.

Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
arch/arm/boot/dts/qcom-apq8084.dtsi
arch/arm/boot/dts/qcom-msm8974.dtsi

index 39eb7a4..80d4886 100644 (file)
        };
 
        clocks {
-               xo_board {
+               xo_board: xo_board {
                        compatible = "fixed-clock";
                        #clock-cells = <0>;
                        clock-frequency = <19200000>;
                };
 
-               sleep_clk {
+               sleep_clk: sleep_clk {
                        compatible = "fixed-clock";
                        #clock-cells = <0>;
                        clock-frequency = <32768>;
                        reg-names = "hc_mem", "core_mem";
                        interrupts = <0 123 0>, <0 138 0>;
                        interrupt-names = "hc_irq", "pwr_irq";
-                       clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
-                       clock-names = "core", "iface";
+                       clocks = <&gcc GCC_SDCC1_APPS_CLK>,
+                                <&gcc GCC_SDCC1_AHB_CLK>,
+                                <&xo_board>;
+                       clock-names = "core", "iface", "xo";
                        status = "disabled";
                };
 
                        reg-names = "hc_mem", "core_mem";
                        interrupts = <0 125 0>, <0 221 0>;
                        interrupt-names = "hc_irq", "pwr_irq";
-                       clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
-                       clock-names = "core", "iface";
+                       clocks = <&gcc GCC_SDCC2_APPS_CLK>,
+                                <&gcc GCC_SDCC2_AHB_CLK>,
+                                <&xo_board>;
+                       clock-names = "core", "iface", "xo";
                        status = "disabled";
                };
 
index d210947..49d579f 100644 (file)
        };
 
        clocks {
-               xo_board {
+               xo_board: xo_board {
                        compatible = "fixed-clock";
                        #clock-cells = <0>;
                        clock-frequency = <19200000>;
                };
 
-               sleep_clk {
+               sleep_clk: sleep_clk {
                        compatible = "fixed-clock";
                        #clock-cells = <0>;
                        clock-frequency = <32768>;
                        reg-names = "hc_mem", "core_mem";
                        interrupts = <0 123 0>, <0 138 0>;
                        interrupt-names = "hc_irq", "pwr_irq";
-                       clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
-                       clock-names = "core", "iface";
+                       clocks = <&gcc GCC_SDCC1_APPS_CLK>,
+                                <&gcc GCC_SDCC1_AHB_CLK>,
+                                <&xo_board>;
+                       clock-names = "core", "iface", "xo";
                        status = "disabled";
                };
 
                        reg-names = "hc_mem", "core_mem";
                        interrupts = <0 125 0>, <0 221 0>;
                        interrupt-names = "hc_irq", "pwr_irq";
-                       clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
-                       clock-names = "core", "iface";
+                       clocks = <&gcc GCC_SDCC2_APPS_CLK>,
+                                <&gcc GCC_SDCC2_AHB_CLK>,
+                                <&xo_board>;
+                       clock-names = "core", "iface", "xo";
                        status = "disabled";
                };