#include "mxs_init.h"
-void mxs_power_clock2xtal(void)
+static void mxs_power_clock2xtal(void)
{
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
&clkctrl_regs->hw_clkctrl_clkseq_set);
}
-void mxs_power_clock2pll(void)
+static void mxs_power_clock2pll(void)
{
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
CLKCTRL_CLKSEQ_BYPASS_CPU);
}
-void mxs_power_clear_auto_restart(void)
+static void mxs_power_clear_auto_restart(void)
{
struct mxs_rtc_regs *rtc_regs =
(struct mxs_rtc_regs *)MXS_RTC_BASE;
;
}
-void mxs_power_set_linreg(void)
+static void mxs_power_set_linreg(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW);
}
-int mxs_get_batt_volt(void)
+static int mxs_get_batt_volt(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
return volt;
}
-int mxs_is_batt_ready(void)
+static int mxs_is_batt_ready(void)
{
return (mxs_get_batt_volt() >= 3600);
}
-int mxs_is_batt_good(void)
+static int mxs_is_batt_good(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
return 0;
}
-void mxs_power_setup_5v_detect(void)
+static void mxs_power_setup_5v_detect(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
POWER_5VCTRL_PWRUP_VBUS_CMPS);
}
-void mxs_src_power_init(void)
+static void mxs_src_power_init(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
}
-void mxs_power_init_4p2_params(void)
+static void mxs_power_init_4p2_params(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
}
-void mxs_enable_4p2_dcdc_input(int xfer)
+static void mxs_enable_4p2_dcdc_input(int xfer)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
POWER_CTRL_ENIRQ_VDD5V_DROOP);
}
-void mxs_power_init_4p2_regulator(void)
+static void mxs_power_init_4p2_regulator(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
}
-void mxs_power_init_dcdc_4p2_source(void)
+static void mxs_power_init_dcdc_4p2_source(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
}
}
-void mxs_power_enable_4p2(void)
+static void mxs_power_enable_4p2(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
&power_regs->hw_power_charge_clr);
}
-void mxs_boot_valid_5v(void)
+static void mxs_boot_valid_5v(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
mxs_power_enable_4p2();
}
-void mxs_powerdown(void)
+static void mxs_powerdown(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
&power_regs->hw_power_reset);
}
-void mxs_batt_boot(void)
+static void mxs_batt_boot(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
}
-void mxs_handle_5v_conflict(void)
+static void mxs_handle_5v_conflict(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
}
}
-void mxs_5v_boot(void)
+static void mxs_5v_boot(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
mxs_handle_5v_conflict();
}
-void mxs_init_batt_bo(void)
+static void mxs_init_batt_bo(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
}
-void mxs_switch_vddd_to_dcdc_source(void)
+static void mxs_switch_vddd_to_dcdc_source(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
POWER_VDDDCTRL_DISABLE_STEPPING);
}
-void mxs_power_configure_power_source(void)
+static void mxs_power_configure_power_source(void)
{
int batt_ready, batt_good;
struct mxs_power_regs *power_regs =
mxs_switch_vddd_to_dcdc_source();
}
-void mxs_enable_output_rail_protection(void)
+static void mxs_enable_output_rail_protection(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
POWER_VDDIOCTRL_PWDN_BRNOUT);
}
-int mxs_get_vddio_power_source_off(void)
+static int mxs_get_vddio_power_source_off(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
}
-int mxs_get_vddd_power_source_off(void)
+static int mxs_get_vddd_power_source_off(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t bo_offset_offset;
};
-const struct mxs_vddx_cfg mxs_vddio_cfg = {
+static const struct mxs_vddx_cfg mxs_vddio_cfg = {
.reg = &(((struct mxs_power_regs *)MXS_POWER_BASE)->
hw_power_vddioctrl),
.step_mV = 50,
.bo_offset_offset = POWER_VDDIOCTRL_BO_OFFSET_OFFSET,
};
-const struct mxs_vddx_cfg mxs_vddd_cfg = {
+static const struct mxs_vddx_cfg mxs_vddd_cfg = {
.reg = &(((struct mxs_power_regs *)MXS_POWER_BASE)->
hw_power_vdddctrl),
.step_mV = 25,
new_brownout << cfg->bo_offset_offset);
}
-void mxs_setup_batt_detect(void)
+static void mxs_setup_batt_detect(void)
{
mxs_lradc_init();
mxs_lradc_enable_batt_measurement();