drm/amd/amdgpu: power up sdma engine when S3 resume back
authorPrike Liang <Prike.Liang@amd.com>
Wed, 11 Sep 2019 05:15:17 +0000 (13:15 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 16 Sep 2019 15:16:07 +0000 (10:16 -0500)
The sdma_v4 should be ungated when the IP resume back,
otherwise it will hang up and resume time out error.

Signed-off-by: Prike Liang <Prike.Liang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c

index 61bd103..5803fcb 100644 (file)
@@ -948,6 +948,7 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block
        case AMD_IP_BLOCK_TYPE_UVD:
        case AMD_IP_BLOCK_TYPE_VCN:
        case AMD_IP_BLOCK_TYPE_VCE:
+       case AMD_IP_BLOCK_TYPE_SDMA:
                if (swsmu)
                        ret = smu_dpm_set_power_gate(&adev->smu, block_type, gate);
                else
@@ -956,7 +957,6 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block
                break;
        case AMD_IP_BLOCK_TYPE_GMC:
        case AMD_IP_BLOCK_TYPE_ACP:
-       case AMD_IP_BLOCK_TYPE_SDMA:
                ret = ((adev)->powerplay.pp_funcs->set_powergating_by_smu(
                                (adev)->powerplay.pp_handle, block_type, gate));
                break;
index c3635c4..265b9c0 100644 (file)
@@ -1804,8 +1804,9 @@ static int sdma_v4_0_hw_init(void *handle)
        int r;
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-       if (adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs &&
-                       adev->powerplay.pp_funcs->set_powergating_by_smu)
+       if ((adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs &&
+                       adev->powerplay.pp_funcs->set_powergating_by_smu) ||
+                       adev->asic_type == CHIP_RENOIR)
                amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false);
 
        if (!amdgpu_sriov_vf(adev))
@@ -1832,8 +1833,9 @@ static int sdma_v4_0_hw_fini(void *handle)
        sdma_v4_0_ctx_switch_enable(adev, false);
        sdma_v4_0_enable(adev, false);
 
-       if (adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs
-                       && adev->powerplay.pp_funcs->set_powergating_by_smu)
+       if ((adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs
+                       && adev->powerplay.pp_funcs->set_powergating_by_smu) ||
+                       adev->asic_type == CHIP_RENOIR)
                amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, true);
 
        return 0;
index dd97809..90fa444 100644 (file)
@@ -400,6 +400,9 @@ int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
        case AMD_IP_BLOCK_TYPE_GFX:
                ret = smu_gfx_off_control(smu, gate);
                break;
+       case AMD_IP_BLOCK_TYPE_SDMA:
+               ret = smu_powergate_sdma(smu, gate);
+               break;
        default:
                break;
        }