drm/i915/display/tgl: Use TGL DP tables for eDP ports without low power support

Reusing icl_get_combo_buf_trans() for eDP was causing the wrong table
being used when the eDP port don't support low power voltage swing table.

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Cc: Lee Shawn C <shawn.c.lee@intel.com>
Cc: Khaled Almahallawy <khaled.almahallawy@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200826201549.83658-1-jose.souza@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index ff05a85..cdd4579 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1088,30 +1088,44 @@ tgl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
 {
        struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 
-       if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.hobl) {
-               struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-
-               if (!intel_dp->hobl_failed && rate <= 540000) {
-                       /* Same table applies to TGL, RKL and DG1 */
-                       *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_edp_hbr2_hobl);
-                       return tgl_combo_phy_ddi_translations_edp_hbr2_hobl;
+       switch (type) {
+       case INTEL_OUTPUT_HDMI:
+               *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
+               return icl_combo_phy_ddi_translations_hdmi;
+       case INTEL_OUTPUT_EDP:
+               if (dev_priv->vbt.edp.hobl) {
+                       struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+                       if (!intel_dp->hobl_failed && rate <= 540000) {
+                               /* Same table applies to TGL, RKL and DG1 */
+                               *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_edp_hbr2_hobl);
+                               return tgl_combo_phy_ddi_translations_edp_hbr2_hobl;
+                       }
                }
-       }
 
-       if (type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_EDP) {
-               return icl_get_combo_buf_trans(encoder, type, rate, n_entries);
-       } else if (rate > 270000) {
-               if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
-                       *n_entries = ARRAY_SIZE(tgl_uy_combo_phy_ddi_translations_dp_hbr2);
-                       return tgl_uy_combo_phy_ddi_translations_dp_hbr2;
+               if (rate > 540000) {
+                       *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
+                       return icl_combo_phy_ddi_translations_edp_hbr3;
+               } else if (dev_priv->vbt.edp.low_vswing) {
+                       *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
+                       return icl_combo_phy_ddi_translations_edp_hbr2;
+               }
+               /* fall through */
+       default:
+               /* All combo DP and eDP ports that do not support low_vswing */
+               if (rate > 270000) {
+                       if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
+                               *n_entries = ARRAY_SIZE(tgl_uy_combo_phy_ddi_translations_dp_hbr2);
+                               return tgl_uy_combo_phy_ddi_translations_dp_hbr2;
+                       }
+
+                       *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr2);
+                       return tgl_combo_phy_ddi_translations_dp_hbr2;
                }
 
-               *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr2);
-               return tgl_combo_phy_ddi_translations_dp_hbr2;
+               *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr);
+               return tgl_combo_phy_ddi_translations_dp_hbr;
        }
-
-       *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr);
-       return tgl_combo_phy_ddi_translations_dp_hbr;
 }
 
 static const struct tgl_dkl_phy_ddi_buf_trans *