clk:starfive: Adjust the format

Adjust and modify the clock driver's format

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>

diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 41eec16..741303e 100755 (executable)
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -106,12 +106,12 @@ choice
                 bool "FPGA"
                 help
                   This enables support for StarFive SoC FPGA board type Hardware.
-       
+
         config STARFIVE_BOARD_EVB
                 bool "EVB"
                 help
                   This enables support for StarFive SoC EVB board type Hardware.
-       
+
        config STARFIVE_BOARD_VISIONFIVE
                 bool "Visionfive"
                 help

diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
index 0332eea..60aac0d 100755 (executable)
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -5,7 +5,7 @@ config CLK_STARFIVE_JH7110
        depends on SOC_STARFIVE_JH7110 || COMPILE_TEST
        default y if SOC_STARFIVE_JH7110
        help
-               Say yes here to support the clock controller on the StarFive 
+               Say yes here to support the clock controller on the StarFive
                JH7110 SoC.
 
 config CLK_STARFIVE_JH7110_VOUT
@@ -13,5 +13,5 @@ config CLK_STARFIVE_JH7110_VOUT
        depends on CLK_STARFIVE_JH7110
        default y if SOC_STARFIVE_JH7110
        help
-               Say yes here to support the vout clocks on the StarFive 
+               Say yes here to support the vout clocks on the StarFive
                JH7100 SoC.

diff --git a/drivers/clk/starfive/clk-starfive-jh7110-aon.c b/drivers/clk/starfive/clk-starfive-jh7110-aon.c
index a5a4bbb..c39239b 100755 (executable)
--- a/drivers/clk/starfive/clk-starfive-jh7110-aon.c
+++ b/drivers/clk/starfive/clk-starfive-jh7110-aon.c
@@ -22,41 +22,41 @@ static const struct jh7110_clk_data jh7110_clk_aon_data[] __initconst = {
        //gmac5
        JH7110_GATE(JH7110_U0_GMAC5_CLK_AHB, 
                        "u0_dw_gmac5_axi64_clk_ahb", 0, JH7110_AON_AHB),
-       JH7110_GATE(JH7110_U0_GMAC5_CLK_AXI, 
+       JH7110_GATE(JH7110_U0_GMAC5_CLK_AXI,
                        "u0_dw_gmac5_axi64_clk_axi", 0, JH7110_AON_AHB),
-       JH7110__DIV(JH7110_GMAC0_RMII_RTX, 
+       JH7110__DIV(JH7110_GMAC0_RMII_RTX,
                        "gmac0_rmii_rtx", 30, JH7110_GMAC0_RMII_REFIN),
-       JH7110_GMUX(JH7110_U0_GMAC5_CLK_TX, 
+       JH7110_GMUX(JH7110_U0_GMAC5_CLK_TX,
                        "u0_dw_gmac5_axi64_clk_tx", 0, 2,
                        JH7110_GMAC0_GTXCLK,
                        JH7110_GMAC0_RMII_RTX),
-       JH7110__INV(JH7110_U0_GMAC5_CLK_TX_INV, 
-                       "u0_dw_gmac5_axi64_clk_tx_inv", 
+       JH7110__INV(JH7110_U0_GMAC5_CLK_TX_INV,
+                       "u0_dw_gmac5_axi64_clk_tx_inv",
                        JH7110_U0_GMAC5_CLK_TX),
-       JH7110__MUX(JH7110_U0_GMAC5_CLK_RX, 
+       JH7110__MUX(JH7110_U0_GMAC5_CLK_RX,
                        "u0_dw_gmac5_axi64_clk_rx", 2,
                        JH7110_GMAC0_RGMII_RXIN,
                        JH7110_GMAC0_RMII_RTX),
-       JH7110__INV(JH7110_U0_GMAC5_CLK_RX_INV, 
-                       "u0_dw_gmac5_axi64_clk_rx_inv", 
+       JH7110__INV(JH7110_U0_GMAC5_CLK_RX_INV,
+                       "u0_dw_gmac5_axi64_clk_rx_inv",
                        JH7110_U0_GMAC5_CLK_RX),
        //otpc
-       JH7110_GATE(JH7110_OTPC_CLK_APB, 
+       JH7110_GATE(JH7110_OTPC_CLK_APB,
                        "u0_otpc_clk_apb", 0, JH7110_AON_APB),
        //rtc
-       JH7110_GATE(JH7110_RTC_HMS_CLK_APB, 
+       JH7110_GATE(JH7110_RTC_HMS_CLK_APB,
                        "u0_rtc_hms_clk_apb", 0, JH7110_AON_APB),
-       JH7110__DIV(JH7110_RTC_INTERNAL, 
+       JH7110__DIV(JH7110_RTC_INTERNAL,
                        "rtc_internal", 1022, JH7110_OSC),
-       JH7110__MUX(JH7110_RTC_HMS_CLK_OSC32K, 
+       JH7110__MUX(JH7110_RTC_HMS_CLK_OSC32K,
                        "u0_rtc_hms_clk_osc32k", 2,
                        JH7110_CLK_RTC,
                        JH7110_RTC_INTERNAL),
-       JH7110_GATE(JH7110_RTC_HMS_CLK_CAL, 
+       JH7110_GATE(JH7110_RTC_HMS_CLK_CAL,
                        "u0_rtc_hms_clk_cal", 0, JH7110_OSC),
 };
 
-int __init clk_starfive_jh7110_aon_init(struct platform_device *pdev, 
+int __init clk_starfive_jh7110_aon_init(struct platform_device *pdev,
                                                struct jh7110_clk_priv *priv)
 {
        unsigned int idx;
@@ -66,43 +66,43 @@ int __init clk_starfive_jh7110_aon_init(struct platform_device *pdev,
        if (IS_ERR(priv->aon_base))
                return PTR_ERR(priv->aon_base);
 
-       priv->pll[PLL_OF(JH7110_U0_GMAC5_CLK_PTP)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_U0_GMAC5_CLK_PTP)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u0_dw_gmac5_axi64_clk_ptp", "gmac0_ptp", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_U0_GMAC5_CLK_RMII)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
-                       "u0_dw_gmac5_axi64_clk_rmii", 
+       priv->pll[PLL_OF(JH7110_U0_GMAC5_CLK_RMII)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
+                       "u0_dw_gmac5_axi64_clk_rmii",
                        "gmac0_rmii_refin", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_AON_SYSCON_PCLK)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_AON_SYSCON_PCLK)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u0_aon_syscon_pclk", "aon_apb", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_AON_IOMUX_PCLK)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_AON_IOMUX_PCLK)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u0_aon_iomux_pclk", "aon_apb", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_AON_CRG_PCLK)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_AON_CRG_PCLK)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u0_aon_crg_pclk", "aon_apb", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_PMU_CLK_APB)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_PMU_CLK_APB)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u0_pmu_clk_apb", "aon_apb", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_PMU_CLK_WKUP)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_PMU_CLK_WKUP)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u0_pmu_clk_wkup", "aon_apb", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_RTC_HMS_CLK_OSC32K_G)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
-                       "u0_rtc_hms_clk_osc32k_g", 
+       priv->pll[PLL_OF(JH7110_RTC_HMS_CLK_OSC32K_G)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
+                       "u0_rtc_hms_clk_osc32k_g",
                        "u0_rtc_hms_clk_osc32k", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_32K_OUT)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_32K_OUT)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "32k_out", "clk_rtc", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_RESET0_CTRL_CLK_SRC)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_RESET0_CTRL_CLK_SRC)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u0_reset_ctrl_clk_src", "osc", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_PCLK_MUX_FUNC_PCLK)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_PCLK_MUX_FUNC_PCLK)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u1_pclk_mux_func_pclk", "aon_apb_func", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_PCLK_MUX_BIST_PCLK)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_PCLK_MUX_BIST_PCLK)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u1_pclk_mux_bist_pclk", "bist_apb", 0, 1, 1);
 
        for (idx = JH7110_CLK_STG_REG_END; idx < JH7110_CLK_REG_END; idx++) {

diff --git a/drivers/clk/starfive/clk-starfive-jh7110-gen.c b/drivers/clk/starfive/clk-starfive-jh7110-gen.c
index d1c70a8..437065b 100755 (executable)
--- a/drivers/clk/starfive/clk-starfive-jh7110-gen.c
+++ b/drivers/clk/starfive/clk-starfive-jh7110-gen.c
@@ -368,7 +368,7 @@ static struct platform_driver clk_starfive_jh7110_driver = {
                .of_match_table = clk_starfive_jh7110_match,
        },
 };
-builtin_platform_driver_probe(clk_starfive_jh7110_driver, 
+builtin_platform_driver_probe(clk_starfive_jh7110_driver,
                        clk_starfive_jh7110_probe);
 
 MODULE_AUTHOR("Xingyu Wu <xingyu.wu@starfivetech.com>");

diff --git a/drivers/clk/starfive/clk-starfive-jh7110-stg.c b/drivers/clk/starfive/clk-starfive-jh7110-stg.c
index c8a47bd..f9de3c1 100755 (executable)
--- a/drivers/clk/starfive/clk-starfive-jh7110-stg.c
+++ b/drivers/clk/starfive/clk-starfive-jh7110-stg.c
@@ -15,68 +15,68 @@
 
 static const struct jh7110_clk_data jh7110_clk_stg_data[] __initconst = {
        //hifi4
-       JH7110_GATE(JH7110_HIFI4_CLK_CORE, "u0_hifi4_clk_core", 
+       JH7110_GATE(JH7110_HIFI4_CLK_CORE, "u0_hifi4_clk_core",
                        0, JH7110_HIFI4_CORE),
        //usb
-       JH7110_GATE(JH7110_USB0_CLK_USB_APB, "u0_cdn_usb_clk_usb_apb", 
+       JH7110_GATE(JH7110_USB0_CLK_USB_APB, "u0_cdn_usb_clk_usb_apb",
                        0, JH7110_STG_APB),
-       JH7110_GATE(JH7110_USB0_CLK_UTMI_APB, "u0_cdn_usb_clk_utmi_apb", 
+       JH7110_GATE(JH7110_USB0_CLK_UTMI_APB, "u0_cdn_usb_clk_utmi_apb",
                        0, JH7110_STG_APB),
-       JH7110_GATE(JH7110_USB0_CLK_AXI, "u0_cdn_usb_clk_axi", 
+       JH7110_GATE(JH7110_USB0_CLK_AXI, "u0_cdn_usb_clk_axi",
                        0, JH7110_STG_AXIAHB),
-       JH7110_GDIV(JH7110_USB0_CLK_LPM, "u0_cdn_usb_clk_lpm", 
+       JH7110_GDIV(JH7110_USB0_CLK_LPM, "u0_cdn_usb_clk_lpm",
                        0, 2, JH7110_OSC),
-       JH7110_GDIV(JH7110_USB0_CLK_STB, "u0_cdn_usb_clk_stb", 
+       JH7110_GDIV(JH7110_USB0_CLK_STB, "u0_cdn_usb_clk_stb",
                        0, 4, JH7110_OSC),
-       JH7110_GATE(JH7110_USB0_CLK_APP_125, "u0_cdn_usb_clk_app_125", 
+       JH7110_GATE(JH7110_USB0_CLK_APP_125, "u0_cdn_usb_clk_app_125",
                        0, JH7110_USB_125M),
        JH7110__DIV(JH7110_USB0_REFCLK, "u0_cdn_usb_refclk", 2, JH7110_OSC),
        //pci-e
-       JH7110_GATE(JH7110_PCIE0_CLK_AXI_MST0, "u0_plda_pcie_clk_axi_mst0", 
+       JH7110_GATE(JH7110_PCIE0_CLK_AXI_MST0, "u0_plda_pcie_clk_axi_mst0",
                        0, JH7110_STG_AXIAHB),
-       JH7110_GATE(JH7110_PCIE0_CLK_APB, "u0_plda_pcie_clk_apb", 
+       JH7110_GATE(JH7110_PCIE0_CLK_APB, "u0_plda_pcie_clk_apb",
                        0, JH7110_STG_APB),
-       JH7110_GATE(JH7110_PCIE0_CLK_TL, "u0_plda_pcie_clk_tl", 
+       JH7110_GATE(JH7110_PCIE0_CLK_TL, "u0_plda_pcie_clk_tl",
                        0, JH7110_STG_AXIAHB),
-       JH7110_GATE(JH7110_PCIE1_CLK_AXI_MST0, "u1_plda_pcie_clk_axi_mst0", 
+       JH7110_GATE(JH7110_PCIE1_CLK_AXI_MST0, "u1_plda_pcie_clk_axi_mst0",
                        0, JH7110_STG_AXIAHB),
-       JH7110_GATE(JH7110_PCIE1_CLK_APB, "u1_plda_pcie_clk_apb", 
+       JH7110_GATE(JH7110_PCIE1_CLK_APB, "u1_plda_pcie_clk_apb",
                        0, JH7110_STG_APB),
-       JH7110_GATE(JH7110_PCIE1_CLK_TL, "u1_plda_pcie_clk_tl", 
+       JH7110_GATE(JH7110_PCIE1_CLK_TL, "u1_plda_pcie_clk_tl",
                        0, JH7110_STG_AXIAHB),
-       JH7110_GATE(JH7110_PCIE01_SLV_DEC_MAINCLK, "u0_pcie01_slv_dec_mainclk", 
+       JH7110_GATE(JH7110_PCIE01_SLV_DEC_MAINCLK, "u0_pcie01_slv_dec_mainclk",
                        0, JH7110_STG_AXIAHB),
        //security
-       JH7110_GATE(JH7110_SEC_HCLK, "u0_sec_top_hclk", 
+       JH7110_GATE(JH7110_SEC_HCLK, "u0_sec_top_hclk",
                        0, JH7110_STG_AXIAHB),
-       JH7110_GATE(JH7110_SEC_MISCAHB_CLK, "u0_sec_top_miscahb_clk", 
+       JH7110_GATE(JH7110_SEC_MISCAHB_CLK, "u0_sec_top_miscahb_clk",
                        0, JH7110_STG_AXIAHB),
        //stg mtrx
-       JH7110_GATE(JH7110_STG_MTRX_GRP0_CLK_MAIN, "u0_stg_mtrx_grp0_clk_main", 
+       JH7110_GATE(JH7110_STG_MTRX_GRP0_CLK_MAIN, "u0_stg_mtrx_grp0_clk_main",
                        0, JH7110_CPU_BUS),
-       JH7110_GATE(JH7110_STG_MTRX_GRP0_CLK_BUS, "u0_stg_mtrx_grp0_clk_bus", 
+       JH7110_GATE(JH7110_STG_MTRX_GRP0_CLK_BUS, "u0_stg_mtrx_grp0_clk_bus",
                        0, JH7110_NOCSTG_BUS),
-       JH7110_GATE(JH7110_STG_MTRX_GRP0_CLK_STG, "u0_stg_mtrx_grp0_clk_stg", 
+       JH7110_GATE(JH7110_STG_MTRX_GRP0_CLK_STG, "u0_stg_mtrx_grp0_clk_stg",
                        0, JH7110_STG_AXIAHB),
-       JH7110_GATE(JH7110_STG_MTRX_GRP1_CLK_MAIN, "u0_stg_mtrx_grp1_clk_main", 
+       JH7110_GATE(JH7110_STG_MTRX_GRP1_CLK_MAIN, "u0_stg_mtrx_grp1_clk_main",
                        0, JH7110_CPU_BUS),
-       JH7110_GATE(JH7110_STG_MTRX_GRP1_CLK_BUS, "u0_stg_mtrx_grp1_clk_bus", 
+       JH7110_GATE(JH7110_STG_MTRX_GRP1_CLK_BUS, "u0_stg_mtrx_grp1_clk_bus",
                        0, JH7110_NOCSTG_BUS),
-       JH7110_GATE(JH7110_STG_MTRX_GRP1_CLK_STG, "u0_stg_mtrx_grp1_clk_stg", 
+       JH7110_GATE(JH7110_STG_MTRX_GRP1_CLK_STG, "u0_stg_mtrx_grp1_clk_stg",
                        0, JH7110_STG_AXIAHB),
-       JH7110_GATE(JH7110_STG_MTRX_GRP1_CLK_HIFI, "u0_stg_mtrx_grp1_clk_hifi", 
+       JH7110_GATE(JH7110_STG_MTRX_GRP1_CLK_HIFI, "u0_stg_mtrx_grp1_clk_hifi",
                        0, JH7110_HIFI4_AXI),
        //e24_rvpi
-       JH7110_GDIV(JH7110_E2_RTC_CLK, "u0_e2_sft7110_rtc_clk", 
+       JH7110_GDIV(JH7110_E2_RTC_CLK, "u0_e2_sft7110_rtc_clk",
                        0, 24, JH7110_OSC),
-       JH7110_GATE(JH7110_E2_CLK_CORE, "u0_e2_sft7110_clk_core", 
+       JH7110_GATE(JH7110_E2_CLK_CORE, "u0_e2_sft7110_clk_core",
                        0, JH7110_STG_AXIAHB),
-       JH7110_GATE(JH7110_E2_CLK_DBG, "u0_e2_sft7110_clk_dbg", 
+       JH7110_GATE(JH7110_E2_CLK_DBG, "u0_e2_sft7110_clk_dbg",
                        0, JH7110_STG_AXIAHB),
        //dw_sgdma1p
-       JH7110_GATE(JH7110_DMA1P_CLK_AXI, "u0_dw_dma1p_8ch_56hs_clk_axi", 
+       JH7110_GATE(JH7110_DMA1P_CLK_AXI, "u0_dw_dma1p_8ch_56hs_clk_axi",
                        0, JH7110_STG_AXIAHB),
-       JH7110_GATE(JH7110_DMA1P_CLK_AHB, "u0_dw_dma1p_8ch_56hs_clk_ahb", 
+       JH7110_GATE(JH7110_DMA1P_CLK_AHB, "u0_dw_dma1p_8ch_56hs_clk_ahb",
                        0, JH7110_STG_AXIAHB),
 };
 
@@ -90,37 +90,37 @@ int __init clk_starfive_jh7110_stg_init(struct platform_device *pdev,
        if (IS_ERR(priv->stg_base))
                return PTR_ERR(priv->stg_base);
 
-       priv->pll[PLL_OF(JH7110_PCIE0_CLK_AXI_SLV0)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
-                       "u0_plda_pcie_clk_axi_slv0", 
+       priv->pll[PLL_OF(JH7110_PCIE0_CLK_AXI_SLV0)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
+                       "u0_plda_pcie_clk_axi_slv0",
                        "u0_plda_pcie_clk_axi_mst0", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_PCIE0_CLK_AXI_SLV)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
-                       "u0_plda_pcie_clk_axi_slv", 
+       priv->pll[PLL_OF(JH7110_PCIE0_CLK_AXI_SLV)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
+                       "u0_plda_pcie_clk_axi_slv",
                        "u0_plda_pcie_clk_axi_mst0", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_PCIE0_CLK_OSC)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_PCIE0_CLK_OSC)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u0_plda_pcie_clk_osc", "osc", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_PCIE1_CLK_AXI_SLV0)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
-                       "u1_plda_pcie_clk_axi_slv0", 
+       priv->pll[PLL_OF(JH7110_PCIE1_CLK_AXI_SLV0)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
+                       "u1_plda_pcie_clk_axi_slv0",
                        "u1_plda_pcie_clk_axi_mst0", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_PCIE1_CLK_AXI_SLV)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
-                       "u1_plda_pcie_clk_axi_slv", 
+       priv->pll[PLL_OF(JH7110_PCIE1_CLK_AXI_SLV)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
+                       "u1_plda_pcie_clk_axi_slv",
                        "u1_plda_pcie_clk_axi_mst0", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_PCIE1_CLK_OSC)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_PCIE1_CLK_OSC)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u1_plda_pcie_clk_osc", "osc", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_E2_IRQ_SYNC_CLK_CORE)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
-                       "u0_e2_sft7110_irq_sync_clk_core", 
+       priv->pll[PLL_OF(JH7110_E2_IRQ_SYNC_CLK_CORE)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
+                       "u0_e2_sft7110_irq_sync_clk_core",
                        "stg_axiahb", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_STG_CRG_PCLK)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_STG_CRG_PCLK)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u0_stg_crg_pclk", "stg_apb", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_STG_SYSCON_PCLK)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_STG_SYSCON_PCLK)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u0_stg_syscon_pclk", "stg_apb", 0, 1, 1);
 
        for (idx = JH7110_CLK_SYS_REG_END; idx < JH7110_CLK_STG_REG_END; idx++) {

diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
index 464de15..fb97283 100755 (executable)
--- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c
+++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
@@ -35,7 +35,7 @@ static const struct jh7110_clk_data jh7110_clk_sys_data[] __initconst = {
        JH7110__DIV(JH7110_STG_AXIAHB, "stg_axiahb", 2, JH7110_AXI_CFG0),
        JH7110_GATE(JH7110_AHB0, "ahb0", 0, JH7110_STG_AXIAHB),
        JH7110_GATE(JH7110_AHB1, "ahb1", 0, JH7110_STG_AXIAHB),
-       JH7110__DIV(JH7110_APB_BUS_FUNC, "apb_bus_func", 
+       JH7110__DIV(JH7110_APB_BUS_FUNC, "apb_bus_func",
                        8, JH7110_STG_AXIAHB),
        JH7110_GATE(JH7110_APB0, "apb0", 0, JH7110_APB_BUS),
        JH7110__DIV(JH7110_PLL0_DIV2, "pll0_div2", 2, JH7110_PLL0_OUT),
@@ -55,38 +55,38 @@ static const struct jh7110_clk_data jh7110_clk_sys_data[] __initconst = {
        JH7110_GDIV(JH7110_GCLK1, "gclk1", 0, 62, JH7110_PLL1_DIV2),
        JH7110_GDIV(JH7110_GCLK2, "gclk2", 0, 62, JH7110_PLL2_DIV2),
        /*u0_u7mc_sft7110*/
-       JH7110_GATE(JH7110_U7_CORE_CLK, "u0_u7mc_sft7110_core_clk", 
+       JH7110_GATE(JH7110_U7_CORE_CLK, "u0_u7mc_sft7110_core_clk",
                        0, JH7110_CPU_CORE),
-       JH7110_GATE(JH7110_U7_CORE_CLK1, "u0_u7mc_sft7110_core_clk1", 
+       JH7110_GATE(JH7110_U7_CORE_CLK1, "u0_u7mc_sft7110_core_clk1",
                        0, JH7110_CPU_CORE),
-       JH7110_GATE(JH7110_U7_CORE_CLK2, "u0_u7mc_sft7110_core_clk2", 
+       JH7110_GATE(JH7110_U7_CORE_CLK2, "u0_u7mc_sft7110_core_clk2",
                        0, JH7110_CPU_CORE),
-       JH7110_GATE(JH7110_U7_CORE_CLK3, "u0_u7mc_sft7110_core_clk3", 
+       JH7110_GATE(JH7110_U7_CORE_CLK3, "u0_u7mc_sft7110_core_clk3",
                        0, JH7110_CPU_CORE),
-       JH7110_GATE(JH7110_U7_CORE_CLK4, "u0_u7mc_sft7110_core_clk4", 
+       JH7110_GATE(JH7110_U7_CORE_CLK4, "u0_u7mc_sft7110_core_clk4",
                        0, JH7110_CPU_CORE),
-       JH7110_GATE(JH7110_U7_DEBUG_CLK, "u0_u7mc_sft7110_debug_clk", 
+       JH7110_GATE(JH7110_U7_DEBUG_CLK, "u0_u7mc_sft7110_debug_clk",
                        0, JH7110_CPU_BUS),
-       JH7110__DIV(JH7110_U7_RTC_TOGGLE, "u0_u7mc_sft7110_rtc_toggle", 
+       JH7110__DIV(JH7110_U7_RTC_TOGGLE, "u0_u7mc_sft7110_rtc_toggle",
                        6, JH7110_OSC),
-       JH7110_GATE(JH7110_U7_TRACE_CLK0, "u0_u7mc_sft7110_trace_clk0", 
+       JH7110_GATE(JH7110_U7_TRACE_CLK0, "u0_u7mc_sft7110_trace_clk0",
                        0, JH7110_CPU_CORE),
-       JH7110_GATE(JH7110_U7_TRACE_CLK1, "u0_u7mc_sft7110_trace_clk1", 
+       JH7110_GATE(JH7110_U7_TRACE_CLK1, "u0_u7mc_sft7110_trace_clk1",
                        0, JH7110_CPU_CORE),
-       JH7110_GATE(JH7110_U7_TRACE_CLK2, "u0_u7mc_sft7110_trace_clk2", 
+       JH7110_GATE(JH7110_U7_TRACE_CLK2, "u0_u7mc_sft7110_trace_clk2",
                        0, JH7110_CPU_CORE),
-       JH7110_GATE(JH7110_U7_TRACE_CLK3, "u0_u7mc_sft7110_trace_clk3", 
+       JH7110_GATE(JH7110_U7_TRACE_CLK3, "u0_u7mc_sft7110_trace_clk3",
                        0, JH7110_CPU_CORE),
-       JH7110_GATE(JH7110_U7_TRACE_CLK4, "u0_u7mc_sft7110_trace_clk4", 
+       JH7110_GATE(JH7110_U7_TRACE_CLK4, "u0_u7mc_sft7110_trace_clk4",
                        0, JH7110_CPU_CORE),
-       JH7110_GATE(JH7110_U7_TRACE_COM_CLK, "u0_u7mc_sft7110_trace_com_clk", 
+       JH7110_GATE(JH7110_U7_TRACE_COM_CLK, "u0_u7mc_sft7110_trace_com_clk",
                        0, JH7110_CPU_BUS),
        //NOC
-       JH7110_GATE(JH7110_NOC_BUS_CLK_CPU_AXI, 
-                       "u0_sft7110_noc_bus_clk_cpu_axi", 
+       JH7110_GATE(JH7110_NOC_BUS_CLK_CPU_AXI,
+                       "u0_sft7110_noc_bus_clk_cpu_axi",
                        0, JH7110_CPU_BUS),
-       JH7110_GATE(JH7110_NOC_BUS_CLK_AXICFG0_AXI, 
-                       "u0_sft7110_noc_bus_clk_axicfg0_axi", 
+       JH7110_GATE(JH7110_NOC_BUS_CLK_AXICFG0_AXI,
+                       "u0_sft7110_noc_bus_clk_axicfg0_axi",
                        0, JH7110_AXI_CFG0),
        //DDRC
        JH7110__DIV(JH7110_OSC_DIV2, "osc_div2", 2, JH7110_OSC),
@@ -97,279 +97,279 @@ static const struct jh7110_clk_data jh7110_clk_sys_data[] __initconst = {
                        JH7110_PLL1_DIV2,
                        JH7110_PLL1_DIV4,
                        JH7110_PLL1_DIV8),
-       JH7110_GATE(JH7110_DDR_CLK_AXI, "u0_ddr_sft7110_clk_axi", 
+       JH7110_GATE(JH7110_DDR_CLK_AXI, "u0_ddr_sft7110_clk_axi",
                        0, JH7110_DDR_BUS),
        //GPU
        JH7110__DIV(JH7110_GPU_CORE, "gpu_core", 7, JH7110_GPU_ROOT),
-       JH7110_GATE(JH7110_GPU_CORE_CLK, "u0_img_gpu_core_clk", 
+       JH7110_GATE(JH7110_GPU_CORE_CLK, "u0_img_gpu_core_clk",
                        0, JH7110_GPU_CORE),
-       JH7110_GATE(JH7110_GPU_SYS_CLK, "u0_img_gpu_sys_clk", 
+       JH7110_GATE(JH7110_GPU_SYS_CLK, "u0_img_gpu_sys_clk",
                        0, JH7110_AXI_CFG1),
-       JH7110_GATE(JH7110_GPU_CLK_APB, "u0_img_gpu_clk_apb", 
+       JH7110_GATE(JH7110_GPU_CLK_APB, "u0_img_gpu_clk_apb",
                        0, JH7110_APB12),
-       JH7110_GDIV(JH7110_GPU_RTC_TOGGLE, "u0_img_gpu_rtc_toggle", 
+       JH7110_GDIV(JH7110_GPU_RTC_TOGGLE, "u0_img_gpu_rtc_toggle",
                        0, 12, JH7110_OSC),
-       JH7110_GATE(JH7110_NOC_BUS_CLK_GPU_AXI, 
-                       "u0_sft7110_noc_bus_clk_gpu_axi", 
+       JH7110_GATE(JH7110_NOC_BUS_CLK_GPU_AXI,
+                       "u0_sft7110_noc_bus_clk_gpu_axi",
                        0, JH7110_GPU_CORE),
        //ISP
-       JH7110_GATE(JH7110_ISP_TOP_CLK_ISPCORE_2X, 
-                       "u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x", 
+       JH7110_GATE(JH7110_ISP_TOP_CLK_ISPCORE_2X,
+                       "u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x",
                        0, JH7110_ISP_2X),
-       JH7110_GATE(JH7110_ISP_TOP_CLK_ISP_AXI, 
-                       "u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi", 
+       JH7110_GATE(JH7110_ISP_TOP_CLK_ISP_AXI,
+                       "u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi",
                        0, JH7110_ISP_AXI),
-       JH7110_GATE(JH7110_NOC_BUS_CLK_ISP_AXI, 
-                       "u0_sft7110_noc_bus_clk_isp_axi", 
+       JH7110_GATE(JH7110_NOC_BUS_CLK_ISP_AXI,
+                       "u0_sft7110_noc_bus_clk_isp_axi",
                        0, JH7110_ISP_AXI),
        //HIFI4
        JH7110__DIV(JH7110_HIFI4_CORE, "hifi4_core", 15, JH7110_BUS_ROOT),
        JH7110__DIV(JH7110_HIFI4_AXI, "hifi4_axi", 2, JH7110_HIFI4_CORE),
        //AXICFG1_DEC
-       JH7110_GATE(JH7110_AXI_CFG1_DEC_CLK_MAIN, "u0_axi_cfg1_dec_clk_main", 
+       JH7110_GATE(JH7110_AXI_CFG1_DEC_CLK_MAIN, "u0_axi_cfg1_dec_clk_main",
                        0, JH7110_AXI_CFG1),
-       JH7110_GATE(JH7110_AXI_CFG1_DEC_CLK_AHB, "u0_axi_cfg1_dec_clk_ahb", 
+       JH7110_GATE(JH7110_AXI_CFG1_DEC_CLK_AHB, "u0_axi_cfg1_dec_clk_ahb",
                        0, JH7110_AHB0),
        //VOUT
-       JH7110_GATE(JH7110_VOUT_SRC, 
-                       "u0_dom_vout_top_clk_dom_vout_top_clk_vout_src", 
+       JH7110_GATE(JH7110_VOUT_SRC,
+                       "u0_dom_vout_top_clk_dom_vout_top_clk_vout_src",
                        0, JH7110_VOUT_ROOT),
        JH7110__DIV(JH7110_VOUT_AXI, "vout_axi", 7, JH7110_VOUT_ROOT),
-       JH7110_GATE(JH7110_NOC_BUS_CLK_DISP_AXI, 
-                       "u0_sft7110_noc_bus_clk_disp_axi", 
+       JH7110_GATE(JH7110_NOC_BUS_CLK_DISP_AXI,
+                       "u0_sft7110_noc_bus_clk_disp_axi",
                        0, JH7110_VOUT_AXI),
-       JH7110_GATE(JH7110_VOUT_TOP_CLK_VOUT_AHB, 
-                       "u0_dom_vout_top_clk_dom_vout_top_clk_vout_ahb", 
+       JH7110_GATE(JH7110_VOUT_TOP_CLK_VOUT_AHB,
+                       "u0_dom_vout_top_clk_dom_vout_top_clk_vout_ahb",
                        0, JH7110_AHB1),
-       JH7110_GATE(JH7110_VOUT_TOP_CLK_VOUT_AXI, 
-                       "u0_dom_vout_top_clk_dom_vout_top_clk_vout_axi", 
+       JH7110_GATE(JH7110_VOUT_TOP_CLK_VOUT_AXI,
+                       "u0_dom_vout_top_clk_dom_vout_top_clk_vout_axi",
                        0, JH7110_VOUT_AXI),
-       JH7110_GATE(JH7110_VOUT_TOP_CLK_HDMITX0_MCLK, 
-                       "u0_dom_vout_top_clk_dom_vout_top_clk_hdmitx0_mclk", 
+       JH7110_GATE(JH7110_VOUT_TOP_CLK_HDMITX0_MCLK,
+                       "u0_dom_vout_top_clk_dom_vout_top_clk_hdmitx0_mclk",
                        0, JH7110_MCLK),
-       JH7110__DIV(JH7110_VOUT_TOP_CLK_MIPIPHY_REF, 
-                       "u0_dom_vout_top_clk_dom_vout_top_clk_mipiphy_ref", 
+       JH7110__DIV(JH7110_VOUT_TOP_CLK_MIPIPHY_REF,
+                       "u0_dom_vout_top_clk_dom_vout_top_clk_mipiphy_ref",
                        2, JH7110_OSC),
        //JPEGC
        JH7110__DIV(JH7110_JPEGC_AXI, "jpegc_axi", 16, JH7110_VENC_ROOT),
-       JH7110_GATE(JH7110_CODAJ12_CLK_AXI, "u0_CODAJ12_clk_axi", 
+       JH7110_GATE(JH7110_CODAJ12_CLK_AXI, "u0_CODAJ12_clk_axi",
                        0, JH7110_JPEGC_AXI),
-       JH7110_GDIV(JH7110_CODAJ12_CLK_CORE, "u0_CODAJ12_clk_core", 
+       JH7110_GDIV(JH7110_CODAJ12_CLK_CORE, "u0_CODAJ12_clk_core",
                        0, 16, JH7110_VENC_ROOT),
-       JH7110_GATE(JH7110_CODAJ12_CLK_APB, "u0_CODAJ12_clk_apb", 
+       JH7110_GATE(JH7110_CODAJ12_CLK_APB, "u0_CODAJ12_clk_apb",
                        0, JH7110_APB12),
        //VDEC
        JH7110__DIV(JH7110_VDEC_AXI, "vdec_axi", 7, JH7110_BUS_ROOT),
-       JH7110_GATE(JH7110_WAVE511_CLK_AXI, "u0_WAVE511_clk_axi", 
+       JH7110_GATE(JH7110_WAVE511_CLK_AXI, "u0_WAVE511_clk_axi",
                        0, JH7110_VDEC_AXI),
-       JH7110_GDIV(JH7110_WAVE511_CLK_BPU, "u0_WAVE511_clk_bpu", 
+       JH7110_GDIV(JH7110_WAVE511_CLK_BPU, "u0_WAVE511_clk_bpu",
                        0, 7, JH7110_BUS_ROOT),
-       JH7110_GDIV(JH7110_WAVE511_CLK_VCE, "u0_WAVE511_clk_vce", 
+       JH7110_GDIV(JH7110_WAVE511_CLK_VCE, "u0_WAVE511_clk_vce",
                        0, 7, JH7110_VDEC_ROOT),
-       JH7110_GATE(JH7110_WAVE511_CLK_APB, "u0_WAVE511_clk_apb", 
+       JH7110_GATE(JH7110_WAVE511_CLK_APB, "u0_WAVE511_clk_apb",
                        0, JH7110_APB12),
-       JH7110_GATE(JH7110_VDEC_JPG_ARB_JPGCLK, "u0_vdec_jpg_arb_jpgclk", 
+       JH7110_GATE(JH7110_VDEC_JPG_ARB_JPGCLK, "u0_vdec_jpg_arb_jpgclk",
                        0, JH7110_JPEGC_AXI),
-       JH7110_GATE(JH7110_VDEC_JPG_ARB_MAINCLK, "u0_vdec_jpg_arb_mainclk", 
+       JH7110_GATE(JH7110_VDEC_JPG_ARB_MAINCLK, "u0_vdec_jpg_arb_mainclk",
                        0, JH7110_VDEC_AXI),
-       JH7110_GATE(JH7110_NOC_BUS_CLK_VDEC_AXI, 
-                       "u0_sft7110_noc_bus_clk_vdec_axi", 
+       JH7110_GATE(JH7110_NOC_BUS_CLK_VDEC_AXI,
+                       "u0_sft7110_noc_bus_clk_vdec_axi",
                        0, JH7110_VDEC_AXI),
        //VENC
        JH7110__DIV(JH7110_VENC_AXI, "venc_axi", 15, JH7110_VENC_ROOT),
-       JH7110_GATE(JH7110_WAVE420L_CLK_AXI, "u0_wave420l_clk_axi", 
+       JH7110_GATE(JH7110_WAVE420L_CLK_AXI, "u0_wave420l_clk_axi",
                        0, JH7110_VENC_AXI),
-       JH7110_GDIV(JH7110_WAVE420L_CLK_BPU, "u0_wave420l_clk_bpu", 
+       JH7110_GDIV(JH7110_WAVE420L_CLK_BPU, "u0_wave420l_clk_bpu",
                        0, 15, JH7110_VENC_ROOT),
-       JH7110_GDIV(JH7110_WAVE420L_CLK_VCE, "u0_wave420l_clk_vce", 
+       JH7110_GDIV(JH7110_WAVE420L_CLK_VCE, "u0_wave420l_clk_vce",
                        0, 15, JH7110_VENC_ROOT),
-       JH7110_GATE(JH7110_WAVE420L_CLK_APB, "u0_wave420l_clk_apb", 
+       JH7110_GATE(JH7110_WAVE420L_CLK_APB, "u0_wave420l_clk_apb",
                        0, JH7110_APB12),
-       JH7110_GATE(JH7110_NOC_BUS_CLK_VENC_AXI, 
-                       "u0_sft7110_noc_bus_clk_venc_axi", 
+       JH7110_GATE(JH7110_NOC_BUS_CLK_VENC_AXI,
+                       "u0_sft7110_noc_bus_clk_venc_axi",
                        0, JH7110_VENC_AXI),
        //INTMEM
-       JH7110_GATE(JH7110_AXI_CFG0_DEC_CLK_MAIN_DIV, 
-                       "u0_axi_cfg0_dec_clk_main_div", 
+       JH7110_GATE(JH7110_AXI_CFG0_DEC_CLK_MAIN_DIV,
+                       "u0_axi_cfg0_dec_clk_main_div",
                        0, JH7110_AHB1),
-       JH7110_GATE(JH7110_AXI_CFG0_DEC_CLK_MAIN, "u0_axi_cfg0_dec_clk_main", 
+       JH7110_GATE(JH7110_AXI_CFG0_DEC_CLK_MAIN, "u0_axi_cfg0_dec_clk_main",
                        0, JH7110_AXI_CFG0),
-       JH7110_GATE(JH7110_AXI_CFG0_DEC_CLK_HIFI4, "u0_axi_cfg0_dec_clk_hifi4", 
+       JH7110_GATE(JH7110_AXI_CFG0_DEC_CLK_HIFI4, "u0_axi_cfg0_dec_clk_hifi4",
                        0, JH7110_HIFI4_AXI),
-       JH7110_GATE(JH7110_AXIMEM2_128B_CLK_AXI, "u2_aximem_128b_clk_axi", 
+       JH7110_GATE(JH7110_AXIMEM2_128B_CLK_AXI, "u2_aximem_128b_clk_axi",
                        0, JH7110_AXI_CFG0),
        //QSPI
-       JH7110_GATE(JH7110_QSPI_CLK_AHB, "u0_cdns_qspi_clk_ahb", 
+       JH7110_GATE(JH7110_QSPI_CLK_AHB, "u0_cdns_qspi_clk_ahb",
                        0, JH7110_AHB1),
-       JH7110_GATE(JH7110_QSPI_CLK_APB, "u0_cdns_qspi_clk_apb", 
+       JH7110_GATE(JH7110_QSPI_CLK_APB, "u0_cdns_qspi_clk_apb",
                        0, JH7110_APB12),
-       JH7110__DIV(JH7110_QSPI_REF_SRC, "u0_cdns_qspi_ref_src", 
+       JH7110__DIV(JH7110_QSPI_REF_SRC, "u0_cdns_qspi_ref_src",
                        16, JH7110_GMACUSB_ROOT),
        JH7110_GMUX(JH7110_QSPI_CLK_REF, "u0_cdns_qspi_clk_ref", 0, 2,
                        JH7110_OSC,
                        JH7110_QSPI_REF_SRC),
        //SDIO
-       JH7110_GATE(JH7110_SDIO0_CLK_AHB, "u0_dw_sdio_clk_ahb", 
+       JH7110_GATE(JH7110_SDIO0_CLK_AHB, "u0_dw_sdio_clk_ahb",
                        0, JH7110_AHB0),
-       JH7110_GATE(JH7110_SDIO1_CLK_AHB, "u1_dw_sdio_clk_ahb", 
+       JH7110_GATE(JH7110_SDIO1_CLK_AHB, "u1_dw_sdio_clk_ahb",
                        0, JH7110_AHB0),
-       JH7110_GDIV(JH7110_SDIO0_CLK_SDCARD, "u0_dw_sdio_clk_sdcard", 
+       JH7110_GDIV(JH7110_SDIO0_CLK_SDCARD, "u0_dw_sdio_clk_sdcard",
                        0, 15, JH7110_AXI_CFG0),
-       JH7110_GDIV(JH7110_SDIO1_CLK_SDCARD, "u1_dw_sdio_clk_sdcard", 
+       JH7110_GDIV(JH7110_SDIO1_CLK_SDCARD, "u1_dw_sdio_clk_sdcard",
                        0, 15, JH7110_AXI_CFG0),
        //STG
        JH7110__DIV(JH7110_USB_125M, "usb_125m", 15, JH7110_GMACUSB_ROOT),
-       JH7110_GATE(JH7110_NOC_BUS_CLK_STG_AXI, 
-                       "u0_sft7110_noc_bus_clk_stg_axi", 
+       JH7110_GATE(JH7110_NOC_BUS_CLK_STG_AXI,
+                       "u0_sft7110_noc_bus_clk_stg_axi",
                        0, JH7110_NOCSTG_BUS),
        //GMAC1
-       JH7110_GATE(JH7110_GMAC5_CLK_AHB, "u1_dw_gmac5_axi64_clk_ahb", 
+       JH7110_GATE(JH7110_GMAC5_CLK_AHB, "u1_dw_gmac5_axi64_clk_ahb",
                        0, JH7110_AHB0),
-       JH7110_GATE(JH7110_GMAC5_CLK_AXI, "u1_dw_gmac5_axi64_clk_axi", 
+       JH7110_GATE(JH7110_GMAC5_CLK_AXI, "u1_dw_gmac5_axi64_clk_axi",
                        0, JH7110_STG_AXIAHB),
        JH7110__DIV(JH7110_GMAC_SRC, "gmac_src", 7, JH7110_GMACUSB_ROOT),
-       JH7110__DIV(JH7110_GMAC1_GTXCLK, "gmac1_gtxclk", 
+       JH7110__DIV(JH7110_GMAC1_GTXCLK, "gmac1_gtxclk",
                        15, JH7110_GMACUSB_ROOT),
-       JH7110__DIV(JH7110_GMAC1_RMII_RTX, "gmac1_rmii_rtx", 
+       JH7110__DIV(JH7110_GMAC1_RMII_RTX, "gmac1_rmii_rtx",
                        30, JH7110_GMAC1_RMII_REFIN),
-       JH7110_GDIV(JH7110_GMAC5_CLK_PTP, "u1_dw_gmac5_axi64_clk_ptp", 
+       JH7110_GDIV(JH7110_GMAC5_CLK_PTP, "u1_dw_gmac5_axi64_clk_ptp",
                        0, 31, JH7110_GMAC_SRC),
        JH7110__MUX(JH7110_GMAC5_CLK_RX, "u1_dw_gmac5_axi64_clk_rx", 2,
                        JH7110_GMAC1_RGMII_RXIN,
                        JH7110_GMAC1_RMII_RTX),
-       JH7110__INV(JH7110_GMAC5_CLK_RX_INV, "u1_dw_gmac5_axi64_clk_rx_inv", 
+       JH7110__INV(JH7110_GMAC5_CLK_RX_INV, "u1_dw_gmac5_axi64_clk_rx_inv",
                        JH7110_GMAC5_CLK_RX),
        JH7110_GMUX(JH7110_GMAC5_CLK_TX, "u1_dw_gmac5_axi64_clk_tx", 0, 2,
                        JH7110_GMAC1_GTXCLK,
                        JH7110_GMAC1_RMII_RTX),
-       JH7110__INV(JH7110_GMAC5_CLK_TX_INV, "u1_dw_gmac5_axi64_clk_tx_inv", 
+       JH7110__INV(JH7110_GMAC5_CLK_TX_INV, "u1_dw_gmac5_axi64_clk_tx_inv",
                        JH7110_GMAC5_CLK_TX),
-       JH7110_GATE(JH7110_GMAC1_GTXC, "gmac1_gtxc", 
+       JH7110_GATE(JH7110_GMAC1_GTXC, "gmac1_gtxc",
                        0, JH7110_GMAC1_GTXCLK),
        //GMAC0
-       JH7110_GDIV(JH7110_GMAC0_GTXCLK, "gmac0_gtxclk", 
+       JH7110_GDIV(JH7110_GMAC0_GTXCLK, "gmac0_gtxclk",
                        0, 15, JH7110_GMACUSB_ROOT),
-       JH7110_GDIV(JH7110_GMAC0_PTP, "gmac0_ptp", 
+       JH7110_GDIV(JH7110_GMAC0_PTP, "gmac0_ptp",
                        0, 31, JH7110_GMAC_SRC),
-       JH7110_GDIV(JH7110_GMAC_PHY, "gmac_phy", 
+       JH7110_GDIV(JH7110_GMAC_PHY, "gmac_phy",
                        0, 31, JH7110_GMAC_SRC),
-       JH7110_GATE(JH7110_GMAC0_GTXC, "gmac0_gtxc", 
+       JH7110_GATE(JH7110_GMAC0_GTXC, "gmac0_gtxc",
                        0, JH7110_GMAC0_GTXCLK),
        //SYS MISC
-       JH7110_GATE(JH7110_SYS_IOMUX_PCLK, "u0_sys_iomux_pclk", 
+       JH7110_GATE(JH7110_SYS_IOMUX_PCLK, "u0_sys_iomux_pclk",
                        0, JH7110_APB12),
-       JH7110_GATE(JH7110_MAILBOX_CLK_APB, "u0_mailbox_clk_apb", 
+       JH7110_GATE(JH7110_MAILBOX_CLK_APB, "u0_mailbox_clk_apb",
                        0, JH7110_APB12),
-       JH7110_GATE(JH7110_INT_CTRL_CLK_APB, "u0_int_ctrl_clk_apb", 
+       JH7110_GATE(JH7110_INT_CTRL_CLK_APB, "u0_int_ctrl_clk_apb",
                        0, JH7110_APB12),
        //CAN
-       JH7110_GATE(JH7110_CAN0_CTRL_CLK_APB, "u0_can_ctrl_clk_apb", 
+       JH7110_GATE(JH7110_CAN0_CTRL_CLK_APB, "u0_can_ctrl_clk_apb",
                        0, JH7110_APB12),
-       JH7110_GDIV(JH7110_CAN0_CTRL_CLK_TIMER, "u0_can_ctrl_clk_timer", 
+       JH7110_GDIV(JH7110_CAN0_CTRL_CLK_TIMER, "u0_can_ctrl_clk_timer",
                        0, 24, JH7110_OSC),
-       JH7110_GDIV(JH7110_CAN0_CTRL_CLK_CAN, "u0_can_ctrl_clk_can", 
+       JH7110_GDIV(JH7110_CAN0_CTRL_CLK_CAN, "u0_can_ctrl_clk_can",
                        0, 63, JH7110_PERH_ROOT),
-       JH7110_GATE(JH7110_CAN1_CTRL_CLK_APB, "u1_can_ctrl_clk_apb", 
+       JH7110_GATE(JH7110_CAN1_CTRL_CLK_APB, "u1_can_ctrl_clk_apb",
                        0, JH7110_APB12),
-       JH7110_GDIV(JH7110_CAN1_CTRL_CLK_TIMER, "u1_can_ctrl_clk_timer", 
+       JH7110_GDIV(JH7110_CAN1_CTRL_CLK_TIMER, "u1_can_ctrl_clk_timer",
                        0, 24, JH7110_OSC),
-       JH7110_GDIV(JH7110_CAN1_CTRL_CLK_CAN, "u1_can_ctrl_clk_can", 
+       JH7110_GDIV(JH7110_CAN1_CTRL_CLK_CAN, "u1_can_ctrl_clk_can",
                        0, 63, JH7110_PERH_ROOT),
        //PWM
-       JH7110_GATE(JH7110_PWM_CLK_APB, "u0_pwm_8ch_clk_apb", 
+       JH7110_GATE(JH7110_PWM_CLK_APB, "u0_pwm_8ch_clk_apb",
                        0, JH7110_APB12),
        //WDT
-       JH7110_GATE(JH7110_DSKIT_WDT_CLK_APB, "u0_dskit_wdt_clk_apb", 
+       JH7110_GATE(JH7110_DSKIT_WDT_CLK_APB, "u0_dskit_wdt_clk_apb",
                        0, JH7110_APB12),
-       JH7110_GATE(JH7110_DSKIT_WDT_CLK_WDT, "u0_dskit_wdt_clk_wdt", 
+       JH7110_GATE(JH7110_DSKIT_WDT_CLK_WDT, "u0_dskit_wdt_clk_wdt",
                        0, JH7110_OSC),
        //TIMER
-       JH7110_GATE(JH7110_TIMER_CLK_APB, "u0_si5_timer_clk_apb", 
+       JH7110_GATE(JH7110_TIMER_CLK_APB, "u0_si5_timer_clk_apb",
                        0, JH7110_APB12),
-       JH7110_GATE(JH7110_TIMER_CLK_TIMER0, "u0_si5_timer_clk_timer0", 
+       JH7110_GATE(JH7110_TIMER_CLK_TIMER0, "u0_si5_timer_clk_timer0",
                        0, JH7110_OSC),
-       JH7110_GATE(JH7110_TIMER_CLK_TIMER1, "u0_si5_timer_clk_timer1", 
+       JH7110_GATE(JH7110_TIMER_CLK_TIMER1, "u0_si5_timer_clk_timer1",
                        0, JH7110_OSC),
-       JH7110_GATE(JH7110_TIMER_CLK_TIMER2, "u0_si5_timer_clk_timer2", 
+       JH7110_GATE(JH7110_TIMER_CLK_TIMER2, "u0_si5_timer_clk_timer2",
                        0, JH7110_OSC),
-       JH7110_GATE(JH7110_TIMER_CLK_TIMER3, "u0_si5_timer_clk_timer3", 
+       JH7110_GATE(JH7110_TIMER_CLK_TIMER3, "u0_si5_timer_clk_timer3",
                        0, JH7110_OSC),
        //TEMP SENSOR
-       JH7110_GATE(JH7110_TEMP_SENSOR_CLK_APB, "u0_temp_sensor_clk_apb", 
+       JH7110_GATE(JH7110_TEMP_SENSOR_CLK_APB, "u0_temp_sensor_clk_apb",
                        0, JH7110_APB12),
-       JH7110_GDIV(JH7110_TEMP_SENSOR_CLK_TEMP, "u0_temp_sensor_clk_temp", 
+       JH7110_GDIV(JH7110_TEMP_SENSOR_CLK_TEMP, "u0_temp_sensor_clk_temp",
                        0, 24, JH7110_OSC),
        //SPI
-       JH7110_GATE(JH7110_SPI0_CLK_APB, "u0_ssp_spi_clk_apb", 
+       JH7110_GATE(JH7110_SPI0_CLK_APB, "u0_ssp_spi_clk_apb",
                        0, JH7110_APB0),
-       JH7110_GATE(JH7110_SPI1_CLK_APB, "u1_ssp_spi_clk_apb", 
+       JH7110_GATE(JH7110_SPI1_CLK_APB, "u1_ssp_spi_clk_apb",
                        0, JH7110_APB0),
-       JH7110_GATE(JH7110_SPI2_CLK_APB, "u2_ssp_spi_clk_apb", 
+       JH7110_GATE(JH7110_SPI2_CLK_APB, "u2_ssp_spi_clk_apb",
                        0, JH7110_APB0),
-       JH7110_GATE(JH7110_SPI3_CLK_APB, "u3_ssp_spi_clk_apb", 
+       JH7110_GATE(JH7110_SPI3_CLK_APB, "u3_ssp_spi_clk_apb",
                        0, JH7110_APB12),
-       JH7110_GATE(JH7110_SPI4_CLK_APB, "u4_ssp_spi_clk_apb", 
+       JH7110_GATE(JH7110_SPI4_CLK_APB, "u4_ssp_spi_clk_apb",
                        0, JH7110_APB12),
-       JH7110_GATE(JH7110_SPI5_CLK_APB, "u5_ssp_spi_clk_apb", 
+       JH7110_GATE(JH7110_SPI5_CLK_APB, "u5_ssp_spi_clk_apb",
                        0, JH7110_APB12),
-       JH7110_GATE(JH7110_SPI6_CLK_APB, "u6_ssp_spi_clk_apb", 
+       JH7110_GATE(JH7110_SPI6_CLK_APB, "u6_ssp_spi_clk_apb",
                        0, JH7110_APB12),
        //I2C
-       JH7110_GATE(JH7110_I2C0_CLK_APB, "u0_dw_i2c_clk_apb", 
+       JH7110_GATE(JH7110_I2C0_CLK_APB, "u0_dw_i2c_clk_apb",
                        0, JH7110_APB0),
-       JH7110_GATE(JH7110_I2C1_CLK_APB, "u1_dw_i2c_clk_apb", 
+       JH7110_GATE(JH7110_I2C1_CLK_APB, "u1_dw_i2c_clk_apb",
                        0, JH7110_APB0),
-       JH7110_GATE(JH7110_I2C2_CLK_APB, "u2_dw_i2c_clk_apb", 
+       JH7110_GATE(JH7110_I2C2_CLK_APB, "u2_dw_i2c_clk_apb",
                        0, JH7110_APB0),
-       JH7110_GATE(JH7110_I2C3_CLK_APB, "u3_dw_i2c_clk_apb", 
+       JH7110_GATE(JH7110_I2C3_CLK_APB, "u3_dw_i2c_clk_apb",
                        0, JH7110_APB12),
-       JH7110_GATE(JH7110_I2C4_CLK_APB, "u4_dw_i2c_clk_apb", 
+       JH7110_GATE(JH7110_I2C4_CLK_APB, "u4_dw_i2c_clk_apb",
                        0, JH7110_APB12),
-       JH7110_GATE(JH7110_I2C5_CLK_APB, "u5_dw_i2c_clk_apb", 
+       JH7110_GATE(JH7110_I2C5_CLK_APB, "u5_dw_i2c_clk_apb",
                        0, JH7110_APB12),
-       JH7110_GATE(JH7110_I2C6_CLK_APB, "u6_dw_i2c_clk_apb", 
+       JH7110_GATE(JH7110_I2C6_CLK_APB, "u6_dw_i2c_clk_apb",
                        0, JH7110_APB12),
        //UART
-       JH7110_GATE(JH7110_UART0_CLK_APB, "u0_dw_uart_clk_apb", 
+       JH7110_GATE(JH7110_UART0_CLK_APB, "u0_dw_uart_clk_apb",
                        0, JH7110_APB0),
-       JH7110_GATE(JH7110_UART0_CLK_CORE, "u0_dw_uart_clk_core", 
+       JH7110_GATE(JH7110_UART0_CLK_CORE, "u0_dw_uart_clk_core",
                        0, JH7110_OSC),
-       JH7110_GATE(JH7110_UART1_CLK_APB, "u1_dw_uart_clk_apb", 
+       JH7110_GATE(JH7110_UART1_CLK_APB, "u1_dw_uart_clk_apb",
                        0, JH7110_APB0),
-       JH7110_GATE(JH7110_UART1_CLK_CORE, "u1_dw_uart_clk_core", 
+       JH7110_GATE(JH7110_UART1_CLK_CORE, "u1_dw_uart_clk_core",
                        0, JH7110_OSC),
-       JH7110_GATE(JH7110_UART2_CLK_APB, "u2_dw_uart_clk_apb", 
+       JH7110_GATE(JH7110_UART2_CLK_APB, "u2_dw_uart_clk_apb",
                        0, JH7110_APB0),
-       JH7110_GATE(JH7110_UART2_CLK_CORE, "u2_dw_uart_clk_core", 
+       JH7110_GATE(JH7110_UART2_CLK_CORE, "u2_dw_uart_clk_core",
                        0, JH7110_OSC),
-       JH7110_GATE(JH7110_UART3_CLK_APB, "u3_dw_uart_clk_apb", 
+       JH7110_GATE(JH7110_UART3_CLK_APB, "u3_dw_uart_clk_apb",
                        0, JH7110_APB0),
-       JH7110_GDIV(JH7110_UART3_CLK_CORE, "u3_dw_uart_clk_core", 
+       JH7110_GDIV(JH7110_UART3_CLK_CORE, "u3_dw_uart_clk_core",
                        0, 131071, JH7110_PERH_ROOT),
-       JH7110_GATE(JH7110_UART4_CLK_APB, "u4_dw_uart_clk_apb", 
+       JH7110_GATE(JH7110_UART4_CLK_APB, "u4_dw_uart_clk_apb",
                        0, JH7110_APB0),
-       JH7110_GDIV(JH7110_UART4_CLK_CORE, "u4_dw_uart_clk_core", 
+       JH7110_GDIV(JH7110_UART4_CLK_CORE, "u4_dw_uart_clk_core",
                        0, 131071, JH7110_PERH_ROOT),
-       JH7110_GATE(JH7110_UART5_CLK_APB, "u5_dw_uart_clk_apb", 
+       JH7110_GATE(JH7110_UART5_CLK_APB, "u5_dw_uart_clk_apb",
                        0, JH7110_APB0),
-       JH7110_GDIV(JH7110_UART5_CLK_CORE, "u5_dw_uart_clk_core", 
+       JH7110_GDIV(JH7110_UART5_CLK_CORE, "u5_dw_uart_clk_core",
                        0, 131071, JH7110_PERH_ROOT),
        //PWMDAC
-       JH7110_GATE(JH7110_PWMDAC_CLK_APB, "u0_pwmdac_clk_apb", 
+       JH7110_GATE(JH7110_PWMDAC_CLK_APB, "u0_pwmdac_clk_apb",
                        0, JH7110_APB0),
-       JH7110_GDIV(JH7110_PWMDAC_CLK_CORE, "u0_pwmdac_clk_core", 
+       JH7110_GDIV(JH7110_PWMDAC_CLK_CORE, "u0_pwmdac_clk_core",
                        0, 256, JH7110_AUDIO_ROOT),
        //SPDIF
-       JH7110_GATE(JH7110_SPDIF_CLK_APB, "u0_cdns_spdif_clk_apb", 
+       JH7110_GATE(JH7110_SPDIF_CLK_APB, "u0_cdns_spdif_clk_apb",
                        0, JH7110_APB0),
-       JH7110_GATE(JH7110_SPDIF_CLK_CORE, "u0_cdns_spdif_clk_core", 
+       JH7110_GATE(JH7110_SPDIF_CLK_CORE, "u0_cdns_spdif_clk_core",
                        0, JH7110_MCLK),
        //I2STX0_4CH0
-       JH7110_GATE(JH7110_I2STX0_4CHCLK_APB, "u0_i2stx_4ch_clk_apb", 
+       JH7110_GATE(JH7110_I2STX0_4CHCLK_APB, "u0_i2stx_4ch_clk_apb",
                        0, JH7110_APB0),
-       JH7110_GDIV(JH7110_I2STX_4CH0_BCLK_MST, "i2stx_4ch0_bclk_mst", 
+       JH7110_GDIV(JH7110_I2STX_4CH0_BCLK_MST, "i2stx_4ch0_bclk_mst",
                        0, 32, JH7110_MCLK),
-       JH7110__INV(JH7110_I2STX_4CH0_BCLK_MST_INV, "i2stx_4ch0_bclk_mst_inv", 
+       JH7110__INV(JH7110_I2STX_4CH0_BCLK_MST_INV, "i2stx_4ch0_bclk_mst_inv",
                        JH7110_I2STX_4CH0_BCLK_MST),
        JH7110_MDIV(JH7110_I2STX_4CH0_LRCK_MST, "i2stx_4ch0_lrck_mst", 64, 2,
                        JH7110_I2STX_4CH0_BCLK_MST_INV,
@@ -377,17 +377,17 @@ static const struct jh7110_clk_data jh7110_clk_sys_data[] __initconst = {
        JH7110__MUX(JH7110_I2STX0_4CHBCLK, "u0_i2stx_4ch_bclk", 2,
                        JH7110_I2STX_4CH0_BCLK_MST,
                        JH7110_I2STX_BCLK_EXT),
-       JH7110__INV(JH7110_I2STX0_4CHBCLK_N, "u0_i2stx_4ch_bclk_n", 
+       JH7110__INV(JH7110_I2STX0_4CHBCLK_N, "u0_i2stx_4ch_bclk_n",
                        JH7110_I2STX0_4CHBCLK),
        JH7110__MUX(JH7110_I2STX0_4CHLRCK, "u0_i2stx_4ch_lrck", 2,
                        JH7110_I2STX_4CH0_LRCK_MST,
                        JH7110_I2STX_LRCK_EXT),
        //I2STX1_4CH0
-       JH7110_GATE(JH7110_I2STX1_4CHCLK_APB, "u1_i2stx_4ch_clk_apb", 
+       JH7110_GATE(JH7110_I2STX1_4CHCLK_APB, "u1_i2stx_4ch_clk_apb",
                        0, JH7110_APB0),
-       JH7110_GDIV(JH7110_I2STX_4CH1_BCLK_MST, "i2stx_4ch1_bclk_mst", 
+       JH7110_GDIV(JH7110_I2STX_4CH1_BCLK_MST, "i2stx_4ch1_bclk_mst",
                        0, 32, JH7110_MCLK),
-       JH7110__INV(JH7110_I2STX_4CH1_BCLK_MST_INV, "i2stx_4ch1_bclk_mst_inv", 
+       JH7110__INV(JH7110_I2STX_4CH1_BCLK_MST_INV, "i2stx_4ch1_bclk_mst_inv",
                        JH7110_I2STX_4CH1_BCLK_MST),
        JH7110_MDIV(JH7110_I2STX_4CH1_LRCK_MST, "i2stx_4ch1_lrck_mst", 64, 2,
                        JH7110_I2STX_4CH1_BCLK_MST_INV,
@@ -395,17 +395,17 @@ static const struct jh7110_clk_data jh7110_clk_sys_data[] __initconst = {
        JH7110__MUX(JH7110_I2STX1_4CHBCLK, "u1_i2stx_4ch_bclk", 2,
                        JH7110_I2STX_4CH1_BCLK_MST,
                        JH7110_I2STX_BCLK_EXT),
-       JH7110__INV(JH7110_I2STX1_4CHBCLK_N, "u1_i2stx_4ch_bclk_n", 
+       JH7110__INV(JH7110_I2STX1_4CHBCLK_N, "u1_i2stx_4ch_bclk_n",
                        JH7110_I2STX1_4CHBCLK),
        JH7110__MUX(JH7110_I2STX1_4CHLRCK, "u1_i2stx_4ch_lrck", 2,
                        JH7110_I2STX_4CH1_LRCK_MST,
                        JH7110_I2STX_LRCK_EXT),
        //I2SRX_3CH
-       JH7110_GATE(JH7110_I2SRX0_3CH_CLK_APB, "u0_i2srx_3ch_clk_apb", 
+       JH7110_GATE(JH7110_I2SRX0_3CH_CLK_APB, "u0_i2srx_3ch_clk_apb",
                        0, JH7110_APB0),
-       JH7110_GDIV(JH7110_I2SRX_3CH_BCLK_MST, "i2srx_3ch_bclk_mst", 
+       JH7110_GDIV(JH7110_I2SRX_3CH_BCLK_MST, "i2srx_3ch_bclk_mst",
                        0, 32, JH7110_MCLK),
-       JH7110__INV(JH7110_I2SRX_3CH_BCLK_MST_INV, "i2srx_3ch_bclk_mst_inv", 
+       JH7110__INV(JH7110_I2SRX_3CH_BCLK_MST_INV, "i2srx_3ch_bclk_mst_inv",
                        JH7110_I2SRX_3CH_BCLK_MST),
        JH7110_MDIV(JH7110_I2SRX_3CH_LRCK_MST, "i2srx_3ch_lrck_mst", 64, 2,
                        JH7110_I2SRX_3CH_BCLK_MST_INV,
@@ -413,33 +413,33 @@ static const struct jh7110_clk_data jh7110_clk_sys_data[] __initconst = {
        JH7110__MUX(JH7110_I2SRX0_3CH_BCLK, "u0_i2srx_3ch_bclk", 2,
                        JH7110_I2SRX_3CH_BCLK_MST,
                        JH7110_I2SRX_BCLK_EXT),
-       JH7110__INV(JH7110_I2SRX0_3CH_BCLK_N, "u0_i2srx_3ch_bclk_n", 
+       JH7110__INV(JH7110_I2SRX0_3CH_BCLK_N, "u0_i2srx_3ch_bclk_n",
                        JH7110_I2SRX0_3CH_BCLK),
        JH7110__MUX(JH7110_I2SRX0_3CH_LRCK, "u0_i2srx_3ch_lrck", 2,
                        JH7110_I2SRX_3CH_LRCK_MST,
                        JH7110_I2SRX_LRCK_EXT),
        //PDM_4MIC
-       JH7110_GDIV(JH7110_PDM_CLK_DMIC, "u0_pdm_4mic_clk_dmic", 
+       JH7110_GDIV(JH7110_PDM_CLK_DMIC, "u0_pdm_4mic_clk_dmic",
                        0, 64, JH7110_MCLK),
-       JH7110_GATE(JH7110_PDM_CLK_APB, "u0_pdm_4mic_clk_apb", 
+       JH7110_GATE(JH7110_PDM_CLK_APB, "u0_pdm_4mic_clk_apb",
                        0, JH7110_APB0),
        //TDM
-       JH7110_GATE(JH7110_TDM_CLK_AHB, "u0_tdm16slot_clk_ahb", 
+       JH7110_GATE(JH7110_TDM_CLK_AHB, "u0_tdm16slot_clk_ahb",
                        0, JH7110_AHB0),
-       JH7110_GATE(JH7110_TDM_CLK_APB, "u0_tdm16slot_clk_apb", 
+       JH7110_GATE(JH7110_TDM_CLK_APB, "u0_tdm16slot_clk_apb",
                        0, JH7110_APB0),
-       JH7110_GDIV(JH7110_TDM_INTERNAL, "tdm_internal", 
+       JH7110_GDIV(JH7110_TDM_INTERNAL, "tdm_internal",
                        0, 64, JH7110_MCLK),
        JH7110__MUX(JH7110_TDM_CLK_TDM, "u0_tdm16slot_clk_tdm", 2,
                        JH7110_TDM_INTERNAL,
                        JH7110_TDM_EXT),
-       JH7110__INV(JH7110_TDM_CLK_TDM_N, "u0_tdm16slot_clk_tdm_n", 
+       JH7110__INV(JH7110_TDM_CLK_TDM_N, "u0_tdm16slot_clk_tdm_n",
                        JH7110_TDM_CLK_TDM),
-       JH7110__DIV(JH7110_JTAG_CERTIFICATION_TRNG_CLK, 
+       JH7110__DIV(JH7110_JTAG_CERTIFICATION_TRNG_CLK,
                        "u0_jtag_certification_trng_clk", 4, JH7110_OSC),
 };
 
-int __init clk_starfive_jh7110_sys_init(struct platform_device *pdev, 
+int __init clk_starfive_jh7110_sys_init(struct platform_device *pdev,
                                                struct jh7110_clk_priv *priv)
 {
        unsigned int idx;
@@ -449,302 +449,302 @@ int __init clk_starfive_jh7110_sys_init(struct platform_device *pdev,
        if (IS_ERR(priv->sys_base))
                return PTR_ERR(priv->sys_base);
        
-       priv->pll[PLL_OF(JH7110_PLL0_OUT)] = 
-                       clk_hw_register_fixed_rate(priv->dev, 
+       priv->pll[PLL_OF(JH7110_PLL0_OUT)] =
+                       clk_hw_register_fixed_rate(priv->dev,
                        "pll0_out", "osc", 0, 1250000000);
        if (IS_ERR(priv->pll[PLL_OF(JH7110_PLL0_OUT)]))
                return PTR_ERR(priv->pll[PLL_OF(JH7110_PLL0_OUT)]);
 
-       priv->pll[PLL_OF(JH7110_PLL1_OUT)] = 
-                       clk_hw_register_fixed_rate(priv->dev, 
+       priv->pll[PLL_OF(JH7110_PLL1_OUT)] =
+                       clk_hw_register_fixed_rate(priv->dev,
                        "pll1_out", "osc", 0, 1066000000);
        if (IS_ERR(priv->pll[PLL_OF(JH7110_PLL1_OUT)]))
                return PTR_ERR(priv->pll[PLL_OF(JH7110_PLL1_OUT)]);
 
-       priv->pll[PLL_OF(JH7110_PLL2_OUT)] = 
-                       clk_hw_register_fixed_rate(priv->dev, 
+       priv->pll[PLL_OF(JH7110_PLL2_OUT)] =
+                       clk_hw_register_fixed_rate(priv->dev,
                        "pll2_out", "osc", 0, 1228800000);
        if (IS_ERR(priv->pll[PLL_OF(JH7110_PLL2_OUT)]))
                return PTR_ERR(priv->pll[PLL_OF(JH7110_PLL2_OUT)]);
 
-       priv->pll[PLL_OF(JH7110_AON_APB)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_AON_APB)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "aon_apb", "apb_bus_func", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_RESET1_CTRL_CLK_SRC)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_RESET1_CTRL_CLK_SRC)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u1_reset_ctrl_clk_src", "osc", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_DDR_ROOT)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_DDR_ROOT)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "ddr_root", "pll1_out", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_VDEC_ROOT)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_VDEC_ROOT)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "vdec_root", "pll0_out", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_VENC_ROOT)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_VENC_ROOT)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "venc_root", "pll2_out", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_VOUT_ROOT)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_VOUT_ROOT)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "vout_root", "pll2_out", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_GMACUSB_ROOT)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_GMACUSB_ROOT)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "gmacusb_root", "pll0_out", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_PCLK2_MUX_FUNC_PCLK)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_PCLK2_MUX_FUNC_PCLK)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u2_pclk_mux_func_pclk", "apb_bus_func", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_PCLK2_MUX_BIST_PCLK)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_PCLK2_MUX_BIST_PCLK)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u2_pclk_mux_bist_pclk", "bist_apb", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_APB_BUS)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_APB_BUS)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "apb_bus", "u2_pclk_mux_pclk", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_APB12)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_APB12)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "apb12", "apb_bus", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_AXI_CFG1)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_AXI_CFG1)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "axi_cfg1", "isp_axi", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_PLL_WRAP_CRG_GCLK0)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_PLL_WRAP_CRG_GCLK0)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u0_pll_wrap_crg_gclk0", "gclk0", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_PLL_WRAP_CRG_GCLK1)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_PLL_WRAP_CRG_GCLK1)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u0_pll_wrap_crg_gclk1", "gclk1", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_PLL_WRAP_CRG_GCLK2)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_PLL_WRAP_CRG_GCLK2)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u0_pll_wrap_crg_gclk2", "gclk2", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_JTAG2APB_PCLK)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_JTAG2APB_PCLK)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u0_jtag2apb_pclk", "bist_apb", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_U7_BUS_CLK)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_U7_BUS_CLK)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u0_u7mc_sft7110_bus_clk", "cpu_bus", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_U7_IRQ_SYNC_BUS_CLK)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_U7_IRQ_SYNC_BUS_CLK)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u0_u7mc_sft7110_irq_sync_bus_clk", "cpu_bus", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_NOC_BUS_CLK2_CPU_AXI)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
-                       "u0_sft7110_noc_bus_clk2_cpu_axi", 
+       priv->pll[PLL_OF(JH7110_NOC_BUS_CLK2_CPU_AXI)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
+                       "u0_sft7110_noc_bus_clk2_cpu_axi",
                        "u0_sft7110_noc_bus_clk_cpu_axi", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_NOC_BUS_CLK_APB_BUS)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_NOC_BUS_CLK_APB_BUS)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u0_sft7110_noc_bus_clk_apb_bus", "apb_bus", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_NOC_BUS_CLK2_APB_BUS)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
-                       "u0_sft7110_noc_bus_clk2_apb_bus", 
+       priv->pll[PLL_OF(JH7110_NOC_BUS_CLK2_APB_BUS)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
+                       "u0_sft7110_noc_bus_clk2_apb_bus",
                        "u0_sft7110_noc_bus_clk_apb_bus", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_NOC_BUS_CLK2_AXICFG0_AXI)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
-                       "u0_sft7110_noc_bus_clk2_axicfg0_axi", 
+       priv->pll[PLL_OF(JH7110_NOC_BUS_CLK2_AXICFG0_AXI)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
+                       "u0_sft7110_noc_bus_clk2_axicfg0_axi",
                        "u0_sft7110_noc_bus_clk_axicfg0_axi", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_DDR_CLK_DDRPHY_PLL_BYPASS)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
-                       "u0_ddr_sft7110_clk_ddrphy_pll_bypass", 
+       priv->pll[PLL_OF(JH7110_DDR_CLK_DDRPHY_PLL_BYPASS)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
+                       "u0_ddr_sft7110_clk_ddrphy_pll_bypass",
                        "pll1_out", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_DDR_CLK_OSC)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_DDR_CLK_OSC)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u0_ddr_sft7110_clk_osc", "osc", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_DDR_CLK_APB)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_DDR_CLK_APB)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u0_ddr_sft7110_clk_apb", "apb12", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_NOC_BUS_CLK_DDRC)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_NOC_BUS_CLK_DDRC)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u0_sft7110_noc_bus_clk_ddrc", "ddr_bus", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_NOC_BUS_CLK2_DDRC)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
-                       "u0_sft7110_noc_bus_clk2_ddrc", 
+       priv->pll[PLL_OF(JH7110_NOC_BUS_CLK2_DDRC)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
+                       "u0_sft7110_noc_bus_clk2_ddrc",
                        "u0_sft7110_noc_bus_clk_ddrc", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_SYS_AHB_DEC_CLK_AHB)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_SYS_AHB_DEC_CLK_AHB)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u0_saif_amba_sys_ahb_dec_clk_ahb", "ahb0", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_STG_AHB_DEC_CLK_AHB)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_STG_AHB_DEC_CLK_AHB)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u0_saif_amba_stg_ahb_dec_clk_ahb", "ahb0", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_NOC_BUS_CLK2_GPU_AXI)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
-                       "u0_sft7110_noc_bus_clk2_gpu_axi", 
+       priv->pll[PLL_OF(JH7110_NOC_BUS_CLK2_GPU_AXI)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
+                       "u0_sft7110_noc_bus_clk2_gpu_axi",
                        "u0_sft7110_noc_bus_clk_gpu_axi", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_ISP_TOP_CLK_DVP)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
-                       "u0_dom_isp_top_clk_dom_isp_top_clk_dvp", 
+       priv->pll[PLL_OF(JH7110_ISP_TOP_CLK_DVP)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
+                       "u0_dom_isp_top_clk_dom_isp_top_clk_dvp",
                        "dvp_clk", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_NOC_BUS_CLK2_ISP_AXI)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
-                       "u0_sft7110_noc_bus_clk2_isp_axi", 
+       priv->pll[PLL_OF(JH7110_NOC_BUS_CLK2_ISP_AXI)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
+                       "u0_sft7110_noc_bus_clk2_isp_axi",
                        "u0_sft7110_noc_bus_clk_isp_axi", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_ISP_TOP_CLK_BIST_APB)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
-                       "u0_dom_isp_top_clk_dom_isp_top_clk_bist_apb", 
+       priv->pll[PLL_OF(JH7110_ISP_TOP_CLK_BIST_APB)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
+                       "u0_dom_isp_top_clk_dom_isp_top_clk_bist_apb",
                        "bist_apb", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_NOC_BUS_CLK2_DISP_AXI)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
-                       "u0_sft7110_noc_bus_clk2_disp_axi", 
+       priv->pll[PLL_OF(JH7110_NOC_BUS_CLK2_DISP_AXI)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
+                       "u0_sft7110_noc_bus_clk2_disp_axi",
                        "u0_sft7110_noc_bus_clk_disp_axi", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_VOUT_TOP_CLK_HDMITX0_BCLK)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
-                       "u0_dom_vout_top_clk_dom_vout_top_clk_hdmitx0_bclk", 
+       priv->pll[PLL_OF(JH7110_VOUT_TOP_CLK_HDMITX0_BCLK)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
+                       "u0_dom_vout_top_clk_dom_vout_top_clk_hdmitx0_bclk",
                        "u0_i2stx_4ch_bclk", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_VOUT_TOP_U0_HDMI_TX_PIN_WS)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
-                       "u0_dom_vout_top_u0_hdmi_tx_pin_ws", 
+       priv->pll[PLL_OF(JH7110_VOUT_TOP_U0_HDMI_TX_PIN_WS)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
+                       "u0_dom_vout_top_u0_hdmi_tx_pin_ws",
                        "u0_i2stx_4ch_lrck", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_VOUT_TOP_CLK_HDMIPHY_REF)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
-                       "u0_dom_vout_top_clk_dom_vout_top_clk_hdmiphy_ref", 
+       priv->pll[PLL_OF(JH7110_VOUT_TOP_CLK_HDMIPHY_REF)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
+                       "u0_dom_vout_top_clk_dom_vout_top_clk_hdmiphy_ref",
                        "osc", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_VOUT_TOP_BIST_PCLK)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
-                       "u0_dom_vout_top_clk_dom_vout_top_bist_pclk", 
+       priv->pll[PLL_OF(JH7110_VOUT_TOP_BIST_PCLK)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
+                       "u0_dom_vout_top_clk_dom_vout_top_bist_pclk",
                        "bist_apb", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_AXIMEM0_128B_CLK_AXI)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
-                       "u0_aximem_128b_clk_axi", 
+       priv->pll[PLL_OF(JH7110_AXIMEM0_128B_CLK_AXI)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
+                       "u0_aximem_128b_clk_axi",
                        "u0_WAVE511_clk_axi", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_VDEC_INTSRAM_CLK_VDEC_AXI)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
-                       "u0_vdec_intsram_clk_vdec_axi", 
+       priv->pll[PLL_OF(JH7110_VDEC_INTSRAM_CLK_VDEC_AXI)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
+                       "u0_vdec_intsram_clk_vdec_axi",
                        "u0_aximem_128b_clk_axi", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_NOC_BUS_CLK2_VDEC_AXI)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
-                       "u0_sft7110_noc_bus_clk2_vdec_axi", 
+       priv->pll[PLL_OF(JH7110_NOC_BUS_CLK2_VDEC_AXI)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
+                       "u0_sft7110_noc_bus_clk2_vdec_axi",
                        "u0_sft7110_noc_bus_clk_vdec_axi", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_AXIMEM1_128B_CLK_AXI)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
-                       "u1_aximem_128b_clk_axi", 
+       priv->pll[PLL_OF(JH7110_AXIMEM1_128B_CLK_AXI)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
+                       "u1_aximem_128b_clk_axi",
                        "u0_wave420l_clk_axi", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_VENC_INTSRAM_CLK_VENC_AXI)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
-                       "u0_venc_intsram_clk_venc_axi", 
+       priv->pll[PLL_OF(JH7110_VENC_INTSRAM_CLK_VENC_AXI)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
+                       "u0_venc_intsram_clk_venc_axi",
                        "u0_wave420l_clk_axi", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_NOC_BUS_CLK2_VENC_AXI)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
-                       "u0_sft7110_noc_bus_clk2_venc_axi", 
+       priv->pll[PLL_OF(JH7110_NOC_BUS_CLK2_VENC_AXI)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
+                       "u0_sft7110_noc_bus_clk2_venc_axi",
                        "u0_sft7110_noc_bus_clk_venc_axi", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_SRAM_CLK_ROM)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
-                       "u0_intmem_rom_sram_clk_rom", 
+       priv->pll[PLL_OF(JH7110_SRAM_CLK_ROM)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
+                       "u0_intmem_rom_sram_clk_rom",
                        "u2_aximem_128b_clk_axi", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_NOC_BUS_CLK2_STG_AXI)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
-                       "u0_sft7110_noc_bus_clk2_stg_axi", 
+       priv->pll[PLL_OF(JH7110_NOC_BUS_CLK2_STG_AXI)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
+                       "u0_sft7110_noc_bus_clk2_stg_axi",
                        "u0_sft7110_noc_bus_clk_stg_axi", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_GMAC5_CLK_RMII)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
-                       "u1_dw_gmac5_axi64_clk_rmii", 
+       priv->pll[PLL_OF(JH7110_GMAC5_CLK_RMII)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
+                       "u1_dw_gmac5_axi64_clk_rmii",
                        "gmac1_rmii_refin", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_AON_AHB)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_AON_AHB)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "aon_ahb", "stg_axiahb", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_SYS_CRG_PCLK)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_SYS_CRG_PCLK)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u0_sys_crg_pclk", "apb12", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_SYS_SYSCON_PCLK)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_SYS_SYSCON_PCLK)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u0_sys_syscon_pclk", "apb12", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_SPI0_CLK_CORE)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_SPI0_CLK_CORE)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u0_ssp_spi_clk_core", "u0_ssp_spi_clk_apb", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_SPI1_CLK_CORE)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_SPI1_CLK_CORE)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u1_ssp_spi_clk_core", "u1_ssp_spi_clk_apb", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_SPI2_CLK_CORE)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_SPI2_CLK_CORE)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u2_ssp_spi_clk_core", "u2_ssp_spi_clk_apb", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_SPI3_CLK_CORE)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_SPI3_CLK_CORE)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u3_ssp_spi_clk_core", "u3_ssp_spi_clk_apb", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_SPI4_CLK_CORE)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_SPI4_CLK_CORE)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u4_ssp_spi_clk_core", "u4_ssp_spi_clk_apb", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_SPI5_CLK_CORE)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_SPI5_CLK_CORE)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u5_ssp_spi_clk_core", "u5_ssp_spi_clk_apb", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_SPI6_CLK_CORE)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_SPI6_CLK_CORE)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u6_ssp_spi_clk_core", "u6_ssp_spi_clk_apb", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_I2C0_CLK_CORE)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_I2C0_CLK_CORE)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u0_dw_i2c_clk_core", "u0_dw_i2c_clk_apb", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_I2C1_CLK_CORE)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_I2C1_CLK_CORE)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u1_dw_i2c_clk_core", "u1_dw_i2c_clk_apb", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_I2C2_CLK_CORE)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_I2C2_CLK_CORE)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u2_dw_i2c_clk_core", "u2_dw_i2c_clk_apb", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_I2C3_CLK_CORE)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_I2C3_CLK_CORE)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u3_dw_i2c_clk_core", "u3_dw_i2c_clk_apb", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_I2C4_CLK_CORE)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_I2C4_CLK_CORE)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u4_dw_i2c_clk_core", "u4_dw_i2c_clk_apb", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_I2C5_CLK_CORE)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_I2C5_CLK_CORE)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u5_dw_i2c_clk_core", "u5_dw_i2c_clk_apb", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_I2C6_CLK_CORE)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_I2C6_CLK_CORE)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u6_dw_i2c_clk_core", "u6_dw_i2c_clk_apb", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_I2STX_BCLK_MST)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_I2STX_BCLK_MST)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "i2stx_bclk_mst", "i2stx_4ch1_bclk_mst", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_I2STX_LRCK_MST)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_I2STX_LRCK_MST)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "i2stx_lrck_mst", "i2stx_4ch1_lrck_mst", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_I2SRX_BCLK_MST)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_I2SRX_BCLK_MST)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "i2srx_bclk_mst", "i2srx_3ch_bclk_mst", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_I2SRX_LRCK_MST)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_I2SRX_LRCK_MST)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "i2srx_lrck_mst", "i2srx_3ch_lrck_mst", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_PDM_CLK_DMIC0_BCLK_SLV)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
-                       "u0_pdm_4mic_clk_dmic0_bclk_slv", 
+       priv->pll[PLL_OF(JH7110_PDM_CLK_DMIC0_BCLK_SLV)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
+                       "u0_pdm_4mic_clk_dmic0_bclk_slv",
                        "u0_i2srx_3ch_bclk", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_PDM_CLK_DMIC0_LRCK_SLV)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
-                       "u0_pdm_4mic_clk_dmic0_lrck_slv", 
+       priv->pll[PLL_OF(JH7110_PDM_CLK_DMIC0_LRCK_SLV)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
+                       "u0_pdm_4mic_clk_dmic0_lrck_slv",
                        "u0_i2srx_3ch_lrck", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_PDM_CLK_DMIC1_BCLK_SLV)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
-                       "u0_pdm_4mic_clk_dmic1_bclk_slv", 
+       priv->pll[PLL_OF(JH7110_PDM_CLK_DMIC1_BCLK_SLV)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
+                       "u0_pdm_4mic_clk_dmic1_bclk_slv",
                        "u0_i2srx_3ch_bclk", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_PDM_CLK_DMIC1_LRCK_SLV)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
-                       "u0_pdm_4mic_clk_dmic1_lrck_slv", 
+       priv->pll[PLL_OF(JH7110_PDM_CLK_DMIC1_LRCK_SLV)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
+                       "u0_pdm_4mic_clk_dmic1_lrck_slv",
                        "u0_i2srx_3ch_lrck", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_TDM_CLK_MST)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_TDM_CLK_MST)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "tdm_clk_mst", "ahb0", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_AHB2APB_CLK_AHB)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_AHB2APB_CLK_AHB)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u1_ahb2apb_clk_ahb", "tdm_internal", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_P2P_ASYNC_CLK_APBS)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_P2P_ASYNC_CLK_APBS)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u1_p2p_async_clk_apbs", "apb0", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_P2P_ASYNC_CLK_APBM)] = \
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OF(JH7110_P2P_ASYNC_CLK_APBM)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u1_p2p_async_clk_apbm", "aon_apb", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_JTAG_DAISY_CHAIN_JTAG_TCK)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
-                       "u0_jtag_daisy_chain_JTAG_TCK", 
+       priv->pll[PLL_OF(JH7110_JTAG_DAISY_CHAIN_JTAG_TCK)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
+                       "u0_jtag_daisy_chain_JTAG_TCK",
                        "jtag_tck_inner", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_U7_DEBUG_SYSTEMJTAG_JTAG_TCK)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
-                       "u0_u7mc_sft7110_debug_systemjtag_jtag_TCK", 
+       priv->pll[PLL_OF(JH7110_U7_DEBUG_SYSTEMJTAG_JTAG_TCK)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
+                       "u0_u7mc_sft7110_debug_systemjtag_jtag_TCK",
                        "u0_jtag_daisy_chain_jtag_tck_0", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_E2_DEBUG_SYSTEMJTAG_TCK)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
-                       "u0_e2_sft7110_debug_systemjtag_jtag_TCK", 
+       priv->pll[PLL_OF(JH7110_E2_DEBUG_SYSTEMJTAG_TCK)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
+                       "u0_e2_sft7110_debug_systemjtag_jtag_TCK",
                        "u0_jtag_daisy_chain_jtag_tck_1", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_JTAG_CERTIFICATION_TCK)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
-                       "u0_jtag_certification_tck", 
+       priv->pll[PLL_OF(JH7110_JTAG_CERTIFICATION_TCK)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
+                       "u0_jtag_certification_tck",
                        "jtag_tck_inner", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_SEC_SKP_CLK)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
-                       "u0_sec_top_skp_clk", 
+       priv->pll[PLL_OF(JH7110_SEC_SKP_CLK)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
+                       "u0_sec_top_skp_clk",
                        "u0_jtag_certification_trng_clk", 0, 1, 1);
-       priv->pll[PLL_OF(JH7110_U2_PCLK_MUX_PCLK)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
-                       "u2_pclk_mux_pclk", 
+       priv->pll[PLL_OF(JH7110_U2_PCLK_MUX_PCLK)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
+                       "u2_pclk_mux_pclk",
                        "u2_pclk_mux_func_pclk", 0, 1, 1);
 
 

diff --git a/drivers/clk/starfive/clk-starfive-jh7110-vout.c b/drivers/clk/starfive/clk-starfive-jh7110-vout.c
index 85229c9..4bd1036 100755 (executable)
--- a/drivers/clk/starfive/clk-starfive-jh7110-vout.c
+++ b/drivers/clk/starfive/clk-starfive-jh7110-vout.c
@@ -28,11 +28,11 @@ static const struct jh7110_clk_data jh7110_clk_vout_data[] __initconst = {
        JH7110__DIV(JH7110_DSI_SYS, "dsi_sys", 31, JH7110_DISP_ROOT),
        JH7110__DIV(JH7110_TX_ESC, "tx_esc", 31, JH7110_DISP_AHB),
        //dc8200
-       JH7110_GATE(JH7110_U0_DC8200_CLK_AXI, "u0_dc8200_clk_axi", 
+       JH7110_GATE(JH7110_U0_DC8200_CLK_AXI, "u0_dc8200_clk_axi",
                        0, JH7110_DISP_AXI),
-       JH7110_GATE(JH7110_U0_DC8200_CLK_CORE, "u0_dc8200_clk_core", 
+       JH7110_GATE(JH7110_U0_DC8200_CLK_CORE, "u0_dc8200_clk_core",
                        0, JH7110_DISP_AXI),
-       JH7110_GATE(JH7110_U0_DC8200_CLK_AHB, "u0_dc8200_clk_ahb", 
+       JH7110_GATE(JH7110_U0_DC8200_CLK_AHB, "u0_dc8200_clk_ahb",
                        0, JH7110_DISP_AHB),
        JH7110_GMUX(JH7110_U0_DC8200_CLK_PIX0, "u0_dc8200_clk_pix0", 0, 2,
                        JH7110_DC8200_PIX0,
@@ -45,28 +45,28 @@ static const struct jh7110_clk_data jh7110_clk_vout_data[] __initconst = {
                        JH7110_U0_DC8200_CLK_PIX0_OUT,
                        JH7110_U0_DC8200_CLK_PIX1_OUT),
        //dsiTx
-       JH7110_GATE(JH7110_U0_CDNS_DSITX_CLK_APB, "u0_cdns_dsiTx_clk_apb", 
+       JH7110_GATE(JH7110_U0_CDNS_DSITX_CLK_APB, "u0_cdns_dsiTx_clk_apb",
                        0, JH7110_DSI_SYS),
-       JH7110_GATE(JH7110_U0_CDNS_DSITX_CLK_SYS, "u0_cdns_dsiTx_clk_sys", 
+       JH7110_GATE(JH7110_U0_CDNS_DSITX_CLK_SYS, "u0_cdns_dsiTx_clk_sys",
                        0, JH7110_DSI_SYS),
        JH7110_GMUX(JH7110_U0_CDNS_DSITX_CLK_DPI, "u0_cdns_dsiTx_clk_api", 0, 2,
                        JH7110_DC8200_PIX0,
                        JH7110_HDMITX0_PIXELCLK),
-       JH7110_GATE(JH7110_U0_CDNS_DSITX_CLK_TXESC, "u0_cdns_dsiTx_clk_txesc", 
+       JH7110_GATE(JH7110_U0_CDNS_DSITX_CLK_TXESC, "u0_cdns_dsiTx_clk_txesc",
                        0, JH7110_TX_ESC),
        //mipitx DPHY
-       JH7110_GATE(JH7110_U0_MIPITX_DPHY_CLK_TXESC, "u0_mipitx_dphy_clk_txesc", 
+       JH7110_GATE(JH7110_U0_MIPITX_DPHY_CLK_TXESC, "u0_mipitx_dphy_clk_txesc",
                        0, JH7110_TX_ESC),
        //hdmi
-       JH7110_GATE(JH7110_U0_HDMI_TX_CLK_MCLK, "u0_hdmi_tx_clk_mclk", 
+       JH7110_GATE(JH7110_U0_HDMI_TX_CLK_MCLK, "u0_hdmi_tx_clk_mclk",
                        0, JH7110_HDMITX0_MCLK),
-       JH7110_GATE(JH7110_U0_HDMI_TX_CLK_BCLK, "u0_hdmi_tx_clk_bclk", 
+       JH7110_GATE(JH7110_U0_HDMI_TX_CLK_BCLK, "u0_hdmi_tx_clk_bclk",
                        0, JH7110_HDMITX0_SCK),
-       JH7110_GATE(JH7110_U0_HDMI_TX_CLK_SYS, "u0_hdmi_tx_clk_sys", 
+       JH7110_GATE(JH7110_U0_HDMI_TX_CLK_SYS, "u0_hdmi_tx_clk_sys",
                        0, JH7110_DISP_APB),
 };
 
-static struct clk_hw *jh7110_vout_clk_get(struct of_phandle_args *clkspec, 
+static struct clk_hw *jh7110_vout_clk_get(struct of_phandle_args *clkspec,
                                        void *data)
 {
        struct jh7110_clk_priv *priv = data;
@@ -87,7 +87,7 @@ static int __init clk_starfive_jh7110_vout_probe(struct platform_device *pdev)
        unsigned int idx;
        int ret = 0;
 
-       priv = devm_kzalloc(&pdev->dev, struct_size(priv, 
+       priv = devm_kzalloc(&pdev->dev, struct_size(priv,
                                reg, JH7110_DISP_ROOT), GFP_KERNEL);
        if (!priv)
                return -ENOMEM;
@@ -99,103 +99,103 @@ static int __init clk_starfive_jh7110_vout_probe(struct platform_device *pdev)
                return PTR_ERR(priv->vout_base);
 
        //source
-       priv->pll[PLL_OFV(JH7110_DISP_ROOT)] = 
+       priv->pll[PLL_OFV(JH7110_DISP_ROOT)] =
                        devm_clk_hw_register_fixed_factor(
-                       priv->dev, "disp_root", 
-                       "u0_dom_vout_top_clk_dom_vout_top_clk_vout_src", 
+                       priv->dev, "disp_root",
+                       "u0_dom_vout_top_clk_dom_vout_top_clk_vout_src",
                        0, 1, 1);
-       priv->pll[PLL_OFV(JH7110_DISP_AXI)] = 
+       priv->pll[PLL_OFV(JH7110_DISP_AXI)] =
                        devm_clk_hw_register_fixed_factor(
-                       priv->dev, "disp_axi", 
-                       "u0_dom_vout_top_clk_dom_vout_top_clk_vout_axi", 
+                       priv->dev, "disp_axi",
+                       "u0_dom_vout_top_clk_dom_vout_top_clk_vout_axi",
                        0, 1, 1);
-       priv->pll[PLL_OFV(JH7110_DISP_AHB)] = 
+       priv->pll[PLL_OFV(JH7110_DISP_AHB)] =
                        devm_clk_hw_register_fixed_factor(
-                       priv->dev, "disp_ahb", 
-                       "u0_dom_vout_top_clk_dom_vout_top_clk_vout_ahb", 
+                       priv->dev, "disp_ahb",
+                       "u0_dom_vout_top_clk_dom_vout_top_clk_vout_ahb",
                        0, 1, 1);
-       priv->pll[PLL_OFV(JH7110_HDMI_PHY_REF)] = 
+       priv->pll[PLL_OFV(JH7110_HDMI_PHY_REF)] =
                        devm_clk_hw_register_fixed_factor(
-                       priv->dev, "hdmi_phy_ref", 
-                       "u0_dom_vout_top_clk_dom_vout_top_clk_hdmiphy_ref", 
+                       priv->dev, "hdmi_phy_ref",
+                       "u0_dom_vout_top_clk_dom_vout_top_clk_hdmiphy_ref",
                        0, 1, 1);
-       priv->pll[PLL_OFV(JH7110_HDMITX0_MCLK)] = 
+       priv->pll[PLL_OFV(JH7110_HDMITX0_MCLK)] =
                        devm_clk_hw_register_fixed_factor(
-                       priv->dev, "hdmitx0_mclk", 
-                       "u0_dom_vout_top_clk_dom_vout_top_clk_hdmitx0_mclk", 
+                       priv->dev, "hdmitx0_mclk",
+                       "u0_dom_vout_top_clk_dom_vout_top_clk_hdmitx0_mclk",
                        0, 1, 1);
-       priv->pll[PLL_OFV(JH7110_HDMITX0_SCK)] = 
+       priv->pll[PLL_OFV(JH7110_HDMITX0_SCK)] =
                        devm_clk_hw_register_fixed_factor(
-                       priv->dev, "hdmitx0_sck", 
-                       "u0_dom_vout_top_clk_dom_vout_top_clk_hdmitx0_bclk", 
+                       priv->dev, "hdmitx0_sck",
+                       "u0_dom_vout_top_clk_dom_vout_top_clk_hdmitx0_bclk",
                        0, 1, 1);
        
-       priv->pll[PLL_OFV(JH7110_MIPI_DPHY_REF)] = 
+       priv->pll[PLL_OFV(JH7110_MIPI_DPHY_REF)] =
                        devm_clk_hw_register_fixed_factor(
-                       priv->dev, "mipi_dphy_ref", 
-                       "u0_dom_vout_top_clk_dom_vout_top_clk_mipiphy_ref", 
+                       priv->dev, "mipi_dphy_ref",
+                       "u0_dom_vout_top_clk_dom_vout_top_clk_mipiphy_ref",
                        0, 1, 1);
        //divider
-       priv->pll[PLL_OFV(JH7110_U0_PCLK_MUX_BIST_PCLK)] = 
+       priv->pll[PLL_OFV(JH7110_U0_PCLK_MUX_BIST_PCLK)] =
                        devm_clk_hw_register_fixed_factor(
-                       priv->dev, "u0_pclk_mux_bist_pclk", 
-                       "u0_dom_vout_top_clk_dom_vout_top_bist_pclk", 
+                       priv->dev, "u0_pclk_mux_bist_pclk",
+                       "u0_dom_vout_top_clk_dom_vout_top_bist_pclk",
                        0, 1, 1);
-       priv->pll[PLL_OFV(JH7110_DISP_APB)] = 
-                       clk_hw_register_fixed_rate(priv->dev, 
+       priv->pll[PLL_OFV(JH7110_DISP_APB)] =
+                       clk_hw_register_fixed_rate(priv->dev,
                        "disp_apb", NULL, 0, 51200000);
-       priv->pll[PLL_OFV(JH7110_U0_PCLK_MUX_FUNC_PCLK)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OFV(JH7110_U0_PCLK_MUX_FUNC_PCLK)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u0_pclk_mux_func_pclk", "apb", 0, 1, 1);
        //bus
-       priv->pll[PLL_OFV(JH7110_U0_DOM_VOUT_CRG_PCLK)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OFV(JH7110_U0_DOM_VOUT_CRG_PCLK)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u0_dom_vout_crg_pclk", "disp_apb", 0, 1, 1);
-       priv->pll[PLL_OFV(JH7110_U0_DOM_VOUT_SYSCON_PCLK)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OFV(JH7110_U0_DOM_VOUT_SYSCON_PCLK)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u0_dom_vout_syscon_pclk", "disp_apb", 0, 1, 1);
-       priv->pll[PLL_OFV(JH7110_U0_SAIF_AMBA_DOM_VOUT_AHB_DEC_CLK_AHB)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
-                       "u0_saif_amba_dom_vout_ahb_dec_clk_ahb", 
+       priv->pll[PLL_OFV(JH7110_U0_SAIF_AMBA_DOM_VOUT_AHB_DEC_CLK_AHB)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
+                       "u0_saif_amba_dom_vout_ahb_dec_clk_ahb",
                        "disp_ahb", 0, 1, 1);
-       priv->pll[PLL_OFV(JH7110_U0_AHB2APB_CLK_AHB)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OFV(JH7110_U0_AHB2APB_CLK_AHB)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u0_ahb2apb_clk_ahb", "disp_ahb", 0, 1, 1);
-       priv->pll[PLL_OFV(JH7110_U0_P2P_ASYNC_CLK_APBS)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OFV(JH7110_U0_P2P_ASYNC_CLK_APBS)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u0_p2p_async_clk_apbs", "disp_apb", 0, 1, 1);
        //dsiTx
-       priv->pll[PLL_OFV(JH7110_U0_CDNS_DSITX_CLK_RXESC)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
-                       "u0_cdns_dsiTx_clk_rxesc", 
+       priv->pll[PLL_OFV(JH7110_U0_CDNS_DSITX_CLK_RXESC)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
+                       "u0_cdns_dsiTx_clk_rxesc",
                        "mipitx_dphy_rxesc", 0, 1, 1);
-       priv->pll[PLL_OFV(JH7110_U0_CDNS_DSITX_CLK_TXBYTEHS)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
-                       "u0_cdns_dsiTx_clk_txbytehs", 
+       priv->pll[PLL_OFV(JH7110_U0_CDNS_DSITX_CLK_TXBYTEHS)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
+                       "u0_cdns_dsiTx_clk_txbytehs",
                        "mipitx_dphy_txbytehs", 0, 1, 1);
        //mipitx DPHY
-       priv->pll[PLL_OFV(JH7110_U0_MIPITX_DPHY_CLK_SYS)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OFV(JH7110_U0_MIPITX_DPHY_CLK_SYS)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u0_mipitx_dphy_clk_sys", "disp_apb", 0, 1, 1);
-       priv->pll[PLL_OFV(JH7110_U0_MIPITX_DPHY_CLK_DPHY_REF)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
-                       "u0_mipitx_dphy_clk_dphy_ref", 
+       priv->pll[PLL_OFV(JH7110_U0_MIPITX_DPHY_CLK_DPHY_REF)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
+                       "u0_mipitx_dphy_clk_dphy_ref",
                        "mipi_dphy_ref", 0, 1, 1);
-       priv->pll[PLL_OFV(JH7110_U0_MIPITX_APBIF_PCLK)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OFV(JH7110_U0_MIPITX_APBIF_PCLK)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u0_mipitx_apbif_pclk", "disp_apb", 0, 1, 1);
        //hdmi
-       priv->pll[PLL_OFV(JH7110_HDMI_TX_CLK_REF)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
+       priv->pll[PLL_OFV(JH7110_HDMI_TX_CLK_REF)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
                        "u0_hdmi_tx_clk_ref", "hdmi_phy_ref", 0, 1, 1);
        
-       priv->pll[PLL_OFV(JH7110_U0_DC8200_CLK_PIX0_OUT)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
-                       "u0_dc8200_clk_pix0_out", 
+       priv->pll[PLL_OFV(JH7110_U0_DC8200_CLK_PIX0_OUT)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
+                       "u0_dc8200_clk_pix0_out",
                        "u0_dc8200_clk_pix0", 0, 1, 1);
-       priv->pll[PLL_OFV(JH7110_U0_DC8200_CLK_PIX1_OUT)] = 
-                       devm_clk_hw_register_fixed_factor(priv->dev, 
-                       "u0_dc8200_clk_pix1_out", 
+       priv->pll[PLL_OFV(JH7110_U0_DC8200_CLK_PIX1_OUT)] =
+                       devm_clk_hw_register_fixed_factor(priv->dev,
+                       "u0_dc8200_clk_pix1_out",
                        "u0_dc8200_clk_pix1", 0, 1, 1);
 
        for (idx = 0; idx < JH7110_DISP_ROOT; idx++) {