u32 tsec1_clk;
u32 tsec2_clk;
u32 usbdr_clk;
+#elif defined(CONFIG_MPC8309)
+ u32 usbdr_clk;
#endif
#ifdef CONFIG_MPC834x
u32 usbmph_clk;
#if defined(CONFIG_FSL_ESDHC)
u32 sdhc_clk;
#endif
+#if !defined(CONFIG_MPC8309)
u32 enc_clk;
+#endif
u32 lbiu_clk;
u32 lclk_clk;
u32 mem_clk;
return -6;
}
#endif
+#if !defined(CONFIG_MPC8309)
switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
case 0:
enc_clk = 0;
/* unkown SCCR_ENCCM value */
return -7;
}
+#endif
#if defined(CONFIG_FSL_ESDHC)
switch ((sccr & SCCR_SDHCCM) >> SCCR_SDHCCM_SHIFT) {
i2c1_clk = sdhc_clk;
#elif defined(CONFIG_MPC837x)
i2c1_clk = enc_clk;
+#elif defined(CONFIG_MPC8309)
+ i2c1_clk = csb_clk;
#endif
#if !defined(CONFIG_MPC832x)
i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
gd->tsec1_clk = tsec1_clk;
gd->tsec2_clk = tsec2_clk;
gd->usbdr_clk = usbdr_clk;
+#elif defined(CONFIG_MPC8309)
+ gd->usbdr_clk = usbdr_clk;
#endif
#if defined(CONFIG_MPC834x)
gd->usbmph_clk = usbmph_clk;
#if !defined(CONFIG_MPC832x)
gd->i2c2_clk = i2c2_clk;
#endif
+#if !defined(CONFIG_MPC8309)
gd->enc_clk = enc_clk;
+#endif
gd->lbiu_clk = lbiu_clk;
gd->lclk_clk = lclk_clk;
gd->mem_clk = mem_clk;
#if defined(CONFIG_MPC8360)
printf(" DDR Secondary: %-4s MHz\n", strmhz(buf, gd->mem_sec_clk));
#endif
+#if !defined(CONFIG_MPC8309)
printf(" SEC: %-4s MHz\n", strmhz(buf, gd->enc_clk));
+#endif
printf(" I2C1: %-4s MHz\n", strmhz(buf, gd->i2c1_clk));
#if !defined(CONFIG_MPC832x)
printf(" I2C2: %-4s MHz\n", strmhz(buf, gd->i2c2_clk));
printf(" TSEC1: %-4s MHz\n", strmhz(buf, gd->tsec1_clk));
printf(" TSEC2: %-4s MHz\n", strmhz(buf, gd->tsec2_clk));
printf(" USB DR: %-4s MHz\n", strmhz(buf, gd->usbdr_clk));
+#elif defined(CONFIG_MPC8309)
+ printf(" USB DR: %-4s MHz\n", strmhz(buf, gd->usbdr_clk));
#endif
#if defined(CONFIG_MPC834x)
printf(" USB MPH: %-4s MHz\n", strmhz(buf, gd->usbmph_clk));
#else
u32 pecr2; /* PCI Express control register 2 */
#endif
+#if defined(CONFIG_MPC8309)
+ u32 can_dbg_ctrl;
+ u32 res9a;
+ u32 gpr1;
+ u8 res9b[0xAC];
+#else
u8 res9[0xB8];
+#endif
} sysconf83xx_t;
/*
* On Chip ROM
*/
typedef struct rom83xx {
+#if defined(CONFIG_MPC8309)
+ u8 mem[0x8000];
+#else
u8 mem[0x10000];
+#endif
} rom83xx_t;
/*
u8 res8[0xC0000];
u8 qe[0x100000]; /* QE block */
} immap_t;
+#elif defined(CONFIG_MPC8309)
+typedef struct immap {
+ sysconf83xx_t sysconf; /* System configuration */
+ wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
+ rtclk83xx_t rtc; /* Real Time Clock Module Registers */
+ rtclk83xx_t pit; /* Periodic Interval Timer */
+ gtm83xx_t gtm[2]; /* Global Timers Module */
+ ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
+ arbiter83xx_t arbiter; /* System Arbiter Registers */
+ reset83xx_t reset; /* Reset Module */
+ clk83xx_t clk; /* System Clock Module */
+ pmc83xx_t pmc; /* Power Management Control Module */
+ gpio83xx_t gpio[2]; /* General purpose I/O module */
+ u8 res0[0x500]; /* res0 1.25 KBytes added for 8309 */
+ qepi83xx_t qepi; /* QE Ports Interrupts Registers */
+ qepio83xx_t qepio; /* QE Parallel I/O ports */
+ u8 res1[0x800];
+ ddr83xx_t ddr; /* DDR Memory Controller Memory */
+ fsl_i2c_t i2c[2]; /* I2C Controllers */
+ u8 res2[0x1300];
+ duart83xx_t duart[2]; /* DUART */
+ u8 res3[0x200];
+ duart83xx_t duart1[2]; /* DUART */
+ u8 res4[0x500];
+ fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
+ u8 res5[0x1000];
+ u8 spi[0x100];
+ u8 res6[0xf00];
+ dma83xx_t dma; /* DMA */
+ pciconf83xx_t pci_conf[1]; /* PCI Configuration Registers */
+ u8 res7[0x80];
+ ios83xx_t ios; /* Sequencer (IOS) */
+ pcictrl83xx_t pci_ctrl[1]; /* PCI Control & Status Registers */
+ u8 res8[0x13A00];
+ u8 can1[0x1000]; /* Flexcan 1 */
+ u8 can2[0x1000]; /* Flexcan 2 */
+ u8 res9[0x5000];
+ usb83xx_t usb;
+ u8 res10[0x5000];
+ u8 can3[0x1000]; /* Flexcan 3 */
+ u8 can4[0x1000]; /* Flexcan 4 */
+ u8 res11[0x1000];
+ u8 dma1[0x2000]; /* DMA */
+ sdhc83xx_t sdhc; /* SDHC Controller */
+ u8 res12[0xC1000];
+ rom83xx_t rom; /* On Chip ROM */
+ u8 res13[0x8000];
+ u8 qe[0x100000]; /* QE block */
+ u8 res14[0xE00000];/* Added for 8309 */
+} immap_t;
#endif
#define CONFIG_SYS_MPC83xx_DDR_OFFSET (0x2000)
* we just need to know what the SNUMs are for the threads.
*/
static u8 thread_snum[] = {
+/* Evthreads 16-29 are not supported in MPC8309 */
+#if !defined(CONFIG_MPC8309)
0x04, 0x05, 0x0c, 0x0d,
0x14, 0x15, 0x1c, 0x1d,
0x24, 0x25, 0x2c, 0x2d,
- 0x34, 0x35, 0x88, 0x89,
- 0x98, 0x99, 0xa8, 0xa9,
- 0xb8, 0xb9, 0xc8, 0xc9,
- 0xd8, 0xd9, 0xe8, 0xe9,
- 0x08, 0x09, 0x18, 0x19,
- 0x28, 0x29, 0x38, 0x39,
- 0x48, 0x49, 0x58, 0x59,
- 0x68, 0x69, 0x78, 0x79,
- 0x80, 0x81
+ 0x34, 0x35,
+#endif
+ 0x88, 0x89, 0x98, 0x99,
+ 0xa8, 0xa9, 0xb8, 0xb9,
+ 0xc8, 0xc9, 0xd8, 0xd9,
+ 0xe8, 0xe9, 0x08, 0x09,
+ 0x18, 0x19, 0x28, 0x29,
+ 0x38, 0x39, 0x48, 0x49,
+ 0x58, 0x59, 0x68, 0x69,
+ 0x78, 0x79, 0x80, 0x81
};
static void qe_snums_init(void)
#define SPR_FAMILY(spridr) ((spridr & 0xFFF00000) >> 20)
#define SPR_8308 0x8100
+#define SPR_8309 0x8110
#define SPR_831X_FAMILY 0x80B
#define SPR_8311 0x80B2
#define SPR_8313 0x80B0
#define SICRH_TSOBI1_V2P5 (1 << 1)
#define SICRH_TSOBI2_V3P3 (0 << 0)
#define SICRH_TSOBI2_V2P5 (1 << 0)
+
+#elif defined(CONFIG_MPC8309)
+/* SICR_1 */
+#define SICR_1_UART1_UART1S (0 << (30-2))
+#define SICR_1_UART1_UART1RTS (1 << (30-2))
+#define SICR_1_I2C_I2C (0 << (30-4))
+#define SICR_1_I2C_CKSTOP (1 << (30-4))
+#define SICR_1_IRQ_A_IRQ (0 << (30-6))
+#define SICR_1_IRQ_A_MCP (1 << (30-6))
+#define SICR_1_IRQ_B_IRQ (0 << (30-8))
+#define SICR_1_IRQ_B_CKSTOP (1 << (30-8))
+#define SICR_1_GPIO_A_GPIO (0 << (30-10))
+#define SICR_1_GPIO_A_SD (2 << (30-10))
+#define SICR_1_GPIO_A_DDR (3 << (30-10))
+#define SICR_1_GPIO_B_GPIO (0 << (30-12))
+#define SICR_1_GPIO_B_SD (2 << (30-12))
+#define SICR_1_GPIO_B_QE (3 << (30-12))
+#define SICR_1_GPIO_C_GPIO (0 << (30-14))
+#define SICR_1_GPIO_C_CAN (1 << (30-14))
+#define SICR_1_GPIO_C_DDR (2 << (30-14))
+#define SICR_1_GPIO_C_LCS (3 << (30-14))
+#define SICR_1_GPIO_D_GPIO (0 << (30-16))
+#define SICR_1_GPIO_D_CAN (1 << (30-16))
+#define SICR_1_GPIO_D_DDR (2 << (30-16))
+#define SICR_1_GPIO_D_LCS (3 << (30-16))
+#define SICR_1_GPIO_E_GPIO (0 << (30-18))
+#define SICR_1_GPIO_E_CAN (1 << (30-18))
+#define SICR_1_GPIO_E_DDR (2 << (30-18))
+#define SICR_1_GPIO_E_LCS (3 << (30-18))
+#define SICR_1_GPIO_F_GPIO (0 << (30-20))
+#define SICR_1_GPIO_F_CAN (1 << (30-20))
+#define SICR_1_GPIO_F_CK (2 << (30-20))
+#define SICR_1_USB_A_USBDR (0 << (30-22))
+#define SICR_1_USB_A_UART2S (1 << (30-22))
+#define SICR_1_USB_B_USBDR (0 << (30-24))
+#define SICR_1_USB_B_UART2S (1 << (30-24))
+#define SICR_1_USB_B_UART2RTS (2 << (30-24))
+#define SICR_1_USB_C_USBDR (0 << (30-26))
+#define SICR_1_USB_C_QE_EXT (3 << (30-26))
+#define SICR_1_FEC1_FEC1 (0 << (30-28))
+#define SICR_1_FEC1_GTM (1 << (30-28))
+#define SICR_1_FEC1_GPIO (2 << (30-28))
+#define SICR_1_FEC2_FEC2 (0 << (30-30))
+#define SICR_1_FEC2_GTM (1 << (30-30))
+#define SICR_1_FEC2_GPIO (2 << (30-30))
+/* SICR_2 */
+#define SICR_2_FEC3_FEC3 (0 << (30-0))
+#define SICR_2_FEC3_TMR (1 << (30-0))
+#define SICR_2_FEC3_GPIO (2 << (30-0))
+#define SICR_2_HDLC1_A_HDLC1 (0 << (30-2))
+#define SICR_2_HDLC1_A_GPIO (1 << (30-2))
+#define SICR_2_HDLC1_A_TDM1 (2 << (30-2))
+#define SICR_2_ELBC_A_LA (0 << (30-4))
+#define SICR_2_ELBC_B_LCLK (0 << (30-6))
+#define SICR_2_HDLC2_A_HDLC2 (0 << (30-8))
+#define SICR_2_HDLC2_A_GPIO (0 << (30-8))
+#define SICR_2_HDLC2_A_TDM2 (0 << (30-8))
+/* bits 10-11 unused */
+#define SICR_2_USB_D_USBDR (0 << (30-12))
+#define SICR_2_USB_D_GPIO (2 << (30-12))
+#define SICR_2_USB_D_QE_BRG (3 << (30-12))
+#define SICR_2_PCI_PCI (0 << (30-14))
+#define SICR_2_PCI_CPCI_HS (2 << (30-14))
+#define SICR_2_HDLC1_B_HDLC1 (0 << (30-16))
+#define SICR_2_HDLC1_B_GPIO (1 << (30-16))
+#define SICR_2_HDLC1_B_QE_BRG (2 << (30-16))
+#define SICR_2_HDLC1_B_TDM1 (3 << (30-16))
+#define SICR_2_HDLC1_C_HDLC1 (0 << (30-18))
+#define SICR_2_HDLC1_C_GPIO (1 << (30-18))
+#define SICR_2_HDLC1_C_TDM1 (2 << (30-18))
+#define SICR_2_HDLC2_B_HDLC2 (0 << (30-20))
+#define SICR_2_HDLC2_B_GPIO (1 << (30-20))
+#define SICR_2_HDLC2_B_QE_BRG (2 << (30-20))
+#define SICR_2_HDLC2_B_TDM2 (3 << (30-20))
+#define SICR_2_HDLC2_C_HDLC2 (0 << (30-22))
+#define SICR_2_HDLC2_C_GPIO (1 << (30-22))
+#define SICR_2_HDLC2_C_TDM2 (2 << (30-22))
+#define SICR_2_HDLC2_C_QE_BRG (3 << (30-22))
+#define SICR_2_QUIESCE_B (0 << (30-24))
+
#endif
/*
#define HRCWL_SVCOD_DIV_8 0x10000000
#define HRCWL_SVCOD_DIV_2 0x20000000
#define HRCWL_SVCOD_DIV_1 0x30000000
+#elif defined(CONFIG_MPC8309)
+
+#define HRCWL_CEVCOD 0x000000C0
+#define HRCWL_CEVCOD_SHIFT 6
+/*
+ * According to Errata MPC8309RMAD, Rev. 0.2, 9/2012
+ * these are different than with 8360, 832x
+ */
+#define HRCWL_CE_PLL_VCO_DIV_2 0x00000000
+#define HRCWL_CE_PLL_VCO_DIV_4 0x00000040
+#define HRCWL_CE_PLL_VCO_DIV_8 0x00000080
+
+#define HRCWL_CEPDF 0x00000020
+#define HRCWL_CEPDF_SHIFT 5
+#define HRCWL_CE_PLL_DIV_1X1 0x00000000
+#define HRCWL_CE_PLL_DIV_2X1 0x00000020
+
+#define HRCWL_CEPMF 0x0000001F
+#define HRCWL_CEPMF_SHIFT 0
+#define HRCWL_CE_TO_PLL_1X16_ 0x00000000
+#define HRCWL_CE_TO_PLL_1X2 0x00000002
+#define HRCWL_CE_TO_PLL_1X3 0x00000003
+#define HRCWL_CE_TO_PLL_1X4 0x00000004
+#define HRCWL_CE_TO_PLL_1X5 0x00000005
+#define HRCWL_CE_TO_PLL_1X6 0x00000006
+#define HRCWL_CE_TO_PLL_1X7 0x00000007
+#define HRCWL_CE_TO_PLL_1X8 0x00000008
+#define HRCWL_CE_TO_PLL_1X9 0x00000009
+#define HRCWL_CE_TO_PLL_1X10 0x0000000A
+#define HRCWL_CE_TO_PLL_1X11 0x0000000B
+#define HRCWL_CE_TO_PLL_1X12 0x0000000C
+#define HRCWL_CE_TO_PLL_1X13 0x0000000D
+#define HRCWL_CE_TO_PLL_1X14 0x0000000E
+#define HRCWL_CE_TO_PLL_1X15 0x0000000F
+#define HRCWL_CE_TO_PLL_1X16 0x00000010
+#define HRCWL_CE_TO_PLL_1X17 0x00000011
+#define HRCWL_CE_TO_PLL_1X18 0x00000012
+#define HRCWL_CE_TO_PLL_1X19 0x00000013
+#define HRCWL_CE_TO_PLL_1X20 0x00000014
+#define HRCWL_CE_TO_PLL_1X21 0x00000015
+#define HRCWL_CE_TO_PLL_1X22 0x00000016
+#define HRCWL_CE_TO_PLL_1X23 0x00000017
+#define HRCWL_CE_TO_PLL_1X24 0x00000018
+#define HRCWL_CE_TO_PLL_1X25 0x00000019
+#define HRCWL_CE_TO_PLL_1X26 0x0000001A
+#define HRCWL_CE_TO_PLL_1X27 0x0000001B
+#define HRCWL_CE_TO_PLL_1X28 0x0000001C
+#define HRCWL_CE_TO_PLL_1X29 0x0000001D
+#define HRCWL_CE_TO_PLL_1X30 0x0000001E
+#define HRCWL_CE_TO_PLL_1X31 0x0000001F
+
+#define HRCWL_SVCOD 0x30000000
+#define HRCWL_SVCOD_SHIFT 28
+#define HRCWL_SVCOD_DIV_2 0x00000000
+#define HRCWL_SVCOD_DIV_4 0x10000000
+#define HRCWL_SVCOD_DIV_8 0x20000000
+#define HRCWL_SVCOD_DIV_1 0x30000000
#endif
/*
#define SCCR_SATACM_1 0x00000055
#define SCCR_SATACM_2 0x000000aa
#define SCCR_SATACM_3 0x000000ff
+#elif defined(CONFIG_MPC8309)
+/* SCCR bits - MPC8309 specific */
+#define SCCR_SDHCCM 0x0c000000
+#define SCCR_SDHCCM_SHIFT 26
+#define SCCR_SDHCCM_0 0x00000000
+#define SCCR_SDHCCM_1 0x04000000
+#define SCCR_SDHCCM_2 0x08000000
+#define SCCR_SDHCCM_3 0x0c000000
+
+#define SCCR_USBDRCM 0x00c00000
+#define SCCR_USBDRCM_SHIFT 22
+#define SCCR_USBDRCM_0 0x00000000
+#define SCCR_USBDRCM_1 0x00400000
+#define SCCR_USBDRCM_2 0x00800000
+#define SCCR_USBDRCM_3 0x00c00000
#endif
#define SCCR_PCIEXP1CM 0x00300000
projects / platform / kernel / u-boot.git / commitdiff