arm64: dts: renesas: r9a07g044: Add pinctrl node

Add GPIO/pinctrl node to R9A07G044 (RZ/G2L) SoC DTSI.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210727112328.18809-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 9a7489dc70d1088276bfffa143283e9b0eb1ce56..22fa8dea08057ba6ce951858d70f4177e1257d3e 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -191,6 +191,19 @@
                        status = "disabled";
                };
 
+               pinctrl: pin-controller@11030000 {
+                       compatible = "renesas,r9a07g044-pinctrl";
+                       reg = <0 0x11030000 0 0x10000>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       gpio-ranges = <&pinctrl 0 0 392>;
+                       clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>;
+                       power-domains = <&cpg>;
+                       resets = <&cpg R9A07G044_GPIO_RSTN>,
+                                <&cpg R9A07G044_GPIO_PORT_RESETN>,
+                                <&cpg R9A07G044_GPIO_SPARE_RESETN>;
+               };
+
                gic: interrupt-controller@11900000 {
                        compatible = "arm,gic-v3";
                        #interrupt-cells = <3>;