ARM: exynos: Fix imprecise abort during Exynos5422 suspend to RAM

Suspend to RAM on Odroid XU3/XU4/HC1 family (Exynos5422) causes
imprecise abort:

	PM: Syncing filesystems ... done.
	Freezing user space processes ... (elapsed 0.003 seconds) done.
	OOM killer disabled.
	Freezing remaining freezable tasks ... (elapsed 0.003 seconds) done.
	wake enabled for irq 139
	Disabling non-boot CPUs ...
	IRQ51 no longer affine to CPU1
	IRQ52 no longer affine to CPU2
	IRQ53 no longer affine to CPU3
	IRQ54 no longer affine to CPU4
	IRQ55 no longer affine to CPU5
	IRQ56 no longer affine to CPU6
	cpu cpu4: Dropping the link to regulator.40
	IRQ57 no longer affine to CPU7
	Unhandled fault: external abort on non-linefetch (0x1008) at 0xf081a028
	Internal error: : 1008 [#1] PREEMPT SMP ARM

with last call trace in exynos_suspend_enter().

The abort is caused by writing to register in secure part of sysram.
Boards booted under secure firmware (e.g. Hardkernel Odroid boards)
should access non-secure sysram.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
[backport of mainline commit e0b35c1ab5ac5f0453d1093770e119bd8d63d85c]
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: Iaa947452e284d9df9b917e77ece381475ad717da

diff --git a/Documentation/arm/Samsung/Bootloader-interface.txt b/Documentation/arm/Samsung/Bootloader-interface.txt
index ed494ac..d17ed51 100644 (file)
--- a/Documentation/arm/Samsung/Bootloader-interface.txt
+++ b/Documentation/arm/Samsung/Bootloader-interface.txt
@@ -26,6 +26,7 @@ Offset        Value                                        Purpose
 0x20          0xfcba0d10 (Magic cookie)                    AFTR
 0x24          exynos_cpu_resume_ns                         AFTR
 0x28 + 4*cpu  0x8 (Magic cookie, Exynos3250)               AFTR
+0x28          0x0 or last value during resume (Exynos542x) System suspend
 
 
 2. Secure mode

diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 0b4d24c..8377715 100644 (file)
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -124,6 +124,7 @@ void exynos_firmware_init(void);
  */
 #define EXYNOS_AFTR_MAGIC      0xfcba0d10
 
+bool __init exynos_secure_firmware_available(void);
 void exynos_set_boot_flag(unsigned int cpu, unsigned int mode);
 void exynos_clear_boot_flag(unsigned int cpu, unsigned int mode);
 

diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
index 08947c7..1d69de4 100644 (file)
--- a/arch/arm/mach-exynos/firmware.c
+++ b/arch/arm/mach-exynos/firmware.c
@@ -190,7 +190,7 @@ static void exynos_l2_configure(const struct l2x0_regs *regs)
        exynos_smc(SMC_CMD_L2X0SETUP2, regs->pwr_ctrl, regs->aux_ctrl, 0);
 }
 
-void __init exynos_firmware_init(void)
+bool __init exynos_secure_firmware_available(void)
 {
        struct device_node *nd;
        const __be32 *addr;
@@ -198,14 +198,22 @@ void __init exynos_firmware_init(void)
        nd = of_find_compatible_node(NULL, NULL,
                                        "samsung,secure-firmware");
        if (!nd)
-               return;
+               return false;
 
        addr = of_get_address(nd, 0, NULL, NULL);
        if (!addr) {
                pr_err("%s: No address specified.\n", __func__);
-               return;
+               return false;
        }
 
+       return true;
+}
+
+void __init exynos_firmware_init(void)
+{
+       if (!exynos_secure_firmware_available())
+               return;
+
        pr_info("Running under secure firmware.\n");
 
        register_firmware_ops(&exynos_firmware_ops);

diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c
index 25fa755..1b05cb8 100644 (file)
--- a/arch/arm/mach-exynos/suspend.c
+++ b/arch/arm/mach-exynos/suspend.c
@@ -70,6 +70,7 @@ struct exynos_pm_data {
 struct exynos_pm_state {
        int cpu_state;
        unsigned int pmu_spare3;
+       void __iomem *sysram_base;
 };
 
 static const struct exynos_pm_data *pm_data __ro_after_init;
@@ -273,7 +274,7 @@ static int exynos5420_cpu_suspend(unsigned long arg)
        unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
        unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
 
-       writel_relaxed(0x0, sysram_base_addr + EXYNOS5420_CPU_STATE);
+       writel_relaxed(0x0, pm_state.sysram_base + EXYNOS5420_CPU_STATE);
 
        if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM)) {
                mcpm_set_entry_vector(cpu, cluster, exynos_cpu_resume);
@@ -347,7 +348,7 @@ static void exynos5420_pm_prepare(void)
         * needs to restore it back in case, the primary cpu fails to
         * suspend for any reason.
         */
-       pm_state.cpu_state = readl_relaxed(sysram_base_addr +
+       pm_state.cpu_state = readl_relaxed(pm_state.sysram_base +
                                           EXYNOS5420_CPU_STATE);
 
        exynos_pm_enter_sleep_mode();
@@ -467,7 +468,7 @@ static void exynos5420_pm_resume(void)
 
        /* Restore the sysram cpu state register */
        writel_relaxed(pm_state.cpu_state,
-                      sysram_base_addr + EXYNOS5420_CPU_STATE);
+                      pm_state.sysram_base + EXYNOS5420_CPU_STATE);
 
        pmu_raw_writel(EXYNOS5420_USE_STANDBY_WFI_ALL,
                        S5P_CENTRAL_SEQ_OPTION);
@@ -673,4 +674,13 @@ void __init exynos_pm_init(void)
 
        register_syscore_ops(&exynos_pm_syscore_ops);
        suspend_set_ops(&exynos_suspend_ops);
+
+       /*
+        * Applicable as of now only to Exynos542x. If booted under secure
+        * firmware, the non-secure region of sysram should be used.
+        */
+       if (exynos_secure_firmware_available())
+               pm_state.sysram_base = sysram_ns_base_addr;
+       else
+               pm_state.sysram_base = sysram_base_addr;
 }