Merge branch 'master-sync' of git://git.denx.de/u-boot-arm

diff --git a/board/amcc/kilauea/kilauea.c b/board/amcc/kilauea/kilauea.c
index 8ce2445..646f431 100644 (file)
--- a/board/amcc/kilauea/kilauea.c
+++ b/board/amcc/kilauea/kilauea.c
@@ -39,6 +39,37 @@ DECLARE_GLOBAL_DATA_PTR;
 
 extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips    */
 
+static int board_cpld_version(void)
+{
+       u32 cpld;
+
+       cpld = in_be32((void *)CONFIG_SYS_FPGA_FIFO_BASE);
+       if ((cpld & CONFIG_SYS_FPGA_MAGIC_MASK) != CONFIG_SYS_FPGA_MAGIC) {
+               /*
+                * Magic not found -> "old" CPLD revision which needs
+                * the "old" EBC configuration
+                */
+               mtebc(PB2AP, EBC_BXAP_BME_ENABLED | EBC_BXAP_FWT_ENCODE(5) |
+                     EBC_BXAP_BWT_ENCODE(0) | EBC_BXAP_BCE_DISABLE |
+                     EBC_BXAP_BCT_2TRANS | EBC_BXAP_CSN_ENCODE(0) |
+                     EBC_BXAP_OEN_ENCODE(0) | EBC_BXAP_WBN_ENCODE(3) |
+                     EBC_BXAP_WBF_ENCODE(0) | EBC_BXAP_TH_ENCODE(4) |
+                     EBC_BXAP_RE_DISABLED | EBC_BXAP_SOR_DELAYED |
+                     EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED);
+
+               /*
+                * Return 0 for "old" CPLD version
+                */
+               return 0;
+       }
+
+       /*
+        * Magic found -> "new" CPLD revision which needs no new
+        * EBC configuration
+        */
+       return (cpld & CONFIG_SYS_FPGA_VER_MASK) >> 8;
+}
+
 /*
  * Board early initialization function
  */
@@ -209,6 +240,13 @@ int board_early_init_f (void)
        mtsdr(SDR0_PFC1, val);
 
        /*
+        * The CPLD version detection has to be the first access to
+        * the CPLD, so we need to make this access this early and
+        * save the CPLD version for later.
+        */
+       gd->board_type = board_cpld_version();
+
+       /*
         * Configure FPGA register with PCIe reset
         */
        out_be32((void *)CONFIG_SYS_FPGA_BASE, 0xff570cc4);     /* assert PCIe reset */
@@ -280,7 +318,7 @@ int checkboard (void)
                puts(", serial# ");
                puts(s);
        }
-       putc('\n');
+       printf(" (CPLD rev. %ld)\n", gd->board_type);
 
        return (0);
 }

diff --git a/drivers/pci/pci_indirect.c b/drivers/pci/pci_indirect.c
index ab51f8d..2070d01 100644 (file)
--- a/drivers/pci/pci_indirect.c
+++ b/drivers/pci/pci_indirect.c
@@ -59,7 +59,8 @@ indirect_##rw##_config_##size(struct pci_controller *hose,               \
        cfg_##rw(val, hose->cfg_data + (offset & mask), type, op);       \
        return 0;                                                        \
 }
-#elif defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SPE)
+#elif defined(CONFIG_440GX)  || defined(CONFIG_440GP) || defined(CONFIG_440SP) || \
+      defined(CONFIG_440SPE) || defined(CONFIG_460EX) || defined(CONFIG_460GT)
 #define INDIRECT_PCI_OP(rw, size, type, op, mask)                       \
 static int                                                              \
 indirect_##rw##_config_##size(struct pci_controller *hose,              \

diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h
index 8d4ce8d..a79feec 100644 (file)
--- a/include/configs/kilauea.h
+++ b/include/configs/kilauea.h
@@ -47,6 +47,7 @@
 
 #define CONFIG_BOARD_EARLY_INIT_F 1            /* Call board_early_init_f */
 #define CONFIG_MISC_INIT_R     1               /* Call misc_init_r     */
+#define CONFIG_BOARD_TYPES
 #define CONFIG_BOARD_EMAC_COUNT
 
 /*-----------------------------------------------------------------------
@@ -520,9 +521,22 @@
 #define CONFIG_SYS_EBC_PB1CR           (CONFIG_SYS_NAND_ADDR | 0x1e000)
 #endif
 
-/* Memory Bank 2 (FPGA) initialization                                         */
-#define CONFIG_SYS_EBC_PB2AP           0x9400C800
-#define CONFIG_SYS_EBC_PB2CR           (CONFIG_SYS_FPGA_BASE | 0x18000)
+/* Memory Bank 2 (FPGA) initialization                                 */
+#define CONFIG_SYS_EBC_PB2AP           (EBC_BXAP_BME_ENABLED |         \
+                                        EBC_BXAP_FWT_ENCODE(6) |       \
+                                        EBC_BXAP_BWT_ENCODE(1) |       \
+                                        EBC_BXAP_BCE_DISABLE |         \
+                                        EBC_BXAP_BCT_2TRANS |          \
+                                        EBC_BXAP_CSN_ENCODE(0) |       \
+                                        EBC_BXAP_OEN_ENCODE(0) |       \
+                                        EBC_BXAP_WBN_ENCODE(3) |       \
+                                        EBC_BXAP_WBF_ENCODE(1) |       \
+                                        EBC_BXAP_TH_ENCODE(4) |        \
+                                        EBC_BXAP_RE_DISABLED |         \
+                                        EBC_BXAP_SOR_DELAYED |         \
+                                        EBC_BXAP_BEM_WRITEONLY |       \
+                                        EBC_BXAP_PEN_DISABLED)
+#define CONFIG_SYS_EBC_PB2CR   (CONFIG_SYS_FPGA_BASE | 0x18000)
 
 #define CONFIG_SYS_EBC_CFG             0x7FC00000 /*  EBC0_CFG */
 
@@ -571,7 +585,7 @@
  * Some Kilauea stuff..., mainly fpga registers
  */
 #define CONFIG_SYS_FPGA_REG_BASE               CONFIG_SYS_FPGA_BASE
-#define CONFIG_SYS_FPGA_FIFO_BASE              (in32(CONFIG_SYS_FPGA_BASE) | (1 << 10))
+#define CONFIG_SYS_FPGA_FIFO_BASE              (CONFIG_SYS_FPGA_BASE | (1 << 10))
 
 /* interrupt */
 #define CONFIG_SYS_FPGA_SLIC0_R_DPRAM_INT      0x80000000
@@ -602,4 +616,8 @@
 #define CONFIG_SYS_FPGA_USER_LED0              0x00000200
 #define CONFIG_SYS_FPGA_USER_LED1              0x00000100
 
+#define CONFIG_SYS_FPGA_MAGIC_MASK             0xffff0000
+#define CONFIG_SYS_FPGA_MAGIC                  0xabcd0000
+#define CONFIG_SYS_FPGA_VER_MASK               0x0000ff00
+
 #endif /* __CONFIG_H */