return {BaseReg, C1};
}
-static bool isZero(Register Reg, MachineRegisterInfo &MRI) {
- int64_t C;
- return mi_match(Reg, MRI, m_ICst(C)) && C == 0;
-}
-
-static unsigned extractCPol(unsigned CachePolicy) {
- return CachePolicy & AMDGPU::CPol::ALL;
-}
-
-static unsigned extractSWZ(unsigned CachePolicy) {
- return (CachePolicy >> 3) & 1;
-}
-
-
-MachineInstr *
-AMDGPURegisterBankInfo::selectStoreIntrinsic(MachineIRBuilder &B,
- MachineInstr &MI) const {
- MachineRegisterInfo &MRI = *B.getMRI();
- executeInWaterfallLoop(B, MI, MRI, {2, 4});
-
- // FIXME: DAG lowering brokenly changes opcode based on FP vs. integer.
-
- Register VData = MI.getOperand(1).getReg();
- LLT Ty = MRI.getType(VData);
-
- int EltSize = Ty.getScalarSizeInBits();
- int Size = Ty.getSizeInBits();
-
- // FIXME: Broken integer truncstore.
- if (EltSize != 32)
- report_fatal_error("unhandled intrinsic store");
-
- // FIXME: Verifier should enforce 1 MMO for these intrinsics.
- const int MemSize = (*MI.memoperands_begin())->getSize();
-
-
- Register RSrc = MI.getOperand(2).getReg();
- Register VOffset = MI.getOperand(3).getReg();
- Register SOffset = MI.getOperand(4).getReg();
- unsigned CachePolicy = MI.getOperand(5).getImm();
-
- unsigned ImmOffset;
- std::tie(VOffset, ImmOffset) = splitBufferOffsets(B, VOffset);
-
- const bool Offen = !isZero(VOffset, MRI);
-
- unsigned Opc = AMDGPU::BUFFER_STORE_DWORD_OFFEN_exact;
- switch (8 * MemSize) {
- case 8:
- Opc = Offen ? AMDGPU::BUFFER_STORE_BYTE_OFFEN_exact :
- AMDGPU::BUFFER_STORE_BYTE_OFFSET_exact;
- break;
- case 16:
- Opc = Offen ? AMDGPU::BUFFER_STORE_SHORT_OFFEN_exact :
- AMDGPU::BUFFER_STORE_SHORT_OFFSET_exact;
- break;
- default:
- Opc = Offen ? AMDGPU::BUFFER_STORE_DWORD_OFFEN_exact :
- AMDGPU::BUFFER_STORE_DWORD_OFFSET_exact;
- if (Size > 32)
- Opc = AMDGPU::getMUBUFOpcode(Opc, Size / 32);
- break;
- }
-
-
- // Set the insertion point back to the instruction in case it was moved into a
- // loop.
- B.setInstr(MI);
-
- MachineInstrBuilder MIB = B.buildInstr(Opc)
- .addUse(VData);
-
- if (Offen)
- MIB.addUse(VOffset);
-
- MIB.addUse(RSrc)
- .addUse(SOffset)
- .addImm(ImmOffset)
- .addImm(extractCPol(CachePolicy))
- .addImm(0) // tfe: FIXME: Remove from inst
- .addImm(extractSWZ(CachePolicy))
- .cloneMemRefs(MI);
-
- // FIXME: We need a way to report failure from applyMappingImpl.
- // Insert constrain copies before inserting the loop.
- if (!constrainSelectedInstRegOperands(*MIB, *TII, *TRI, *this))
- report_fatal_error("failed to constrain selected store intrinsic");
-
- return MIB;
-}
-
bool AMDGPURegisterBankInfo::buildVCopy(MachineIRBuilder &B, Register DstReg,
Register SrcReg) const {
MachineRegisterInfo &MRI = *B.getMRI();