drm: rcar-du: Write ESCR and OTAR as CRTC registers

The ESCR and OTAR registers exist in each DU channel, but at different
offsets for odd and even channels. This led to usage of the group
register access API to write them, with offsets macros named ESCR/OTAR
and ESCR2/OTAR2 for the first and second ESCR/OTAR register in the group
respectively.

The names are confusing as it suggests that the ESCR/OTAR registers for
DU0 and DU2 are taken into account, especially with writes performed to
the group register access API.

Rename the offsets to ESCR/OTAR02 and ESCR/OTAR13, and use the CRTC
register access API to clarify the code. The offsets values are updated
accordingly.

Cosmetic patch, no functional changes intended.

Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
[Squashed ESCR and OTAR changes in a single commit]
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
index 2bf63dc..6288b9a 100644 (file)
--- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
@@ -313,9 +313,8 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
 
        dev_dbg(rcrtc->group->dev->dev, "%s: ESCR 0x%08x\n", __func__, escr);
 
-       rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? ESCR2 : ESCR,
-                           escr);
-       rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? OTAR2 : OTAR, 0);
+       rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? ESCR13 : ESCR02, escr);
+       rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? OTAR13 : OTAR02, 0);
 
        /* Signal polarities */
        dsmr = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? DSMR_VSL : 0)

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_regs.h b/drivers/gpu/drm/rcar-du/rcar_du_regs.h
index f141724..bc87f08 100644 (file)
--- a/drivers/gpu/drm/rcar-du/rcar_du_regs.h
+++ b/drivers/gpu/drm/rcar-du/rcar_du_regs.h
@@ -489,8 +489,8 @@
  * External Synchronization Control Registers
  */
 
-#define ESCR                   0x10000
-#define ESCR2                  0x31000
+#define ESCR02                 0x10000
+#define ESCR13                 0x01000
 #define ESCR_DCLKOINV          (1 << 25)
 #define ESCR_DCLKSEL_DCLKIN    (0 << 20)
 #define ESCR_DCLKSEL_CLKS      (1 << 20)
@@ -501,8 +501,8 @@
 #define ESCR_SYNCSEL_EXHSYNC   (3 << 8)
 #define ESCR_FRQSEL_MASK       (0x3f << 0)
 
-#define OTAR                   0x10004
-#define OTAR2                  0x31004
+#define OTAR02                 0x10004
+#define OTAR13                 0x01004
 
 /* -----------------------------------------------------------------------------
  * Dual Display Output Control Registers