Fix tests for PR 18500 so that they will pass for big-endian ARM toolchains.

	PR gas/18500
	* gas/arm/vfpv3xd-ldr_immediate.d: Update test for big-endian ARM
	toolchains.
	* gas/arm/vfpv3-ldr_immediate.d: Likewise.
	* gas/arm/vfpv2-ldr_immediate.d: Likewise.

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index eef8931..bcd42ec 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2015-10-21  Nick Clifton  <nickc@redhat.com>
+
+       PR gas/18500
+       * gas/arm/vfpv3xd-ldr_immediate.d: Update test for big-endian ARM
+       toolchains.
+       * gas/arm/vfpv3-ldr_immediate.d: Likewise.
+       * gas/arm/vfpv2-ldr_immediate.d: Likewise.
+
 2015-10-14  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 
        * gas/s390/esa-g5.d: Use odd GPR for the second operand.

diff --git a/gas/testsuite/gas/arm/vfpv2-ldr_immediate.d b/gas/testsuite/gas/arm/vfpv2-ldr_immediate.d
index 109d443..d82ecfa 100644 (file)
--- a/gas/testsuite/gas/arm/vfpv2-ldr_immediate.d
+++ b/gas/testsuite/gas/arm/vfpv2-ldr_immediate.d
@@ -8,43 +8,43 @@ Disassembly of section \.text:
 
 0[0-9a-fx]+ .*ed9f0b00         vldr    d0, \[pc\].*
 0[0-9a-fx]+ .*ed9f0a01         vldr    s0, \[pc, #4\].*
-0[0-9a-fx]+ .*00000000         .*
-0[0-9a-fx]+ .*3fbe0000         .*
+0[0-9a-fx]+ .*[00000000|3fbe0000]      .*
+0[0-9a-fx]+ .*[3fbe0000|00000000]      .*
 0[0-9a-fx]+ .*3df00000         .*
 .*
 0[0-9a-fx]+ .*ed9f0b00         vldr    d0, \[pc\].*
 0[0-9a-fx]+ .*ed9f0a01         vldr    s0, \[pc, #4\].*
-0[0-9a-fx]+ .*00000000         .*
-0[0-9a-fx]+ .*bfc00000         .*
+0[0-9a-fx]+ .*[00000000|bfc00000]      .*
+0[0-9a-fx]+ .*[bfc00000|00000000]      .*
 0[0-9a-fx]+ .*be000000         .*
 .*
 0[0-9a-fx]+ .*ed9f0b00         vldr    d0, \[pc\].*
 0[0-9a-fx]+ .*ed9f0a01         vldr    s0, \[pc, #4\].*
-0[0-9a-fx]+ .*00000000         .*
-0[0-9a-fx]+ .*3fc00000         .*
+0[0-9a-fx]+ .*[00000000|3fc00000]      .*
+0[0-9a-fx]+ .*[3fc00000|00000000]      .*
 0[0-9a-fx]+ .*3e000000         .*
 .*
 0[0-9a-fx]+ .*ed9f0b00         vldr    d0, \[pc\].*
 0[0-9a-fx]+ .*ed9f0a01         vldr    s0, \[pc, #4\].*
-0[0-9a-fx]+ .*00000000         .*
-0[0-9a-fx]+ .*3fe08000         .*
+0[0-9a-fx]+ .*[00000000|3fe08000]      .*
+0[0-9a-fx]+ .*[3fe08000|00000000]      .*
 0[0-9a-fx]+ .*3f040000         .*
 .*
 0[0-9a-fx]+ .*ed9f0b00         vldr    d0, \[pc\].*
 0[0-9a-fx]+ .*ed9f0a01         vldr    s0, \[pc, #4\].*
-0[0-9a-fx]+ .*00000000         .*
-0[0-9a-fx]+ .*3fef0000         .*
+0[0-9a-fx]+ .*[00000000|3fef0000]      .*
+0[0-9a-fx]+ .*[3fef0000|00000000]      .*
 0[0-9a-fx]+ .*3f780000         .*
 .*
 0[0-9a-fx]+ .*ed9f0b00         vldr    d0, \[pc\].*
 0[0-9a-fx]+ .*ed9f0a01         vldr    s0, \[pc, #4\].*
-0[0-9a-fx]+ .*00000000         .*
-0[0-9a-fx]+ .*403f0000         .*
+0[0-9a-fx]+ .*[00000000|403f0000]      .*
+0[0-9a-fx]+ .*[403f0000|00000000]      .*
 0[0-9a-fx]+ .*41f80000         .*
 .*
 0[0-9a-fx]+ .*ed9f0b00         vldr    d0, \[pc\].*
 0[0-9a-fx]+ .*ed9f0a01         vldr    s0, \[pc, #4\].*
-0[0-9a-fx]+ .*00000000         .*
-0[0-9a-fx]+ .*40400000         .*
+0[0-9a-fx]+ .*[00000000|40400000]      .*
+0[0-9a-fx]+ .*[40400000|00000000]      .*
 0[0-9a-fx]+ .*42000000         .*
 #pass

diff --git a/gas/testsuite/gas/arm/vfpv3-ldr_immediate.d b/gas/testsuite/gas/arm/vfpv3-ldr_immediate.d
index 5f0e925..c7cdc7c 100644 (file)
--- a/gas/testsuite/gas/arm/vfpv3-ldr_immediate.d
+++ b/gas/testsuite/gas/arm/vfpv3-ldr_immediate.d
@@ -8,8 +8,8 @@ Disassembly of section \.text:
 
 0[0-9a-fx]+ .*ed9f0b00         vldr    d0, \[pc\].*
 0[0-9a-fx]+ .*ed9f0a01         vldr    s0, \[pc, #4\].*
-0[0-9a-fx]+ .*00000000         .*
-0[0-9a-fx]+ .*3fbe0000         .*
+0[0-9a-fx]+ .*[00000000|3fbe0000]      .*
+0[0-9a-fx]+ .*[3fbe0000|00000000]      .*
 0[0-9a-fx]+ .*3df00000         .*
 .*
 
@@ -19,8 +19,8 @@ Disassembly of section \.text:
 0[0-9a-fx]+ .*eeb40a00         (vmov\.f32|fconsts)     s0, #64.*
 0[0-9a-fx]+ .*ed9f0b00         vldr    d0, \[pc\].*
 0[0-9a-fx]+ .*ed9f0a01         vldr    s0, \[pc, #4\].*
-0[0-9a-fx]+ .*00000000         .*
-0[0-9a-fx]+ .*3fe08000         .*
+0[0-9a-fx]+ .*[00000000|3fe08000]      .*
+0[0-9a-fx]+ .*[3fe08000|00000000]      .*
 0[0-9a-fx]+ .*3f040000         .*
 .*
 0[0-9a-fx]+ .*eeb60b0f         (vmov\.f64|fconstd)     d0, #111.*
@@ -29,7 +29,7 @@ Disassembly of section \.text:
 0[0-9a-fx]+ .*eeb30a0f         (vmov\.f32|fconsts)     s0, #63.*
 0[0-9a-fx]+ .*ed9f0b00         vldr    d0, \[pc\].*
 0[0-9a-fx]+ .*ed9f0a01         vldr    s0, \[pc, #4\].*
-0[0-9a-fx]+ .*00000000         .*
-0[0-9a-fx]+ .*40400000         .*
+0[0-9a-fx]+ .*[00000000|40400000]      .*
+0[0-9a-fx]+ .*[40400000|00000000]      .*
 0[0-9a-fx]+ .*42000000         .*
 #pass

diff --git a/gas/testsuite/gas/arm/vfpv3xd-ldr_immediate.d b/gas/testsuite/gas/arm/vfpv3xd-ldr_immediate.d
index 5df3d26..6755738 100644 (file)
--- a/gas/testsuite/gas/arm/vfpv3xd-ldr_immediate.d
+++ b/gas/testsuite/gas/arm/vfpv3xd-ldr_immediate.d
@@ -8,35 +8,35 @@ Disassembly of section \.text:
 
 0[0-9a-fx]+ .*ed9f0b00         vldr    d0, \[pc\].*
 0[0-9a-fx]+ .*ed9f0a01         vldr    s0, \[pc, #4\].*
-0[0-9a-fx]+ .*00000000         .*
-0[0-9a-fx]+ .*3fbe0000         .*
+0[0-9a-fx]+ .*[00000000|3fbe0000]      .*
+0[0-9a-fx]+ .*[3fbe0000|00000000]      .*
 0[0-9a-fx]+ .*3df00000         .*
 .*
 0[0-9a-fx]+ .*ed9f0b00         vldr    d0, \[pc\].*
 0[0-9a-fx]+ .*eebc0a00         (vmov\.f32|fconsts)     s0, #192.*
-0[0-9a-fx]+ .*00000000         .*
-0[0-9a-fx]+ .*bfc00000         .*
+0[0-9a-fx]+ .*[00000000|bfc00000]      .*
+0[0-9a-fx]+ .*[bfc00000|00000000]      .*
 0[0-9a-fx]+ .*ed9f0b00         vldr    d0, \[pc\].*
 0[0-9a-fx]+ .*eeb40a00         (vmov\.f32|fconsts)     s0, #64.*
-0[0-9a-fx]+ .*00000000         .*
-0[0-9a-fx]+ .*3fc00000         .*
+0[0-9a-fx]+ .*[00000000|3fc00000]      .*
+0[0-9a-fx]+ .*[3fc00000|00000000]      .*
 0[0-9a-fx]+ .*ed9f0b00         vldr    d0, \[pc\].*
 0[0-9a-fx]+ .*ed9f0a01         vldr    s0, \[pc, #4\].*
-0[0-9a-fx]+ .*00000000         .*
-0[0-9a-fx]+ .*3fe08000         .*
+0[0-9a-fx]+ .*[00000000|3fe08000]      .*
+0[0-9a-fx]+ .*[3fe08000|00000000]      .*
 0[0-9a-fx]+ .*3f040000         .*
 .*
 0[0-9a-fx]+ .*ed9f0b00         vldr    d0, \[pc\].*
 0[0-9a-fx]+ .*eeb60a0f         (vmov\.f32|fconsts)     s0, #111.*
-0[0-9a-fx]+ .*00000000         .*
-0[0-9a-fx]+ .*3fef0000         .*
+0[0-9a-fx]+ .*[00000000|3fef0000]      .*
+0[0-9a-fx]+ .*[3fef0000|00000000]      .*
 0[0-9a-fx]+ .*ed9f0b00         vldr    d0, \[pc\].*
 0[0-9a-fx]+ .*eeb30a0f         (vmov\.f32|fconsts)     s0, #63.*
-0[0-9a-fx]+ .*00000000         .*
-0[0-9a-fx]+ .*403f0000         .*
+0[0-9a-fx]+ .*[00000000|403f0000]      .*
+0[0-9a-fx]+ .*[403f0000|00000000]      .*
 0[0-9a-fx]+ .*ed9f0b00         vldr    d0, \[pc\].*
 0[0-9a-fx]+ .*ed9f0a01         vldr    s0, \[pc, #4\].*
-0[0-9a-fx]+ .*00000000         .*
-0[0-9a-fx]+ .*40400000         .*
+0[0-9a-fx]+ .*[00000000|40400000]      .*
+0[0-9a-fx]+ .*[40400000|00000000]      .*
 0[0-9a-fx]+ .*42000000         .*
 #pass