Don't use Linux kernel internal types like u32, __u32 or __le32.
-Use target_phys_addr_t for guest physical addresses except pcibus_t
+Use hwaddr for guest physical addresses except pcibus_t
for PCI addresses. In addition, ram_addr_t is a QEMU internal address
space that maps guest RAM physical addresses into an intermediate
address space that can map to host virtual address spaces. Generally
/* Return the physical page corresponding to a virtual one. Use it
only for debugging because no protection checks are done. Return -1
if no page found. */
-target_phys_addr_t cpu_get_phys_page_debug(CPUArchState *env, target_ulong addr);
+hwaddr cpu_get_phys_page_debug(CPUArchState *env, target_ulong addr);
/* memory API */
/* CPU interfaces that are target independent. */
-#include "targphys.h"
+#include "hwaddr.h"
#ifndef NEED_CPU_H
#include "poison.h"
/* memory API */
-typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value);
-typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr);
+typedef void CPUWriteMemoryFunc(void *opaque, hwaddr addr, uint32_t value);
+typedef uint32_t CPUReadMemoryFunc(void *opaque, hwaddr addr);
void qemu_ram_remap(ram_addr_t addr, ram_addr_t length);
/* This should only be used for ram local to a device. */
ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr);
void qemu_ram_set_idstr(ram_addr_t addr, const char *name, DeviceState *dev);
-void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
+void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf,
int len, int is_write);
-static inline void cpu_physical_memory_read(target_phys_addr_t addr,
+static inline void cpu_physical_memory_read(hwaddr addr,
void *buf, int len)
{
cpu_physical_memory_rw(addr, buf, len, 0);
}
-static inline void cpu_physical_memory_write(target_phys_addr_t addr,
+static inline void cpu_physical_memory_write(hwaddr addr,
const void *buf, int len)
{
cpu_physical_memory_rw(addr, (void *)buf, len, 1);
}
-void *cpu_physical_memory_map(target_phys_addr_t addr,
- target_phys_addr_t *plen,
+void *cpu_physical_memory_map(hwaddr addr,
+ hwaddr *plen,
int is_write);
-void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len,
- int is_write, target_phys_addr_t access_len);
+void cpu_physical_memory_unmap(void *buffer, hwaddr len,
+ int is_write, hwaddr access_len);
void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque));
void cpu_unregister_map_client(void *cookie);
-bool cpu_physical_memory_is_io(target_phys_addr_t phys_addr);
+bool cpu_physical_memory_is_io(hwaddr phys_addr);
/* Coalesced MMIO regions are areas where write operations can be reordered.
* This usually implies that write operations are side-effect free. This allows
*/
void qemu_flush_coalesced_mmio_buffer(void);
-uint32_t ldub_phys(target_phys_addr_t addr);
-uint32_t lduw_le_phys(target_phys_addr_t addr);
-uint32_t lduw_be_phys(target_phys_addr_t addr);
-uint32_t ldl_le_phys(target_phys_addr_t addr);
-uint32_t ldl_be_phys(target_phys_addr_t addr);
-uint64_t ldq_le_phys(target_phys_addr_t addr);
-uint64_t ldq_be_phys(target_phys_addr_t addr);
-void stb_phys(target_phys_addr_t addr, uint32_t val);
-void stw_le_phys(target_phys_addr_t addr, uint32_t val);
-void stw_be_phys(target_phys_addr_t addr, uint32_t val);
-void stl_le_phys(target_phys_addr_t addr, uint32_t val);
-void stl_be_phys(target_phys_addr_t addr, uint32_t val);
-void stq_le_phys(target_phys_addr_t addr, uint64_t val);
-void stq_be_phys(target_phys_addr_t addr, uint64_t val);
+uint32_t ldub_phys(hwaddr addr);
+uint32_t lduw_le_phys(hwaddr addr);
+uint32_t lduw_be_phys(hwaddr addr);
+uint32_t ldl_le_phys(hwaddr addr);
+uint32_t ldl_be_phys(hwaddr addr);
+uint64_t ldq_le_phys(hwaddr addr);
+uint64_t ldq_be_phys(hwaddr addr);
+void stb_phys(hwaddr addr, uint32_t val);
+void stw_le_phys(hwaddr addr, uint32_t val);
+void stw_be_phys(hwaddr addr, uint32_t val);
+void stl_le_phys(hwaddr addr, uint32_t val);
+void stl_be_phys(hwaddr addr, uint32_t val);
+void stq_le_phys(hwaddr addr, uint64_t val);
+void stq_be_phys(hwaddr addr, uint64_t val);
#ifdef NEED_CPU_H
-uint32_t lduw_phys(target_phys_addr_t addr);
-uint32_t ldl_phys(target_phys_addr_t addr);
-uint64_t ldq_phys(target_phys_addr_t addr);
-void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val);
-void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val);
-void stw_phys(target_phys_addr_t addr, uint32_t val);
-void stl_phys(target_phys_addr_t addr, uint32_t val);
-void stq_phys(target_phys_addr_t addr, uint64_t val);
+uint32_t lduw_phys(hwaddr addr);
+uint32_t ldl_phys(hwaddr addr);
+uint64_t ldq_phys(hwaddr addr);
+void stl_phys_notdirty(hwaddr addr, uint32_t val);
+void stq_phys_notdirty(hwaddr addr, uint64_t val);
+void stw_phys(hwaddr addr, uint32_t val);
+void stl_phys(hwaddr addr, uint32_t val);
+void stq_phys(hwaddr addr, uint64_t val);
#endif
-void cpu_physical_memory_write_rom(target_phys_addr_t addr,
+void cpu_physical_memory_write_rom(hwaddr addr,
const uint8_t *buf, int len);
extern struct MemoryRegion io_mem_ram;
#include <signal.h>
#include "osdep.h"
#include "qemu-queue.h"
-#include "targphys.h"
+#include "hwaddr.h"
#ifndef TARGET_LONG_BITS
#error TARGET_LONG_BITS must be defined before including this header
#define CPU_COMMON_TLB \
/* The meaning of the MMU modes is defined in the target code. */ \
CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \
- target_phys_addr_t iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \
+ hwaddr iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \
target_ulong tlb_flush_addr; \
target_ulong tlb_flush_mask;
is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the
supplied size is only used by tlb_flush_page. */
void tlb_set_page(CPUArchState *env, target_ulong vaddr,
- target_phys_addr_t paddr, int prot,
+ hwaddr paddr, int prot,
int mmu_idx, target_ulong size)
{
MemoryRegionSection *section;
target_ulong code_address;
uintptr_t addend;
CPUTLBEntry *te;
- target_phys_addr_t iotlb;
+ hwaddr iotlb;
assert(size >= TARGET_PAGE_SIZE);
if (size != TARGET_PAGE_SIZE) {
void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry, uintptr_t start,
uintptr_t length);
MemoryRegionSection *phys_page_find(struct AddressSpaceDispatch *d,
- target_phys_addr_t index);
+ hwaddr index);
void cpu_tlb_reset_dirty_all(ram_addr_t start1, ram_addr_t length);
void tlb_set_dirty(CPUArchState *env, target_ulong vaddr);
extern int tlb_flush_count;
/* exec.c */
void tb_flush_jmp_cache(CPUArchState *env, target_ulong addr);
-target_phys_addr_t memory_region_section_get_iotlb(CPUArchState *env,
+hwaddr memory_region_section_get_iotlb(CPUArchState *env,
MemoryRegionSection *section,
target_ulong vaddr,
- target_phys_addr_t paddr,
+ hwaddr paddr,
int prot,
target_ulong *address);
bool memory_region_is_unassigned(MemoryRegion *mr);
#if defined(CONFIG_USER_ONLY)
typedef const char *(*lookup_symbol_t)(struct syminfo *s, target_ulong orig_addr);
#else
-typedef const char *(*lookup_symbol_t)(struct syminfo *s, target_phys_addr_t orig_addr);
+typedef const char *(*lookup_symbol_t)(struct syminfo *s, hwaddr orig_addr);
#endif
struct syminfo {
bool iommu_dma_memory_valid(DMAContext *dma, dma_addr_t addr, dma_addr_t len,
DMADirection dir)
{
- target_phys_addr_t paddr, plen;
+ hwaddr paddr, plen;
#ifdef DEBUG_IOMMU
fprintf(stderr, "dma_memory_check context=%p addr=0x" DMA_ADDR_FMT
int iommu_dma_memory_rw(DMAContext *dma, dma_addr_t addr,
void *buf, dma_addr_t len, DMADirection dir)
{
- target_phys_addr_t paddr, plen;
+ hwaddr paddr, plen;
int err;
#ifdef DEBUG_IOMMU
int iommu_dma_memory_set(DMAContext *dma, dma_addr_t addr, uint8_t c,
dma_addr_t len)
{
- target_phys_addr_t paddr, plen;
+ hwaddr paddr, plen;
int err;
#ifdef DEBUG_IOMMU
DMADirection dir)
{
int err;
- target_phys_addr_t paddr, plen;
+ hwaddr paddr, plen;
void *buf;
if (dma->map) {
typedef int DMATranslateFunc(DMAContext *dma,
dma_addr_t addr,
- target_phys_addr_t *paddr,
- target_phys_addr_t *len,
+ hwaddr *paddr,
+ hwaddr *len,
DMADirection dir);
typedef void* DMAMapFunc(DMAContext *dma,
dma_addr_t addr,
DMADirection dir)
{
if (!dma_has_iommu(dma)) {
- target_phys_addr_t xlen = *len;
+ hwaddr xlen = *len;
void *p;
p = address_space_map(dma->as, addr, &xlen, dir == DMA_DIRECTION_FROM_DEVICE);
DMADirection dir, dma_addr_t access_len)
{
if (!dma_has_iommu(dma)) {
- address_space_unmap(dma->as, buffer, (target_phys_addr_t)len,
+ address_space_unmap(dma->as, buffer, (hwaddr)len,
dir == DMA_DIRECTION_FROM_DEVICE, access_len);
} else {
iommu_dma_memory_unmap(dma, buffer, len, dir, access_len);
#include "elf.h"
#include "cpu.h"
#include "cpu-all.h"
-#include "targphys.h"
+#include "hwaddr.h"
#include "monitor.h"
#include "kvm.h"
#include "dump.h"
bool have_section;
bool resume;
size_t note_size;
- target_phys_addr_t memory_offset;
+ hwaddr memory_offset;
int fd;
RAMBlock *block;
}
static int write_elf64_load(DumpState *s, MemoryMapping *memory_mapping,
- int phdr_index, target_phys_addr_t offset)
+ int phdr_index, hwaddr offset)
{
Elf64_Phdr phdr;
int ret;
}
static int write_elf32_load(DumpState *s, MemoryMapping *memory_mapping,
- int phdr_index, target_phys_addr_t offset)
+ int phdr_index, hwaddr offset)
{
Elf32_Phdr phdr;
int ret;
{
Elf64_Phdr phdr;
int endian = s->dump_info.d_endian;
- target_phys_addr_t begin = s->memory_offset - s->note_size;
+ hwaddr begin = s->memory_offset - s->note_size;
int ret;
memset(&phdr, 0, sizeof(Elf64_Phdr));
static int write_elf32_note(DumpState *s)
{
- target_phys_addr_t begin = s->memory_offset - s->note_size;
+ hwaddr begin = s->memory_offset - s->note_size;
Elf32_Phdr phdr;
int endian = s->dump_info.d_endian;
int ret;
}
/* get the memory's offset in the vmcore */
-static target_phys_addr_t get_offset(target_phys_addr_t phys_addr,
+static hwaddr get_offset(hwaddr phys_addr,
DumpState *s)
{
RAMBlock *block;
- target_phys_addr_t offset = s->memory_offset;
+ hwaddr offset = s->memory_offset;
int64_t size_in_block, start;
if (s->has_filter) {
static int write_elf_loads(DumpState *s)
{
- target_phys_addr_t offset;
+ hwaddr offset;
MemoryMapping *memory_mapping;
uint32_t phdr_index = 1;
int ret;
void tlb_flush_page(CPUArchState *env, target_ulong addr);
void tlb_flush(CPUArchState *env, int flush_global);
void tlb_set_page(CPUArchState *env, target_ulong vaddr,
- target_phys_addr_t paddr, int prot,
+ hwaddr paddr, int prot,
int mmu_idx, target_ulong size);
-void tb_invalidate_phys_addr(target_phys_addr_t addr);
+void tb_invalidate_phys_addr(hwaddr addr);
#else
static inline void tlb_flush_page(CPUArchState *env, target_ulong addr)
{
#if !defined(CONFIG_USER_ONLY)
-struct MemoryRegion *iotlb_to_region(target_phys_addr_t index);
-uint64_t io_mem_read(struct MemoryRegion *mr, target_phys_addr_t addr,
+struct MemoryRegion *iotlb_to_region(hwaddr index);
+uint64_t io_mem_read(struct MemoryRegion *mr, hwaddr addr,
unsigned size);
-void io_mem_write(struct MemoryRegion *mr, target_phys_addr_t addr,
+void io_mem_write(struct MemoryRegion *mr, hwaddr addr,
uint64_t value, unsigned size);
void tlb_fill(CPUArchState *env1, target_ulong addr, int is_write, int mmu_idx,
}
-static void phys_page_set_level(PhysPageEntry *lp, target_phys_addr_t *index,
- target_phys_addr_t *nb, uint16_t leaf,
+static void phys_page_set_level(PhysPageEntry *lp, hwaddr *index,
+ hwaddr *nb, uint16_t leaf,
int level)
{
PhysPageEntry *p;
int i;
- target_phys_addr_t step = (target_phys_addr_t)1 << (level * L2_BITS);
+ hwaddr step = (hwaddr)1 << (level * L2_BITS);
if (!lp->is_leaf && lp->ptr == PHYS_MAP_NODE_NIL) {
lp->ptr = phys_map_node_alloc();
}
static void phys_page_set(AddressSpaceDispatch *d,
- target_phys_addr_t index, target_phys_addr_t nb,
+ hwaddr index, hwaddr nb,
uint16_t leaf)
{
/* Wildly overreserve - it doesn't matter much. */
phys_page_set_level(&d->phys_map, &index, &nb, leaf, P_L2_LEVELS - 1);
}
-MemoryRegionSection *phys_page_find(AddressSpaceDispatch *d, target_phys_addr_t index)
+MemoryRegionSection *phys_page_find(AddressSpaceDispatch *d, hwaddr index)
{
PhysPageEntry lp = d->phys_map;
PhysPageEntry *p;
tb_invalidate_phys_page_range(pc, pc + 1, 0);
}
#else
-void tb_invalidate_phys_addr(target_phys_addr_t addr)
+void tb_invalidate_phys_addr(hwaddr addr)
{
ram_addr_t ram_addr;
MemoryRegionSection *section;
return ret;
}
-target_phys_addr_t memory_region_section_get_iotlb(CPUArchState *env,
+hwaddr memory_region_section_get_iotlb(CPUArchState *env,
MemoryRegionSection *section,
target_ulong vaddr,
- target_phys_addr_t paddr,
+ hwaddr paddr,
int prot,
target_ulong *address)
{
- target_phys_addr_t iotlb;
+ hwaddr iotlb;
CPUWatchpoint *wp;
if (memory_region_is_ram(section->mr)) {
#define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
typedef struct subpage_t {
MemoryRegion iomem;
- target_phys_addr_t base;
+ hwaddr base;
uint16_t sub_section[TARGET_PAGE_SIZE];
} subpage_t;
static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
uint16_t section);
-static subpage_t *subpage_init(target_phys_addr_t base);
+static subpage_t *subpage_init(hwaddr base);
static void destroy_page_desc(uint16_t section_index)
{
MemoryRegionSection *section = &phys_sections[section_index];
static void register_subpage(AddressSpaceDispatch *d, MemoryRegionSection *section)
{
subpage_t *subpage;
- target_phys_addr_t base = section->offset_within_address_space
+ hwaddr base = section->offset_within_address_space
& TARGET_PAGE_MASK;
MemoryRegionSection *existing = phys_page_find(d, base >> TARGET_PAGE_BITS);
MemoryRegionSection subsection = {
.offset_within_address_space = base,
.size = TARGET_PAGE_SIZE,
};
- target_phys_addr_t start, end;
+ hwaddr start, end;
assert(existing->mr->subpage || existing->mr == &io_mem_unassigned);
static void register_multipage(AddressSpaceDispatch *d, MemoryRegionSection *section)
{
- target_phys_addr_t start_addr = section->offset_within_address_space;
+ hwaddr start_addr = section->offset_within_address_space;
ram_addr_t size = section->size;
- target_phys_addr_t addr;
+ hwaddr addr;
uint16_t section_index = phys_section_add(section);
assert(size);
return ram_addr;
}
-static uint64_t unassigned_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t unassigned_mem_read(void *opaque, hwaddr addr,
unsigned size)
{
#ifdef DEBUG_UNASSIGNED
return 0;
}
-static void unassigned_mem_write(void *opaque, target_phys_addr_t addr,
+static void unassigned_mem_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
#ifdef DEBUG_UNASSIGNED
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static uint64_t error_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t error_mem_read(void *opaque, hwaddr addr,
unsigned size)
{
abort();
}
-static void error_mem_write(void *opaque, target_phys_addr_t addr,
+static void error_mem_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
abort();
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static void notdirty_mem_write(void *opaque, target_phys_addr_t ram_addr,
+static void notdirty_mem_write(void *opaque, hwaddr ram_addr,
uint64_t val, unsigned size)
{
int dirty_flags;
/* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
so these check for a hit then pass through to the normal out-of-line
phys routines. */
-static uint64_t watch_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t watch_mem_read(void *opaque, hwaddr addr,
unsigned size)
{
check_watchpoint(addr & ~TARGET_PAGE_MASK, ~(size - 1), BP_MEM_READ);
}
}
-static void watch_mem_write(void *opaque, target_phys_addr_t addr,
+static void watch_mem_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
check_watchpoint(addr & ~TARGET_PAGE_MASK, ~(size - 1), BP_MEM_WRITE);
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static uint64_t subpage_read(void *opaque, target_phys_addr_t addr,
+static uint64_t subpage_read(void *opaque, hwaddr addr,
unsigned len)
{
subpage_t *mmio = opaque;
return io_mem_read(section->mr, addr, len);
}
-static void subpage_write(void *opaque, target_phys_addr_t addr,
+static void subpage_write(void *opaque, hwaddr addr,
uint64_t value, unsigned len)
{
subpage_t *mmio = opaque;
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static uint64_t subpage_ram_read(void *opaque, target_phys_addr_t addr,
+static uint64_t subpage_ram_read(void *opaque, hwaddr addr,
unsigned size)
{
ram_addr_t raddr = addr;
}
}
-static void subpage_ram_write(void *opaque, target_phys_addr_t addr,
+static void subpage_ram_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
ram_addr_t raddr = addr;
return 0;
}
-static subpage_t *subpage_init(target_phys_addr_t base)
+static subpage_t *subpage_init(hwaddr base)
{
subpage_t *mmio;
return phys_section_add(§ion);
}
-MemoryRegion *iotlb_to_region(target_phys_addr_t index)
+MemoryRegion *iotlb_to_region(hwaddr index)
{
return phys_sections[index & ~TARGET_PAGE_MASK].mr;
}
#else
-static void invalidate_and_set_dirty(target_phys_addr_t addr,
- target_phys_addr_t length)
+static void invalidate_and_set_dirty(hwaddr addr,
+ hwaddr length)
{
if (!cpu_physical_memory_is_dirty(addr)) {
/* invalidate code */
xen_modified_memory(addr, length);
}
-void address_space_rw(AddressSpace *as, target_phys_addr_t addr, uint8_t *buf,
+void address_space_rw(AddressSpace *as, hwaddr addr, uint8_t *buf,
int len, bool is_write)
{
AddressSpaceDispatch *d = as->dispatch;
int l;
uint8_t *ptr;
uint32_t val;
- target_phys_addr_t page;
+ hwaddr page;
MemoryRegionSection *section;
while (len > 0) {
if (is_write) {
if (!memory_region_is_ram(section->mr)) {
- target_phys_addr_t addr1;
+ hwaddr addr1;
addr1 = memory_region_section_addr(section, addr);
/* XXX: could force cpu_single_env to NULL to avoid
potential bugs */
} else {
if (!(memory_region_is_ram(section->mr) ||
memory_region_is_romd(section->mr))) {
- target_phys_addr_t addr1;
+ hwaddr addr1;
/* I/O case */
addr1 = memory_region_section_addr(section, addr);
if (l >= 4 && ((addr1 & 3) == 0)) {
}
}
-void address_space_write(AddressSpace *as, target_phys_addr_t addr,
+void address_space_write(AddressSpace *as, hwaddr addr,
const uint8_t *buf, int len)
{
address_space_rw(as, addr, (uint8_t *)buf, len, true);
* @addr: address within that address space
* @buf: buffer with the data transferred
*/
-void address_space_read(AddressSpace *as, target_phys_addr_t addr, uint8_t *buf, int len)
+void address_space_read(AddressSpace *as, hwaddr addr, uint8_t *buf, int len)
{
address_space_rw(as, addr, buf, len, false);
}
-void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
+void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf,
int len, int is_write)
{
return address_space_rw(&address_space_memory, addr, buf, len, is_write);
}
/* used for ROM loading : can write in RAM and ROM */
-void cpu_physical_memory_write_rom(target_phys_addr_t addr,
+void cpu_physical_memory_write_rom(hwaddr addr,
const uint8_t *buf, int len)
{
AddressSpaceDispatch *d = address_space_memory.dispatch;
int l;
uint8_t *ptr;
- target_phys_addr_t page;
+ hwaddr page;
MemoryRegionSection *section;
while (len > 0) {
typedef struct {
void *buffer;
- target_phys_addr_t addr;
- target_phys_addr_t len;
+ hwaddr addr;
+ hwaddr len;
} BounceBuffer;
static BounceBuffer bounce;
* likely to succeed.
*/
void *address_space_map(AddressSpace *as,
- target_phys_addr_t addr,
- target_phys_addr_t *plen,
+ hwaddr addr,
+ hwaddr *plen,
bool is_write)
{
AddressSpaceDispatch *d = as->dispatch;
- target_phys_addr_t len = *plen;
- target_phys_addr_t todo = 0;
+ hwaddr len = *plen;
+ hwaddr todo = 0;
int l;
- target_phys_addr_t page;
+ hwaddr page;
MemoryRegionSection *section;
ram_addr_t raddr = RAM_ADDR_MAX;
ram_addr_t rlen;
* Will also mark the memory as dirty if is_write == 1. access_len gives
* the amount of memory that was actually read or written by the caller.
*/
-void address_space_unmap(AddressSpace *as, void *buffer, target_phys_addr_t len,
- int is_write, target_phys_addr_t access_len)
+void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len,
+ int is_write, hwaddr access_len)
{
if (buffer != bounce.buffer) {
if (is_write) {
cpu_notify_map_clients();
}
-void *cpu_physical_memory_map(target_phys_addr_t addr,
- target_phys_addr_t *plen,
+void *cpu_physical_memory_map(hwaddr addr,
+ hwaddr *plen,
int is_write)
{
return address_space_map(&address_space_memory, addr, plen, is_write);
}
-void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len,
- int is_write, target_phys_addr_t access_len)
+void cpu_physical_memory_unmap(void *buffer, hwaddr len,
+ int is_write, hwaddr access_len)
{
return address_space_unmap(&address_space_memory, buffer, len, is_write, access_len);
}
/* warning: addr must be aligned */
-static inline uint32_t ldl_phys_internal(target_phys_addr_t addr,
+static inline uint32_t ldl_phys_internal(hwaddr addr,
enum device_endian endian)
{
uint8_t *ptr;
return val;
}
-uint32_t ldl_phys(target_phys_addr_t addr)
+uint32_t ldl_phys(hwaddr addr)
{
return ldl_phys_internal(addr, DEVICE_NATIVE_ENDIAN);
}
-uint32_t ldl_le_phys(target_phys_addr_t addr)
+uint32_t ldl_le_phys(hwaddr addr)
{
return ldl_phys_internal(addr, DEVICE_LITTLE_ENDIAN);
}
-uint32_t ldl_be_phys(target_phys_addr_t addr)
+uint32_t ldl_be_phys(hwaddr addr)
{
return ldl_phys_internal(addr, DEVICE_BIG_ENDIAN);
}
/* warning: addr must be aligned */
-static inline uint64_t ldq_phys_internal(target_phys_addr_t addr,
+static inline uint64_t ldq_phys_internal(hwaddr addr,
enum device_endian endian)
{
uint8_t *ptr;
return val;
}
-uint64_t ldq_phys(target_phys_addr_t addr)
+uint64_t ldq_phys(hwaddr addr)
{
return ldq_phys_internal(addr, DEVICE_NATIVE_ENDIAN);
}
-uint64_t ldq_le_phys(target_phys_addr_t addr)
+uint64_t ldq_le_phys(hwaddr addr)
{
return ldq_phys_internal(addr, DEVICE_LITTLE_ENDIAN);
}
-uint64_t ldq_be_phys(target_phys_addr_t addr)
+uint64_t ldq_be_phys(hwaddr addr)
{
return ldq_phys_internal(addr, DEVICE_BIG_ENDIAN);
}
/* XXX: optimize */
-uint32_t ldub_phys(target_phys_addr_t addr)
+uint32_t ldub_phys(hwaddr addr)
{
uint8_t val;
cpu_physical_memory_read(addr, &val, 1);
}
/* warning: addr must be aligned */
-static inline uint32_t lduw_phys_internal(target_phys_addr_t addr,
+static inline uint32_t lduw_phys_internal(hwaddr addr,
enum device_endian endian)
{
uint8_t *ptr;
return val;
}
-uint32_t lduw_phys(target_phys_addr_t addr)
+uint32_t lduw_phys(hwaddr addr)
{
return lduw_phys_internal(addr, DEVICE_NATIVE_ENDIAN);
}
-uint32_t lduw_le_phys(target_phys_addr_t addr)
+uint32_t lduw_le_phys(hwaddr addr)
{
return lduw_phys_internal(addr, DEVICE_LITTLE_ENDIAN);
}
-uint32_t lduw_be_phys(target_phys_addr_t addr)
+uint32_t lduw_be_phys(hwaddr addr)
{
return lduw_phys_internal(addr, DEVICE_BIG_ENDIAN);
}
/* warning: addr must be aligned. The ram page is not masked as dirty
and the code inside is not invalidated. It is useful if the dirty
bits are used to track modified PTEs */
-void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val)
+void stl_phys_notdirty(hwaddr addr, uint32_t val)
{
uint8_t *ptr;
MemoryRegionSection *section;
}
}
-void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val)
+void stq_phys_notdirty(hwaddr addr, uint64_t val)
{
uint8_t *ptr;
MemoryRegionSection *section;
}
/* warning: addr must be aligned */
-static inline void stl_phys_internal(target_phys_addr_t addr, uint32_t val,
+static inline void stl_phys_internal(hwaddr addr, uint32_t val,
enum device_endian endian)
{
uint8_t *ptr;
}
}
-void stl_phys(target_phys_addr_t addr, uint32_t val)
+void stl_phys(hwaddr addr, uint32_t val)
{
stl_phys_internal(addr, val, DEVICE_NATIVE_ENDIAN);
}
-void stl_le_phys(target_phys_addr_t addr, uint32_t val)
+void stl_le_phys(hwaddr addr, uint32_t val)
{
stl_phys_internal(addr, val, DEVICE_LITTLE_ENDIAN);
}
-void stl_be_phys(target_phys_addr_t addr, uint32_t val)
+void stl_be_phys(hwaddr addr, uint32_t val)
{
stl_phys_internal(addr, val, DEVICE_BIG_ENDIAN);
}
/* XXX: optimize */
-void stb_phys(target_phys_addr_t addr, uint32_t val)
+void stb_phys(hwaddr addr, uint32_t val)
{
uint8_t v = val;
cpu_physical_memory_write(addr, &v, 1);
}
/* warning: addr must be aligned */
-static inline void stw_phys_internal(target_phys_addr_t addr, uint32_t val,
+static inline void stw_phys_internal(hwaddr addr, uint32_t val,
enum device_endian endian)
{
uint8_t *ptr;
}
}
-void stw_phys(target_phys_addr_t addr, uint32_t val)
+void stw_phys(hwaddr addr, uint32_t val)
{
stw_phys_internal(addr, val, DEVICE_NATIVE_ENDIAN);
}
-void stw_le_phys(target_phys_addr_t addr, uint32_t val)
+void stw_le_phys(hwaddr addr, uint32_t val)
{
stw_phys_internal(addr, val, DEVICE_LITTLE_ENDIAN);
}
-void stw_be_phys(target_phys_addr_t addr, uint32_t val)
+void stw_be_phys(hwaddr addr, uint32_t val)
{
stw_phys_internal(addr, val, DEVICE_BIG_ENDIAN);
}
/* XXX: optimize */
-void stq_phys(target_phys_addr_t addr, uint64_t val)
+void stq_phys(hwaddr addr, uint64_t val)
{
val = tswap64(val);
cpu_physical_memory_write(addr, &val, 8);
}
-void stq_le_phys(target_phys_addr_t addr, uint64_t val)
+void stq_le_phys(hwaddr addr, uint64_t val)
{
val = cpu_to_le64(val);
cpu_physical_memory_write(addr, &val, 8);
}
-void stq_be_phys(target_phys_addr_t addr, uint64_t val)
+void stq_be_phys(hwaddr addr, uint64_t val)
{
val = cpu_to_be64(val);
cpu_physical_memory_write(addr, &val, 8);
uint8_t *buf, int len, int is_write)
{
int l;
- target_phys_addr_t phys_addr;
+ hwaddr phys_addr;
target_ulong page;
while (len > 0) {
#endif
#ifndef CONFIG_USER_ONLY
-bool cpu_physical_memory_is_io(target_phys_addr_t phys_addr)
+bool cpu_physical_memory_is_io(hwaddr phys_addr)
{
MemoryRegionSection *section;
uint32_t num_irq;
} a9mp_priv_state;
-static uint64_t a9_scu_read(void *opaque, target_phys_addr_t offset,
+static uint64_t a9_scu_read(void *opaque, hwaddr offset,
unsigned size)
{
a9mp_priv_state *s = (a9mp_priv_state *)opaque;
}
}
-static void a9_scu_write(void *opaque, target_phys_addr_t offset,
+static void a9_scu_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
a9mp_priv_state *s = (a9mp_priv_state *)opaque;
/* PCI IO reads/writes, to byte-word addressable memory. */
/* ??? Doesn't handle multiple PCI busses. */
-static uint64_t bw_io_read(void *opaque, target_phys_addr_t addr, unsigned size)
+static uint64_t bw_io_read(void *opaque, hwaddr addr, unsigned size)
{
switch (size) {
case 1:
abort();
}
-static void bw_io_write(void *opaque, target_phys_addr_t addr,
+static void bw_io_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
switch (size) {
};
/* PCI config space reads/writes, to byte-word addressable memory. */
-static uint64_t bw_conf1_read(void *opaque, target_phys_addr_t addr,
+static uint64_t bw_conf1_read(void *opaque, hwaddr addr,
unsigned size)
{
PCIBus *b = opaque;
return pci_data_read(b, addr, size);
}
-static void bw_conf1_write(void *opaque, target_phys_addr_t addr,
+static void bw_conf1_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
PCIBus *b = opaque;
/* PCI/EISA Interrupt Acknowledge Cycle. */
-static uint64_t iack_read(void *opaque, target_phys_addr_t addr, unsigned size)
+static uint64_t iack_read(void *opaque, hwaddr addr, unsigned size)
{
return pic_read_irq(isa_pic);
}
-static void special_write(void *opaque, target_phys_addr_t addr,
+static void special_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
qemu_log("pci: special write cycle");
}
}
-static uint64_t cchip_read(void *opaque, target_phys_addr_t addr, unsigned size)
+static uint64_t cchip_read(void *opaque, hwaddr addr, unsigned size)
{
CPUAlphaState *env = cpu_single_env;
TyphoonState *s = opaque;
return ret;
}
-static uint64_t dchip_read(void *opaque, target_phys_addr_t addr, unsigned size)
+static uint64_t dchip_read(void *opaque, hwaddr addr, unsigned size)
{
/* Skip this. It's all related to DRAM timing and setup. */
return 0;
}
-static uint64_t pchip_read(void *opaque, target_phys_addr_t addr, unsigned size)
+static uint64_t pchip_read(void *opaque, hwaddr addr, unsigned size)
{
TyphoonState *s = opaque;
uint64_t ret = 0;
return ret;
}
-static void cchip_write(void *opaque, target_phys_addr_t addr,
+static void cchip_write(void *opaque, hwaddr addr,
uint64_t v32, unsigned size)
{
TyphoonState *s = opaque;
}
}
-static void dchip_write(void *opaque, target_phys_addr_t addr,
+static void dchip_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
/* Skip this. It's all related to DRAM timing and setup. */
}
-static void pchip_write(void *opaque, target_phys_addr_t addr,
+static void pchip_write(void *opaque, hwaddr addr,
uint64_t v32, unsigned size)
{
TyphoonState *s = opaque;
CPUM68KState *env;
int kernel_size;
uint64_t elf_entry;
- target_phys_addr_t entry;
+ hwaddr entry;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *sram = g_new(MemoryRegion, 1);
static void pci_apb_set_irq(void *opaque, int irq_num, int level);
-static void apb_config_writel (void *opaque, target_phys_addr_t addr,
+static void apb_config_writel (void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
APBState *s = opaque;
}
static uint64_t apb_config_readl (void *opaque,
- target_phys_addr_t addr, unsigned size)
+ hwaddr addr, unsigned size)
{
APBState *s = opaque;
uint32_t val;
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static void apb_pci_config_write(void *opaque, target_phys_addr_t addr,
+static void apb_pci_config_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
APBState *s = opaque;
pci_data_write(s->bus, addr, val, size);
}
-static uint64_t apb_pci_config_read(void *opaque, target_phys_addr_t addr,
+static uint64_t apb_pci_config_read(void *opaque, hwaddr addr,
unsigned size)
{
uint32_t ret;
return ret;
}
-static void pci_apb_iowriteb (void *opaque, target_phys_addr_t addr,
+static void pci_apb_iowriteb (void *opaque, hwaddr addr,
uint32_t val)
{
cpu_outb(addr & IOPORTS_MASK, val);
}
-static void pci_apb_iowritew (void *opaque, target_phys_addr_t addr,
+static void pci_apb_iowritew (void *opaque, hwaddr addr,
uint32_t val)
{
cpu_outw(addr & IOPORTS_MASK, bswap16(val));
}
-static void pci_apb_iowritel (void *opaque, target_phys_addr_t addr,
+static void pci_apb_iowritel (void *opaque, hwaddr addr,
uint32_t val)
{
cpu_outl(addr & IOPORTS_MASK, bswap32(val));
}
-static uint32_t pci_apb_ioreadb (void *opaque, target_phys_addr_t addr)
+static uint32_t pci_apb_ioreadb (void *opaque, hwaddr addr)
{
uint32_t val;
return val;
}
-static uint32_t pci_apb_ioreadw (void *opaque, target_phys_addr_t addr)
+static uint32_t pci_apb_ioreadw (void *opaque, hwaddr addr)
{
uint32_t val;
return val;
}
-static uint32_t pci_apb_ioreadl (void *opaque, target_phys_addr_t addr)
+static uint32_t pci_apb_ioreadl (void *opaque, hwaddr addr)
{
uint32_t val;
return 0;
}
-PCIBus *pci_apb_init(target_phys_addr_t special_base,
- target_phys_addr_t mem_base,
+PCIBus *pci_apb_init(hwaddr special_base,
+ hwaddr mem_base,
qemu_irq *ivec_irqs, PCIBus **bus2, PCIBus **bus3,
qemu_irq **pbm_irqs)
{
#include "qemu-common.h"
-PCIBus *pci_apb_init(target_phys_addr_t special_base,
- target_phys_addr_t mem_base,
+PCIBus *pci_apb_init(hwaddr special_base,
+ hwaddr mem_base,
qemu_irq *ivec_irqs, PCIBus **bus2, PCIBus **bus3,
qemu_irq **pbm_irqs);
#endif
apic_timer_update(s, s->next_time);
}
-static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
+static uint32_t apic_mem_readb(void *opaque, hwaddr addr)
{
return 0;
}
-static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t apic_mem_readw(void *opaque, hwaddr addr)
{
return 0;
}
-static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void apic_mem_writeb(void *opaque, hwaddr addr, uint32_t val)
{
}
-static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void apic_mem_writew(void *opaque, hwaddr addr, uint32_t val)
{
}
-static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
+static uint32_t apic_mem_readl(void *opaque, hwaddr addr)
{
DeviceState *d;
APICCommonState *s;
return val;
}
-static void apic_send_msi(target_phys_addr_t addr, uint32_t data)
+static void apic_send_msi(hwaddr addr, uint32_t data)
{
uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;
uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;
apic_deliver_irq(dest, dest_mode, delivery, vector, trigger_mode);
}
-static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void apic_mem_writel(void *opaque, hwaddr addr, uint32_t val)
{
DeviceState *d;
APICCommonState *s;
}
}
-void apic_enable_vapic(DeviceState *d, target_phys_addr_t paddr)
+void apic_enable_vapic(DeviceState *d, hwaddr paddr)
{
APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);
APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
uint32_t vapic_control;
DeviceState *vapic;
- target_phys_addr_t vapic_paddr; /* note: persistence via kvmvapic */
+ hwaddr vapic_paddr; /* note: persistence via kvmvapic */
};
typedef struct VAPICState {
void apic_report_irq_delivered(int delivered);
bool apic_next_timer(APICCommonState *s, int64_t current_time);
void apic_enable_tpr_access_reporting(DeviceState *d, bool enable);
-void apic_enable_vapic(DeviceState *d, target_phys_addr_t paddr);
+void apic_enable_vapic(DeviceState *d, hwaddr paddr);
void vapic_report_tpr_access(DeviceState *dev, void *cpu, target_ulong ip,
TPRAccess access);
const char *kernel_cmdline;
const char *initrd_filename;
const char *dtb_filename;
- target_phys_addr_t loader_start;
+ hwaddr loader_start;
/* multicore boards that use the default secondary core boot functions
* need to put the address of the secondary boot code, the boot reg,
* and the GIC address in the next 3 values, respectively. boards that
* have their own boot functions can use these values as they want.
*/
- target_phys_addr_t smp_loader_start;
- target_phys_addr_t smp_bootreg_addr;
- target_phys_addr_t gic_cpu_if_addr;
+ hwaddr smp_loader_start;
+ hwaddr smp_bootreg_addr;
+ hwaddr gic_cpu_if_addr;
int nb_cpus;
int board_id;
int (*atag_board)(const struct arm_boot_info *info, void *p);
const struct arm_boot_info *info);
/* Used internally by arm_boot.c */
int is_linux;
- target_phys_addr_t initrd_size;
- target_phys_addr_t entry;
+ hwaddr initrd_size;
+ hwaddr entry;
};
void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info);
/* Per-CPU private memory mapped IO. */
-static uint64_t mpcore_scu_read(void *opaque, target_phys_addr_t offset,
+static uint64_t mpcore_scu_read(void *opaque, hwaddr offset,
unsigned size)
{
mpcore_priv_state *s = (mpcore_priv_state *)opaque;
}
}
-static void mpcore_scu_write(void *opaque, target_phys_addr_t offset,
+static void mpcore_scu_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
mpcore_priv_state *s = (mpcore_priv_state *)opaque;
* at 0x200, 0x300...
*/
for (i = 0; i < (s->num_cpu + 1); i++) {
- target_phys_addr_t offset = 0x100 + (i * 0x100);
+ hwaddr offset = 0x100 + (i * 0x100);
memory_region_add_subregion(&s->container, offset,
sysbus_mmio_get_region(gicbusdev, i + 1));
}
*/
for (i = 0; i < (s->num_cpu + 1) * 2; i++) {
/* Timers at 0x600, 0x700, ...; watchdogs at 0x620, 0x720, ... */
- target_phys_addr_t offset = 0x600 + (i >> 1) * 0x100 + (i & 1) * 0x20;
+ hwaddr offset = 0x600 + (i >> 1) * 0x100 + (i & 1) * 0x20;
memory_region_add_subregion(&s->container, offset,
sysbus_mmio_get_region(busdev, i));
}
static void set_kernel_args(const struct arm_boot_info *info)
{
int initrd_size = info->initrd_size;
- target_phys_addr_t base = info->loader_start;
- target_phys_addr_t p;
+ hwaddr base = info->loader_start;
+ hwaddr p;
p = base + KERNEL_ARGS_ADDR;
/* ATAG_CORE */
static void set_kernel_args_old(const struct arm_boot_info *info)
{
- target_phys_addr_t p;
+ hwaddr p;
const char *s;
int initrd_size = info->initrd_size;
- target_phys_addr_t base = info->loader_start;
+ hwaddr base = info->loader_start;
/* see linux/include/asm-arm/setup.h */
p = base + KERNEL_ARGS_ADDR;
}
}
-static int load_dtb(target_phys_addr_t addr, const struct arm_boot_info *binfo)
+static int load_dtb(hwaddr addr, const struct arm_boot_info *binfo)
{
#ifdef CONFIG_FDT
uint32_t *mem_reg_property;
int n;
int is_linux = 0;
uint64_t elf_entry;
- target_phys_addr_t entry;
+ hwaddr entry;
int big_endian;
QemuOpts *machine_opts;
*/
if (info->dtb_filename) {
/* Place the DTB after the initrd in memory */
- target_phys_addr_t dtb_start = TARGET_PAGE_ALIGN(info->loader_start
+ hwaddr dtb_start = TARGET_PAGE_ALIGN(info->loader_start
+ INITRD_LOAD_ADDR
+ initrd_size);
if (load_dtb(dtb_start, info)) {
}
}
-static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset)
+static uint32_t gic_dist_readb(void *opaque, hwaddr offset)
{
GICState *s = (GICState *)opaque;
uint32_t res;
return 0;
}
-static uint32_t gic_dist_readw(void *opaque, target_phys_addr_t offset)
+static uint32_t gic_dist_readw(void *opaque, hwaddr offset)
{
uint32_t val;
val = gic_dist_readb(opaque, offset);
return val;
}
-static uint32_t gic_dist_readl(void *opaque, target_phys_addr_t offset)
+static uint32_t gic_dist_readl(void *opaque, hwaddr offset)
{
uint32_t val;
val = gic_dist_readw(opaque, offset);
return val;
}
-static void gic_dist_writeb(void *opaque, target_phys_addr_t offset,
+static void gic_dist_writeb(void *opaque, hwaddr offset,
uint32_t value)
{
GICState *s = (GICState *)opaque;
hw_error("gic_dist_writeb: Bad offset %x\n", (int)offset);
}
-static void gic_dist_writew(void *opaque, target_phys_addr_t offset,
+static void gic_dist_writew(void *opaque, hwaddr offset,
uint32_t value)
{
gic_dist_writeb(opaque, offset, value & 0xff);
gic_dist_writeb(opaque, offset + 1, value >> 8);
}
-static void gic_dist_writel(void *opaque, target_phys_addr_t offset,
+static void gic_dist_writel(void *opaque, hwaddr offset,
uint32_t value)
{
GICState *s = (GICState *)opaque;
}
/* Wrappers to read/write the GIC CPU interface for the current CPU */
-static uint64_t gic_thiscpu_read(void *opaque, target_phys_addr_t addr,
+static uint64_t gic_thiscpu_read(void *opaque, hwaddr addr,
unsigned size)
{
GICState *s = (GICState *)opaque;
return gic_cpu_read(s, gic_get_current_cpu(s), addr);
}
-static void gic_thiscpu_write(void *opaque, target_phys_addr_t addr,
+static void gic_thiscpu_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
GICState *s = (GICState *)opaque;
/* Wrappers to read/write the GIC CPU interface for a specific CPU.
* These just decode the opaque pointer into GICState* + cpu id.
*/
-static uint64_t gic_do_cpu_read(void *opaque, target_phys_addr_t addr,
+static uint64_t gic_do_cpu_read(void *opaque, hwaddr addr,
unsigned size)
{
GICState **backref = (GICState **)opaque;
return gic_cpu_read(s, id, addr);
}
-static void gic_do_cpu_write(void *opaque, target_phys_addr_t addr,
+static void gic_do_cpu_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
GICState **backref = (GICState **)opaque;
};
-static uint64_t l2x0_priv_read(void *opaque, target_phys_addr_t offset,
+static uint64_t l2x0_priv_read(void *opaque, hwaddr offset,
unsigned size)
{
uint32_t cache_data;
return 0;
}
-static void l2x0_priv_write(void *opaque, target_phys_addr_t offset,
+static void l2x0_priv_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
l2x0_state *s = (l2x0_state *)opaque;
timerblock_update_irq(tb);
}
-static uint64_t timerblock_read(void *opaque, target_phys_addr_t addr,
+static uint64_t timerblock_read(void *opaque, hwaddr addr,
unsigned size)
{
timerblock *tb = (timerblock *)opaque;
}
}
-static void timerblock_write(void *opaque, target_phys_addr_t addr,
+static void timerblock_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
timerblock *tb = (timerblock *)opaque;
/* Wrapper functions to implement the "read timer/watchdog for
* the current CPU" memory regions.
*/
-static uint64_t arm_thistimer_read(void *opaque, target_phys_addr_t addr,
+static uint64_t arm_thistimer_read(void *opaque, hwaddr addr,
unsigned size)
{
arm_mptimer_state *s = (arm_mptimer_state *)opaque;
return timerblock_read(&s->timerblock[id * 2], addr, size);
}
-static void arm_thistimer_write(void *opaque, target_phys_addr_t addr,
+static void arm_thistimer_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
arm_mptimer_state *s = (arm_mptimer_state *)opaque;
timerblock_write(&s->timerblock[id * 2], addr, value, size);
}
-static uint64_t arm_thiswdog_read(void *opaque, target_phys_addr_t addr,
+static uint64_t arm_thiswdog_read(void *opaque, hwaddr addr,
unsigned size)
{
arm_mptimer_state *s = (arm_mptimer_state *)opaque;
return timerblock_read(&s->timerblock[id * 2 + 1], addr, size);
}
-static void arm_thiswdog_write(void *opaque, target_phys_addr_t addr,
+static void arm_thiswdog_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
arm_mptimer_state *s = (arm_mptimer_state *)opaque;
}
}
-static uint64_t arm_sysctl_read(void *opaque, target_phys_addr_t offset,
+static uint64_t arm_sysctl_read(void *opaque, hwaddr offset,
unsigned size)
{
arm_sysctl_state *s = (arm_sysctl_state *)opaque;
}
}
-static void arm_sysctl_write(void *opaque, target_phys_addr_t offset,
+static void arm_sysctl_write(void *opaque, hwaddr offset,
uint64_t val, unsigned size)
{
arm_sysctl_state *s = (arm_sysctl_state *)opaque;
}
}
-static uint32_t arm_timer_read(void *opaque, target_phys_addr_t offset)
+static uint32_t arm_timer_read(void *opaque, hwaddr offset)
{
arm_timer_state *s = (arm_timer_state *)opaque;
ptimer_set_limit(s->timer, limit, reload);
}
-static void arm_timer_write(void *opaque, target_phys_addr_t offset,
+static void arm_timer_write(void *opaque, hwaddr offset,
uint32_t value)
{
arm_timer_state *s = (arm_timer_state *)opaque;
qemu_set_irq(s->irq, s->level[0] || s->level[1]);
}
-static uint64_t sp804_read(void *opaque, target_phys_addr_t offset,
+static uint64_t sp804_read(void *opaque, hwaddr offset,
unsigned size)
{
sp804_state *s = (sp804_state *)opaque;
return 0;
}
-static void sp804_write(void *opaque, target_phys_addr_t offset,
+static void sp804_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
sp804_state *s = (sp804_state *)opaque;
arm_timer_state *timer[3];
} icp_pit_state;
-static uint64_t icp_pit_read(void *opaque, target_phys_addr_t offset,
+static uint64_t icp_pit_read(void *opaque, hwaddr offset,
unsigned size)
{
icp_pit_state *s = (icp_pit_state *)opaque;
return arm_timer_read(s->timer[n], offset & 0xff);
}
-static void icp_pit_write(void *opaque, target_phys_addr_t offset,
+static void icp_pit_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
icp_pit_state *s = (icp_pit_state *)opaque;
}
-static uint32_t bitband_readb(void *opaque, target_phys_addr_t offset)
+static uint32_t bitband_readb(void *opaque, hwaddr offset)
{
uint8_t v;
cpu_physical_memory_read(bitband_addr(opaque, offset), &v, 1);
return (v & (1 << ((offset >> 2) & 7))) != 0;
}
-static void bitband_writeb(void *opaque, target_phys_addr_t offset,
+static void bitband_writeb(void *opaque, hwaddr offset,
uint32_t value)
{
uint32_t addr;
cpu_physical_memory_write(addr, &v, 1);
}
-static uint32_t bitband_readw(void *opaque, target_phys_addr_t offset)
+static uint32_t bitband_readw(void *opaque, hwaddr offset)
{
uint32_t addr;
uint16_t mask;
return (v & mask) != 0;
}
-static void bitband_writew(void *opaque, target_phys_addr_t offset,
+static void bitband_writew(void *opaque, hwaddr offset,
uint32_t value)
{
uint32_t addr;
cpu_physical_memory_write(addr, (uint8_t *)&v, 2);
}
-static uint32_t bitband_readl(void *opaque, target_phys_addr_t offset)
+static uint32_t bitband_readl(void *opaque, hwaddr offset)
{
uint32_t addr;
uint32_t mask;
return (v & mask) != 0;
}
-static void bitband_writel(void *opaque, target_phys_addr_t offset,
+static void bitband_writel(void *opaque, hwaddr offset,
uint32_t value)
{
uint32_t addr;
}
}
-static uint64_t nvic_sysreg_read(void *opaque, target_phys_addr_t addr,
+static uint64_t nvic_sysreg_read(void *opaque, hwaddr addr,
unsigned size)
{
/* At the moment we only support the ID registers for byte/word access.
hw_error("NVIC: Bad read of size %d at offset 0x%x\n", size, offset);
}
-static void nvic_sysreg_write(void *opaque, target_phys_addr_t addr,
+static void nvic_sysreg_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
uint32_t offset = addr;
};
static struct nand_state_t nand_state;
-static uint64_t nand_read(void *opaque, target_phys_addr_t addr, unsigned size)
+static uint64_t nand_read(void *opaque, hwaddr addr, unsigned size)
{
struct nand_state_t *s = opaque;
uint32_t r;
}
static void
-nand_write(void *opaque, target_phys_addr_t addr, uint64_t value,
+nand_write(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
struct nand_state_t *s = opaque;
uint32_t regs[0x5c / 4];
} gpio_state;
-static uint64_t gpio_read(void *opaque, target_phys_addr_t addr, unsigned size)
+static uint64_t gpio_read(void *opaque, hwaddr addr, unsigned size)
{
struct gpio_state_t *s = opaque;
uint32_t r = 0;
D(printf("%s %x=%x\n", __func__, addr, r));
}
-static void gpio_write(void *opaque, target_phys_addr_t addr, uint64_t value,
+static void gpio_write(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
struct gpio_state_t *s = opaque;
MemoryRegion iomem_ldma;
MemoryRegion iomem_cop;
- target_phys_addr_t bonito_pciio_start;
- target_phys_addr_t bonito_pciio_length;
+ hwaddr bonito_pciio_start;
+ hwaddr bonito_pciio_length;
int bonito_pciio_handle;
- target_phys_addr_t bonito_localio_start;
- target_phys_addr_t bonito_localio_length;
+ hwaddr bonito_localio_start;
+ hwaddr bonito_localio_length;
int bonito_localio_handle;
} PCIBonitoState;
PCIBonitoState *pci_dev;
};
-static void bonito_writel(void *opaque, target_phys_addr_t addr,
+static void bonito_writel(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
PCIBonitoState *s = opaque;
}
}
-static uint64_t bonito_readl(void *opaque, target_phys_addr_t addr,
+static uint64_t bonito_readl(void *opaque, hwaddr addr,
unsigned size)
{
PCIBonitoState *s = opaque;
},
};
-static void bonito_pciconf_writel(void *opaque, target_phys_addr_t addr,
+static void bonito_pciconf_writel(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
PCIBonitoState *s = opaque;
d->config_write(d, addr, val, 4);
}
-static uint64_t bonito_pciconf_readl(void *opaque, target_phys_addr_t addr,
+static uint64_t bonito_pciconf_readl(void *opaque, hwaddr addr,
unsigned size)
{
},
};
-static uint64_t bonito_ldma_readl(void *opaque, target_phys_addr_t addr,
+static uint64_t bonito_ldma_readl(void *opaque, hwaddr addr,
unsigned size)
{
uint32_t val;
return val;
}
-static void bonito_ldma_writel(void *opaque, target_phys_addr_t addr,
+static void bonito_ldma_writel(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
PCIBonitoState *s = opaque;
},
};
-static uint64_t bonito_cop_readl(void *opaque, target_phys_addr_t addr,
+static uint64_t bonito_cop_readl(void *opaque, hwaddr addr,
unsigned size)
{
uint32_t val;
return val;
}
-static void bonito_cop_writel(void *opaque, target_phys_addr_t addr,
+static void bonito_cop_writel(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
PCIBonitoState *s = opaque;
},
};
-static uint32_t bonito_sbridge_pciaddr(void *opaque, target_phys_addr_t addr)
+static uint32_t bonito_sbridge_pciaddr(void *opaque, hwaddr addr)
{
PCIBonitoState *s = opaque;
PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
return pciaddr;
}
-static void bonito_spciconf_writeb(void *opaque, target_phys_addr_t addr,
+static void bonito_spciconf_writeb(void *opaque, hwaddr addr,
uint32_t val)
{
PCIBonitoState *s = opaque;
pci_set_word(d->config + PCI_STATUS, status);
}
-static void bonito_spciconf_writew(void *opaque, target_phys_addr_t addr,
+static void bonito_spciconf_writew(void *opaque, hwaddr addr,
uint32_t val)
{
PCIBonitoState *s = opaque;
pci_set_word(d->config + PCI_STATUS, status);
}
-static void bonito_spciconf_writel(void *opaque, target_phys_addr_t addr,
+static void bonito_spciconf_writel(void *opaque, hwaddr addr,
uint32_t val)
{
PCIBonitoState *s = opaque;
pci_set_word(d->config + PCI_STATUS, status);
}
-static uint32_t bonito_spciconf_readb(void *opaque, target_phys_addr_t addr)
+static uint32_t bonito_spciconf_readb(void *opaque, hwaddr addr)
{
PCIBonitoState *s = opaque;
PCIDevice *d = PCI_DEVICE(s);
return pci_data_read(phb->bus, phb->config_reg, 1);
}
-static uint32_t bonito_spciconf_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t bonito_spciconf_readw(void *opaque, hwaddr addr)
{
PCIBonitoState *s = opaque;
PCIDevice *d = PCI_DEVICE(s);
return pci_data_read(phb->bus, phb->config_reg, 2);
}
-static uint32_t bonito_spciconf_readl(void *opaque, target_phys_addr_t addr)
+static uint32_t bonito_spciconf_readl(void *opaque, hwaddr addr)
{
PCIBonitoState *s = opaque;
PCIDevice *d = PCI_DEVICE(s);
static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
{
unsigned desc[2];
- target_phys_addr_t packet_desc_addr, last_desc_addr;
+ hwaddr packet_desc_addr, last_desc_addr;
GemState *s;
unsigned rxbufsize, bytes_to_copy;
unsigned rxbuf_offset;
static void gem_transmit(GemState *s)
{
unsigned desc[2];
- target_phys_addr_t packet_desc_addr;
+ hwaddr packet_desc_addr;
uint8_t tx_packet[2048];
uint8_t *p;
unsigned total_bytes;
* gem_read32:
* Read a GEM register.
*/
-static uint64_t gem_read(void *opaque, target_phys_addr_t offset, unsigned size)
+static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
{
GemState *s;
uint32_t retval;
* gem_write32:
* Write a GEM register.
*/
-static void gem_write(void *opaque, target_phys_addr_t offset, uint64_t val,
+static void gem_write(void *opaque, hwaddr offset, uint64_t val,
unsigned size)
{
GemState *s = (GemState *)opaque;
}
static CadenceTimerState *cadence_timer_from_addr(void *opaque,
- target_phys_addr_t offset)
+ hwaddr offset)
{
unsigned int index;
CadenceTTCState *s = (CadenceTTCState *)opaque;
cadence_timer_run(s);
}
-static uint32_t cadence_ttc_read_imp(void *opaque, target_phys_addr_t offset)
+static uint32_t cadence_ttc_read_imp(void *opaque, hwaddr offset)
{
CadenceTimerState *s = cadence_timer_from_addr(opaque, offset);
uint32_t value;
}
}
-static uint64_t cadence_ttc_read(void *opaque, target_phys_addr_t offset,
+static uint64_t cadence_ttc_read(void *opaque, hwaddr offset,
unsigned size)
{
uint32_t ret = cadence_ttc_read_imp(opaque, offset);
return ret;
}
-static void cadence_ttc_write(void *opaque, target_phys_addr_t offset,
+static void cadence_ttc_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
CadenceTimerState *s = cadence_timer_from_addr(opaque, offset);
uart_update_status(s);
}
-static void uart_write(void *opaque, target_phys_addr_t offset,
+static void uart_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
UartState *s = (UartState *)opaque;
}
}
-static uint64_t uart_read(void *opaque, target_phys_addr_t offset,
+static uint64_t uart_read(void *opaque, hwaddr offset,
unsigned size)
{
UartState *s = (UartState *)opaque;
***************************************/
static uint64_t cirrus_vga_mem_read(void *opaque,
- target_phys_addr_t addr,
+ hwaddr addr,
uint32_t size)
{
CirrusVGAState *s = opaque;
}
static void cirrus_vga_mem_write(void *opaque,
- target_phys_addr_t addr,
+ hwaddr addr,
uint64_t mem_value,
uint32_t size)
{
*
***************************************/
-static uint64_t cirrus_linear_read(void *opaque, target_phys_addr_t addr,
+static uint64_t cirrus_linear_read(void *opaque, hwaddr addr,
unsigned size)
{
CirrusVGAState *s = opaque;
return ret;
}
-static void cirrus_linear_write(void *opaque, target_phys_addr_t addr,
+static void cirrus_linear_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
CirrusVGAState *s = opaque;
static uint64_t cirrus_linear_bitblt_read(void *opaque,
- target_phys_addr_t addr,
+ hwaddr addr,
unsigned size)
{
CirrusVGAState *s = opaque;
}
static void cirrus_linear_bitblt_write(void *opaque,
- target_phys_addr_t addr,
+ hwaddr addr,
uint64_t val,
unsigned size)
{
*
***************************************/
-static uint64_t cirrus_mmio_read(void *opaque, target_phys_addr_t addr,
+static uint64_t cirrus_mmio_read(void *opaque, hwaddr addr,
unsigned size)
{
CirrusVGAState *s = opaque;
}
}
-static void cirrus_mmio_write(void *opaque, target_phys_addr_t addr,
+static void cirrus_mmio_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
CirrusVGAState *s = opaque;
const char *cmdline;
int image_size;
- target_phys_addr_t entry;
+ hwaddr entry;
};
void cris_load_image(CRISCPU *cpu, struct cris_load_info *li);
s->dregs[25] = CS_VER;
}
-static uint64_t cs_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t cs_mem_read(void *opaque, hwaddr addr,
unsigned size)
{
CSState *s = opaque;
return ret;
}
-static void cs_mem_write(void *opaque, target_phys_addr_t addr,
+static void cs_mem_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
CSState *s = opaque;
}
}
-static uint64_t cs_read (void *opaque, target_phys_addr_t addr, unsigned size)
+static uint64_t cs_read (void *opaque, hwaddr addr, unsigned size)
{
CSState *s = opaque;
uint32_t saddr, iaddr, ret;
return ret;
}
-static void cs_write (void *opaque, target_phys_addr_t addr,
+static void cs_write (void *opaque, hwaddr addr,
uint64_t val64, unsigned size)
{
CSState *s = opaque;
cuda_update_irq(s);
}
-static uint32_t cuda_readb(void *opaque, target_phys_addr_t addr)
+static uint32_t cuda_readb(void *opaque, hwaddr addr)
{
CUDAState *s = opaque;
uint32_t val;
return val;
}
-static void cuda_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void cuda_writeb(void *opaque, hwaddr addr, uint32_t val)
{
CUDAState *s = opaque;
}
}
-static void cuda_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
+static void cuda_writew (void *opaque, hwaddr addr, uint32_t value)
{
}
-static void cuda_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
+static void cuda_writel (void *opaque, hwaddr addr, uint32_t value)
{
}
-static uint32_t cuda_readw (void *opaque, target_phys_addr_t addr)
+static uint32_t cuda_readw (void *opaque, hwaddr addr)
{
return 0;
}
-static uint32_t cuda_readl (void *opaque, target_phys_addr_t addr)
+static uint32_t cuda_readl (void *opaque, hwaddr addr)
{
return 0;
}
int DMA_read_memory (int nchan, void *buf, int pos, int len)
{
struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3];
- target_phys_addr_t addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
+ hwaddr addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
if (r->mode & 0x20) {
int i;
int DMA_write_memory (int nchan, void *buf, int pos, int len)
{
struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3];
- target_phys_addr_t addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
+ hwaddr addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
if (r->mode & 0x20) {
int i;
int loopback_packet;
/* Memory access */
- void (*memory_rw)(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write);
+ void (*memory_rw)(void *opaque, hwaddr addr, uint8_t *buf, int len, int is_write);
void* mem_opaque;
} dp8393xState;
dp8393x_update_irq(s);
}
-static uint32_t dp8393x_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t dp8393x_readw(void *opaque, hwaddr addr)
{
dp8393xState *s = opaque;
int reg;
return read_register(s, reg);
}
-static uint32_t dp8393x_readb(void *opaque, target_phys_addr_t addr)
+static uint32_t dp8393x_readb(void *opaque, hwaddr addr)
{
uint16_t v = dp8393x_readw(opaque, addr & ~0x1);
return (v >> (8 * (addr & 0x1))) & 0xff;
}
-static uint32_t dp8393x_readl(void *opaque, target_phys_addr_t addr)
+static uint32_t dp8393x_readl(void *opaque, hwaddr addr)
{
uint32_t v;
v = dp8393x_readw(opaque, addr);
return v;
}
-static void dp8393x_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void dp8393x_writew(void *opaque, hwaddr addr, uint32_t val)
{
dp8393xState *s = opaque;
int reg;
write_register(s, reg, (uint16_t)val);
}
-static void dp8393x_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void dp8393x_writeb(void *opaque, hwaddr addr, uint32_t val)
{
uint16_t old_val = dp8393x_readw(opaque, addr & ~0x1);
dp8393x_writew(opaque, addr & ~0x1, val);
}
-static void dp8393x_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void dp8393x_writel(void *opaque, hwaddr addr, uint32_t val)
{
dp8393x_writew(opaque, addr, val & 0xffff);
dp8393x_writew(opaque, addr + 2, (val >> 16) & 0xffff);
.cleanup = nic_cleanup,
};
-void dp83932_init(NICInfo *nd, target_phys_addr_t base, int it_shift,
+void dp83932_init(NICInfo *nd, hwaddr base, int it_shift,
MemoryRegion *address_space,
qemu_irq irq, void* mem_opaque,
- void (*memory_rw)(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write))
+ void (*memory_rw)(void *opaque, hwaddr addr, uint8_t *buf, int len, int is_write))
{
dp8393xState *s;
uint8_t *contents;
} NvRamState;
-static uint64_t nvram_read(void *opaque, target_phys_addr_t addr, unsigned size)
+static uint64_t nvram_read(void *opaque, hwaddr addr, unsigned size)
{
NvRamState *s = opaque;
uint32_t val;
return val;
}
-static void nvram_write(void *opaque, target_phys_addr_t addr, uint64_t val,
+static void nvram_write(void *opaque, hwaddr addr, uint64_t val,
unsigned size)
{
NvRamState *s = opaque;
MemoryRegion *ram = g_new(MemoryRegion, 1);
int kernel_size;
uint64_t elf_entry;
- target_phys_addr_t entry;
+ hwaddr entry;
if (!cpu_model)
cpu_model = "cfv4e";
enum { NWRITEOPS = ARRAY_SIZE(macreg_writeops) };
static void
-e1000_mmio_write(void *opaque, target_phys_addr_t addr, uint64_t val,
+e1000_mmio_write(void *opaque, hwaddr addr, uint64_t val,
unsigned size)
{
E1000State *s = opaque;
}
static uint64_t
-e1000_mmio_read(void *opaque, target_phys_addr_t addr, unsigned size)
+e1000_mmio_read(void *opaque, hwaddr addr, unsigned size)
{
E1000State *s = opaque;
unsigned int index = (addr & 0x1ffff) >> 2;
},
};
-static uint64_t e1000_io_read(void *opaque, target_phys_addr_t addr,
+static uint64_t e1000_io_read(void *opaque, hwaddr addr,
unsigned size)
{
E1000State *s = opaque;
return 0;
}
-static void e1000_io_write(void *opaque, target_phys_addr_t addr,
+static void e1000_io_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
E1000State *s = opaque;
uint32_t version;
} ECCState;
-static void ecc_mem_write(void *opaque, target_phys_addr_t addr, uint64_t val,
+static void ecc_mem_write(void *opaque, hwaddr addr, uint64_t val,
unsigned size)
{
ECCState *s = opaque;
}
}
-static uint64_t ecc_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t ecc_mem_read(void *opaque, hwaddr addr,
unsigned size)
{
ECCState *s = opaque;
},
};
-static void ecc_diag_mem_write(void *opaque, target_phys_addr_t addr,
+static void ecc_diag_mem_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
ECCState *s = opaque;
s->diag[addr & ECC_DIAG_MASK] = val;
}
-static uint64_t ecc_diag_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t ecc_diag_mem_read(void *opaque, hwaddr addr,
unsigned size)
{
ECCState *s = opaque;
}
}
-static uint64_t eepro100_read(void *opaque, target_phys_addr_t addr,
+static uint64_t eepro100_read(void *opaque, hwaddr addr,
unsigned size)
{
EEPRO100State *s = opaque;
}
}
-static void eepro100_write(void *opaque, target_phys_addr_t addr,
+static void eepro100_write(void *opaque, hwaddr addr,
uint64_t data, unsigned size)
{
EEPRO100State *s = opaque;
static int glue(symfind, SZ)(const void *s0, const void *s1)
{
- target_phys_addr_t addr = *(target_phys_addr_t *)s0;
+ hwaddr addr = *(hwaddr *)s0;
struct elf_sym *sym = (struct elf_sym *)s1;
int result = 0;
if (addr < sym->st_value) {
}
static const char *glue(lookup_symbol, SZ)(struct syminfo *s,
- target_phys_addr_t orig_addr)
+ hwaddr orig_addr)
{
struct elf_sym *syms = glue(s->disas_symtab.elf, SZ);
struct elf_sym *sym;
uint64_t size;
} EmptySlot;
-static uint64_t empty_slot_read(void *opaque, target_phys_addr_t addr,
+static uint64_t empty_slot_read(void *opaque, hwaddr addr,
unsigned size)
{
DPRINTF("read from " TARGET_FMT_plx "\n", addr);
return 0;
}
-static void empty_slot_write(void *opaque, target_phys_addr_t addr,
+static void empty_slot_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
DPRINTF("write 0x%x to " TARGET_FMT_plx "\n", (unsigned)val, addr);
.endianness = DEVICE_NATIVE_ENDIAN,
};
-void empty_slot_init(target_phys_addr_t addr, uint64_t slot_size)
+void empty_slot_init(hwaddr addr, uint64_t slot_size)
{
if (slot_size > 0) {
/* Only empty slots larger than 0 byte need handling. */
/* empty_slot.c */
-void empty_slot_init(target_phys_addr_t addr, uint64_t slot_size);
+void empty_slot_init(hwaddr addr, uint64_t slot_size);
qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
}
-static void escc_mem_write(void *opaque, target_phys_addr_t addr,
+static void escc_mem_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
SerialState *serial = opaque;
}
}
-static uint64_t escc_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t escc_mem_read(void *opaque, hwaddr addr,
unsigned size)
{
SerialState *serial = opaque;
}
};
-MemoryRegion *escc_init(target_phys_addr_t base, qemu_irq irqA, qemu_irq irqB,
+MemoryRegion *escc_init(hwaddr base, qemu_irq irqA, qemu_irq irqB,
CharDriverState *chrA, CharDriverState *chrB,
int clock, int it_shift)
{
put_queue(s, 0);
}
-void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq,
+void slavio_serial_ms_kbd_init(hwaddr base, qemu_irq irq,
int disabled, int clock, int it_shift)
{
DeviceState *dev;
/* escc.c */
#define ESCC_SIZE 4
-MemoryRegion *escc_init(target_phys_addr_t base, qemu_irq irqA, qemu_irq irqB,
+MemoryRegion *escc_init(hwaddr base, qemu_irq irqA, qemu_irq irqB,
CharDriverState *chrA, CharDriverState *chrB,
int clock, int it_shift);
-void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq,
+void slavio_serial_ms_kbd_init(hwaddr base, qemu_irq irq,
int disabled, int clock, int it_shift);
return val;
}
-static void esp_pci_io_write(void *opaque, target_phys_addr_t addr,
+static void esp_pci_io_write(void *opaque, hwaddr addr,
uint64_t val, unsigned int size)
{
PCIESPState *pci = opaque;
}
}
-static uint64_t esp_pci_io_read(void *opaque, target_phys_addr_t addr,
+static uint64_t esp_pci_io_read(void *opaque, hwaddr addr,
unsigned int size)
{
PCIESPState *pci = opaque;
s->wregs[saddr] = val;
}
-static bool esp_mem_accepts(void *opaque, target_phys_addr_t addr,
+static bool esp_mem_accepts(void *opaque, hwaddr addr,
unsigned size, bool is_write)
{
return (size == 1) || (is_write && size == 4);
ESPState esp;
} SysBusESPState;
-static void sysbus_esp_mem_write(void *opaque, target_phys_addr_t addr,
+static void sysbus_esp_mem_write(void *opaque, hwaddr addr,
uint64_t val, unsigned int size)
{
SysBusESPState *sysbus = opaque;
esp_reg_write(&sysbus->esp, saddr, val);
}
-static uint64_t sysbus_esp_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t sysbus_esp_mem_read(void *opaque, hwaddr addr,
unsigned int size)
{
SysBusESPState *sysbus = opaque;
.valid.accepts = esp_mem_accepts,
};
-void esp_init(target_phys_addr_t espaddr, int it_shift,
+void esp_init(hwaddr espaddr, int it_shift,
ESPDMAMemoryReadWriteFunc dma_memory_read,
ESPDMAMemoryReadWriteFunc dma_memory_write,
void *dma_opaque, qemu_irq irq, qemu_irq *reset,
/* esp.c */
#define ESP_MAX_DEVS 7
typedef void (*ESPDMAMemoryReadWriteFunc)(void *opaque, uint8_t *buf, int len);
-void esp_init(target_phys_addr_t espaddr, int it_shift,
+void esp_init(hwaddr espaddr, int it_shift,
ESPDMAMemoryReadWriteFunc dma_memory_read,
ESPDMAMemoryReadWriteFunc dma_memory_write,
void *dma_opaque, qemu_irq irq, qemu_irq *reset,
/* Instantiate an ETRAXFS Ethernet MAC. */
static inline DeviceState *
-etraxfs_eth_init(NICInfo *nd, target_phys_addr_t base, int phyaddr,
+etraxfs_eth_init(NICInfo *nd, hwaddr base, int phyaddr,
void *dma_out, void *dma_in)
{
DeviceState *dev;
&& ctrl->channels[c].client;
}
-static inline int fs_channel(target_phys_addr_t addr)
+static inline int fs_channel(hwaddr addr)
{
/* Every channel has a 0x2000 ctrl register map. */
return addr >> 13;
#ifdef USE_THIS_DEAD_CODE
static void channel_load_g(struct fs_dma_ctrl *ctrl, int c)
{
- target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP);
+ hwaddr addr = channel_reg(ctrl, c, RW_GROUP);
/* Load and decode. FIXME: handle endianness. */
cpu_physical_memory_read (addr,
static void channel_load_c(struct fs_dma_ctrl *ctrl, int c)
{
- target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
+ hwaddr addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
/* Load and decode. FIXME: handle endianness. */
cpu_physical_memory_read (addr,
static void channel_load_d(struct fs_dma_ctrl *ctrl, int c)
{
- target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA);
+ hwaddr addr = channel_reg(ctrl, c, RW_SAVED_DATA);
/* Load and decode. FIXME: handle endianness. */
D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
static void channel_store_c(struct fs_dma_ctrl *ctrl, int c)
{
- target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
+ hwaddr addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
/* Encode and store. FIXME: handle endianness. */
D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
static void channel_store_d(struct fs_dma_ctrl *ctrl, int c)
{
- target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA);
+ hwaddr addr = channel_reg(ctrl, c, RW_SAVED_DATA);
/* Encode and store. FIXME: handle endianness. */
D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
return 0;
}
-static uint32_t dma_rinvalid (void *opaque, target_phys_addr_t addr)
+static uint32_t dma_rinvalid (void *opaque, hwaddr addr)
{
hw_error("Unsupported short raccess. reg=" TARGET_FMT_plx "\n", addr);
return 0;
}
static uint64_t
-dma_read(void *opaque, target_phys_addr_t addr, unsigned int size)
+dma_read(void *opaque, hwaddr addr, unsigned int size)
{
struct fs_dma_ctrl *ctrl = opaque;
int c;
}
static void
-dma_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value)
+dma_winvalid (void *opaque, hwaddr addr, uint32_t value)
{
hw_error("Unsupported short waccess. reg=" TARGET_FMT_plx "\n", addr);
}
}
static void
-dma_write(void *opaque, target_phys_addr_t addr,
+dma_write(void *opaque, hwaddr addr,
uint64_t val64, unsigned int size)
{
struct fs_dma_ctrl *ctrl = opaque;
qemu_bh_schedule_idle(etraxfs_dmac->bh);
}
-void *etraxfs_dmac_init(target_phys_addr_t base, int nr_channels)
+void *etraxfs_dmac_init(hwaddr base, int nr_channels)
{
struct fs_dma_ctrl *ctrl = NULL;
} client;
};
-void *etraxfs_dmac_init(target_phys_addr_t base, int nr_channels);
+void *etraxfs_dmac_init(hwaddr base, int nr_channels);
void etraxfs_dmac_connect(void *opaque, int channel, qemu_irq *line,
int input);
void etraxfs_dmac_connect_client(void *opaque, int c,
}
static uint64_t
-eth_read(void *opaque, target_phys_addr_t addr, unsigned int size)
+eth_read(void *opaque, hwaddr addr, unsigned int size)
{
struct fs_eth *eth = opaque;
uint32_t r = 0;
}
static void
-eth_write(void *opaque, target_phys_addr_t addr,
+eth_write(void *opaque, hwaddr addr,
uint64_t val64, unsigned int size)
{
struct fs_eth *eth = opaque;
}
static uint64_t
-pic_read(void *opaque, target_phys_addr_t addr, unsigned int size)
+pic_read(void *opaque, hwaddr addr, unsigned int size)
{
struct etrax_pic *fs = opaque;
uint32_t rval;
return rval;
}
-static void pic_write(void *opaque, target_phys_addr_t addr,
+static void pic_write(void *opaque, hwaddr addr,
uint64_t value, unsigned int size)
{
struct etrax_pic *fs = opaque;
}
static uint64_t
-ser_read(void *opaque, target_phys_addr_t addr, unsigned int size)
+ser_read(void *opaque, hwaddr addr, unsigned int size)
{
struct etrax_serial *s = opaque;
D(CPUCRISState *env = s->env);
}
static void
-ser_write(void *opaque, target_phys_addr_t addr,
+ser_write(void *opaque, hwaddr addr,
uint64_t val64, unsigned int size)
{
struct etrax_serial *s = opaque;
};
static uint64_t
-timer_read(void *opaque, target_phys_addr_t addr, unsigned int size)
+timer_read(void *opaque, hwaddr addr, unsigned int size)
{
struct etrax_timer *t = opaque;
uint32_t r = 0;
}
static void
-timer_write(void *opaque, target_phys_addr_t addr,
+timer_write(void *opaque, hwaddr addr,
uint64_t val64, unsigned int size)
{
struct etrax_timer *t = opaque;
/*
* exynos4210 UART
*/
-DeviceState *exynos4210_uart_create(target_phys_addr_t addr,
+DeviceState *exynos4210_uart_create(hwaddr addr,
int fifo_size,
int channel,
CharDriverState *chr,
}
static uint64_t
-exynos4210_combiner_read(void *opaque, target_phys_addr_t offset, unsigned size)
+exynos4210_combiner_read(void *opaque, hwaddr offset, unsigned size)
{
struct Exynos4210CombinerState *s =
(struct Exynos4210CombinerState *)opaque;
}
}
-static void exynos4210_combiner_write(void *opaque, target_phys_addr_t offset,
+static void exynos4210_combiner_write(void *opaque, hwaddr offset,
uint64_t val, unsigned size)
{
struct Exynos4210CombinerState *s =
uint16_t virtpage_offsize; /* VIDWADD2 register */
MemoryRegionSection mem_section; /* RAM fragment containing framebuffer */
uint8_t *host_fb_addr; /* Host pointer to window's framebuffer */
- target_phys_addr_t fb_len; /* Framebuffer length */
+ hwaddr fb_len; /* Framebuffer length */
};
typedef struct {
static void fimd_update_memory_section(Exynos4210fimdState *s, unsigned win)
{
Exynos4210fimdWindow *w = &s->window[win];
- target_phys_addr_t fb_start_addr, fb_mapped_len;
+ hwaddr fb_start_addr, fb_mapped_len;
if (!s->enabled || !(w->wincon & FIMD_WINCON_ENWIN) ||
FIMD_WINDOW_PROTECTED(s->shadowcon, win)) {
Exynos4210fimdState *s = (Exynos4210fimdState *)opaque;
Exynos4210fimdWindow *w;
int i, line;
- target_phys_addr_t fb_line_addr, inc_size;
+ hwaddr fb_line_addr, inc_size;
int scrn_height;
int first_line = -1, last_line = -1, scrn_width;
bool blend = false;
s->hueoffset = 0x01800080;
}
-static void exynos4210_fimd_write(void *opaque, target_phys_addr_t offset,
+static void exynos4210_fimd_write(void *opaque, hwaddr offset,
uint64_t val, unsigned size)
{
Exynos4210fimdState *s = (Exynos4210fimdState *)opaque;
}
}
-static uint64_t exynos4210_fimd_read(void *opaque, target_phys_addr_t offset,
+static uint64_t exynos4210_fimd_read(void *opaque, hwaddr offset,
unsigned size)
{
Exynos4210fimdState *s = (Exynos4210fimdState *)opaque;
exynos4210_i2c_raise_interrupt(s);
}
-static uint64_t exynos4210_i2c_read(void *opaque, target_phys_addr_t offset,
+static uint64_t exynos4210_i2c_read(void *opaque, hwaddr offset,
unsigned size)
{
Exynos4210I2CState *s = (Exynos4210I2CState *)opaque;
return value;
}
-static void exynos4210_i2c_write(void *opaque, target_phys_addr_t offset,
+static void exynos4210_i2c_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
Exynos4210I2CState *s = (Exynos4210I2CState *)opaque;
}
/* Multi Core Timer read */
-static uint64_t exynos4210_mct_read(void *opaque, target_phys_addr_t offset,
+static uint64_t exynos4210_mct_read(void *opaque, hwaddr offset,
unsigned size)
{
Exynos4210MCTState *s = (Exynos4210MCTState *)opaque;
}
/* MCT write */
-static void exynos4210_mct_write(void *opaque, target_phys_addr_t offset,
+static void exynos4210_mct_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
Exynos4210MCTState *s = (Exynos4210MCTState *)opaque;
uint32_t reg[PMU_NUM_OF_REGISTERS];
} Exynos4210PmuState;
-static uint64_t exynos4210_pmu_read(void *opaque, target_phys_addr_t offset,
+static uint64_t exynos4210_pmu_read(void *opaque, hwaddr offset,
unsigned size)
{
Exynos4210PmuState *s = (Exynos4210PmuState *)opaque;
return 0;
}
-static void exynos4210_pmu_write(void *opaque, target_phys_addr_t offset,
+static void exynos4210_pmu_write(void *opaque, hwaddr offset,
uint64_t val, unsigned size)
{
Exynos4210PmuState *s = (Exynos4210PmuState *)opaque;
/*
* PWM Read
*/
-static uint64_t exynos4210_pwm_read(void *opaque, target_phys_addr_t offset,
+static uint64_t exynos4210_pwm_read(void *opaque, hwaddr offset,
unsigned size)
{
Exynos4210PWMState *s = (Exynos4210PWMState *)opaque;
/*
* PWM Write
*/
-static void exynos4210_pwm_write(void *opaque, target_phys_addr_t offset,
+static void exynos4210_pwm_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
Exynos4210PWMState *s = (Exynos4210PWMState *)opaque;
/*
* RTC Read
*/
-static uint64_t exynos4210_rtc_read(void *opaque, target_phys_addr_t offset,
+static uint64_t exynos4210_rtc_read(void *opaque, hwaddr offset,
unsigned size)
{
uint32_t value = 0;
/*
* RTC Write
*/
-static void exynos4210_rtc_write(void *opaque, target_phys_addr_t offset,
+static void exynos4210_rtc_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
Exynos4210RTCState *s = (Exynos4210RTCState *)opaque;
typedef struct Exynos4210UartReg {
const char *name; /* the only reason is the debug output */
- target_phys_addr_t offset;
+ hwaddr offset;
uint32_t reset_value;
} Exynos4210UartReg;
#if DEBUG_UART
/* Used only for debugging inside PRINT_DEBUG_... macros */
-static const char *exynos4210_uart_regname(target_phys_addr_t offset)
+static const char *exynos4210_uart_regname(hwaddr offset)
{
int regs_number = sizeof(exynos4210_uart_regs) / sizeof(Exynos4210UartReg);
s->channel, speed, parity, data_bits, stop_bits);
}
-static void exynos4210_uart_write(void *opaque, target_phys_addr_t offset,
+static void exynos4210_uart_write(void *opaque, hwaddr offset,
uint64_t val, unsigned size)
{
Exynos4210UartState *s = (Exynos4210UartState *)opaque;
break;
}
}
-static uint64_t exynos4210_uart_read(void *opaque, target_phys_addr_t offset,
+static uint64_t exynos4210_uart_read(void *opaque, hwaddr offset,
unsigned size)
{
Exynos4210UartState *s = (Exynos4210UartState *)opaque;
}
};
-DeviceState *exynos4210_uart_create(target_phys_addr_t addr,
+DeviceState *exynos4210_uart_create(hwaddr addr,
int fifo_size,
int channel,
CharDriverState *chr,
bus = sysbus_from_qdev(dev);
qdev_init_nofail(dev);
- if (addr != (target_phys_addr_t)-1) {
+ if (addr != (hwaddr)-1) {
sysbus_mmio_map(bus, 0, addr);
}
sysbus_connect_irq(bus, 0, irq);
}
}
-static uint64_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg,
+static uint64_t fdctrl_read_mem (void *opaque, hwaddr reg,
unsigned ize)
{
return fdctrl_read(opaque, (uint32_t)reg);
}
-static void fdctrl_write_mem (void *opaque, target_phys_addr_t reg,
+static void fdctrl_write_mem (void *opaque, hwaddr reg,
uint64_t value, unsigned size)
{
fdctrl_write(opaque, (uint32_t)reg, value);
}
void fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
- target_phys_addr_t mmio_base, DriveInfo **fds)
+ hwaddr mmio_base, DriveInfo **fds)
{
FDCtrl *fdctrl;
DeviceState *dev;
sysbus_mmio_map(&sys->busdev, 0, mmio_base);
}
-void sun4m_fdctrl_init(qemu_irq irq, target_phys_addr_t io_base,
+void sun4m_fdctrl_init(qemu_irq irq, hwaddr io_base,
DriveInfo **fds, qemu_irq *fdc_tc)
{
DeviceState *dev;
ISADevice *fdctrl_init_isa(ISABus *bus, DriveInfo **fds);
void fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
- target_phys_addr_t mmio_base, DriveInfo **fds);
-void sun4m_fdctrl_init(qemu_irq irq, target_phys_addr_t io_base,
+ hwaddr mmio_base, DriveInfo **fds);
+void sun4m_fdctrl_init(qemu_irq irq, hwaddr io_base,
DriveInfo **fds, qemu_irq *fdc_tc);
FDriveType isa_fdc_get_drive_type(ISADevice *fdc, int i);
typedef struct pflash_t pflash_t;
/* pflash_cfi01.c */
-pflash_t *pflash_cfi01_register(target_phys_addr_t base,
+pflash_t *pflash_cfi01_register(hwaddr base,
DeviceState *qdev, const char *name,
- target_phys_addr_t size,
+ hwaddr size,
BlockDriverState *bs,
uint32_t sector_len, int nb_blocs, int width,
uint16_t id0, uint16_t id1,
uint16_t id2, uint16_t id3, int be);
/* pflash_cfi02.c */
-pflash_t *pflash_cfi02_register(target_phys_addr_t base,
+pflash_t *pflash_cfi02_register(hwaddr base,
DeviceState *qdev, const char *name,
- target_phys_addr_t size,
+ hwaddr size,
BlockDriverState *bs, uint32_t sector_len,
int nb_blocs, int nb_mappings, int width,
uint16_t id0, uint16_t id1,
void framebuffer_update_display(
DisplayState *ds,
MemoryRegion *address_space,
- target_phys_addr_t base,
+ hwaddr base,
int cols, /* Width in pixels. */
int rows, /* Height in pixels. */
int src_width, /* Length of source line, in bytes. */
int *first_row, /* Input and output. */
int *last_row /* Output only */)
{
- target_phys_addr_t src_len;
+ hwaddr src_len;
uint8_t *dest;
uint8_t *src;
uint8_t *src_base;
void framebuffer_update_display(
DisplayState *ds,
MemoryRegion *address_space,
- target_phys_addr_t base,
+ hwaddr base,
int cols,
int rows,
int src_width,
return ret;
}
-static uint64_t fw_cfg_data_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t fw_cfg_data_mem_read(void *opaque, hwaddr addr,
unsigned size)
{
return fw_cfg_read(opaque);
}
-static void fw_cfg_data_mem_write(void *opaque, target_phys_addr_t addr,
+static void fw_cfg_data_mem_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
fw_cfg_write(opaque, (uint8_t)value);
}
-static void fw_cfg_ctl_mem_write(void *opaque, target_phys_addr_t addr,
+static void fw_cfg_ctl_mem_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
fw_cfg_select(opaque, (uint16_t)value);
}
-static bool fw_cfg_ctl_mem_valid(void *opaque, target_phys_addr_t addr,
+static bool fw_cfg_ctl_mem_valid(void *opaque, hwaddr addr,
unsigned size, bool is_write)
{
return is_write && size == 2;
}
-static uint64_t fw_cfg_comb_read(void *opaque, target_phys_addr_t addr,
+static uint64_t fw_cfg_comb_read(void *opaque, hwaddr addr,
unsigned size)
{
return fw_cfg_read(opaque);
}
-static void fw_cfg_comb_write(void *opaque, target_phys_addr_t addr,
+static void fw_cfg_comb_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
switch (size) {
}
}
-static bool fw_cfg_comb_valid(void *opaque, target_phys_addr_t addr,
+static bool fw_cfg_comb_valid(void *opaque, hwaddr addr,
unsigned size, bool is_write)
{
return (size == 1) || (is_write && size == 2);
}
FWCfgState *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
- target_phys_addr_t ctl_addr, target_phys_addr_t data_addr)
+ hwaddr ctl_addr, hwaddr data_addr)
{
DeviceState *dev;
SysBusDevice *d;
int fw_cfg_add_file(FWCfgState *s, const char *filename, uint8_t *data,
uint32_t len);
FWCfgState *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
- target_phys_addr_t crl_addr, target_phys_addr_t data_addr);
+ hwaddr crl_addr, hwaddr data_addr);
#endif /* NO_QEMU_PROTOS */
/* called for accesses to io ports */
static uint64_t g364fb_ctrl_read(void *opaque,
- target_phys_addr_t addr,
+ hwaddr addr,
unsigned int size)
{
G364State *s = opaque;
}
static void g364fb_ctrl_write(void *opaque,
- target_phys_addr_t addr,
+ hwaddr addr,
uint64_t val,
unsigned int size)
{
void grlib_irqmp_ack(DeviceState *dev, int intno);
static inline
-DeviceState *grlib_irqmp_create(target_phys_addr_t base,
+DeviceState *grlib_irqmp_create(hwaddr base,
CPUSPARCState *env,
qemu_irq **cpu_irqs,
uint32_t nr_irqs,
/* GPTimer */
static inline
-DeviceState *grlib_gptimer_create(target_phys_addr_t base,
+DeviceState *grlib_gptimer_create(hwaddr base,
uint32_t nr_timers,
uint32_t freq,
qemu_irq *cpu_irqs,
/* APB UART */
static inline
-DeviceState *grlib_apbuart_create(target_phys_addr_t base,
+DeviceState *grlib_apbuart_create(hwaddr base,
CharDriverState *serial,
qemu_irq irq)
{
}
-static uint64_t grlib_apbuart_read(void *opaque, target_phys_addr_t addr,
+static uint64_t grlib_apbuart_read(void *opaque, hwaddr addr,
unsigned size)
{
UART *uart = opaque;
}
}
-static void grlib_apbuart_write(void *opaque, target_phys_addr_t addr,
+static void grlib_apbuart_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
UART *uart = opaque;
}
}
-static uint64_t grlib_gptimer_read(void *opaque, target_phys_addr_t addr,
+static uint64_t grlib_gptimer_read(void *opaque, hwaddr addr,
unsigned size)
{
GPTimerUnit *unit = opaque;
- target_phys_addr_t timer_addr;
+ hwaddr timer_addr;
int id;
uint32_t value = 0;
return 0;
}
-static void grlib_gptimer_write(void *opaque, target_phys_addr_t addr,
+static void grlib_gptimer_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
GPTimerUnit *unit = opaque;
- target_phys_addr_t timer_addr;
+ hwaddr timer_addr;
int id;
addr &= 0xff;
}
}
-static uint64_t grlib_irqmp_read(void *opaque, target_phys_addr_t addr,
+static uint64_t grlib_irqmp_read(void *opaque, hwaddr addr,
unsigned size)
{
IRQMP *irqmp = opaque;
return 0;
}
-static void grlib_irqmp_write(void *opaque, target_phys_addr_t addr,
+static void grlib_irqmp_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
IRQMP *irqmp = opaque;
#define GT_PCI1_SERR1MASK (0xca8 >> 2)
#define PCI_MAPPING_ENTRY(regname) \
- target_phys_addr_t regname ##_start; \
- target_phys_addr_t regname ##_length; \
+ hwaddr regname ##_start; \
+ hwaddr regname ##_length; \
MemoryRegion regname ##_mem
#define TYPE_GT64120_PCI_HOST_BRIDGE "gt64120"
/* Adjust range to avoid touching space which isn't mappable via PCI */
/* XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000
0x1fc00000 - 0x1fd00000 */
-static void check_reserved_space (target_phys_addr_t *start,
- target_phys_addr_t *length)
+static void check_reserved_space (hwaddr *start,
+ hwaddr *length)
{
- target_phys_addr_t begin = *start;
- target_phys_addr_t end = *start + *length;
+ hwaddr begin = *start;
+ hwaddr end = *start + *length;
if (end >= 0x1e000000LL && end < 0x1f100000LL)
end = 0x1e000000LL;
static void gt64120_isd_mapping(GT64120State *s)
{
- target_phys_addr_t start = s->regs[GT_ISD] << 21;
- target_phys_addr_t length = 0x1000;
+ hwaddr start = s->regs[GT_ISD] << 21;
+ hwaddr length = 0x1000;
if (s->ISD_length) {
memory_region_del_subregion(get_system_memory(), &s->ISD_mem);
}
}
-static void gt64120_writel (void *opaque, target_phys_addr_t addr,
+static void gt64120_writel (void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
GT64120State *s = opaque;
}
static uint64_t gt64120_readl (void *opaque,
- target_phys_addr_t addr, unsigned size)
+ hwaddr addr, unsigned size)
{
GT64120State *s = opaque;
PCIHostState *phb = PCI_HOST_BRIDGE(s);
}
}
-static void pic_write(void *opaque, target_phys_addr_t addr,
+static void pic_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
HeathrowPICS *s = opaque;
}
}
-static uint64_t pic_read(void *opaque, target_phys_addr_t addr,
+static uint64_t pic_read(void *opaque, hwaddr addr,
unsigned size)
{
HeathrowPICS *s = opaque;
}
#define NUM_REGS 0x200
-static void hb_regs_write(void *opaque, target_phys_addr_t offset,
+static void hb_regs_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
uint32_t *regs = opaque;
regs[offset/4] = value;
}
-static uint64_t hb_regs_read(void *opaque, target_phys_addr_t offset,
+static uint64_t hb_regs_read(void *opaque, hwaddr offset,
unsigned size)
{
uint32_t *regs = opaque;
}
#ifdef HPET_DEBUG
-static uint32_t hpet_ram_readb(void *opaque, target_phys_addr_t addr)
+static uint32_t hpet_ram_readb(void *opaque, hwaddr addr)
{
printf("qemu: hpet_read b at %" PRIx64 "\n", addr);
return 0;
}
-static uint32_t hpet_ram_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t hpet_ram_readw(void *opaque, hwaddr addr)
{
printf("qemu: hpet_read w at %" PRIx64 "\n", addr);
return 0;
}
#endif
-static uint64_t hpet_ram_read(void *opaque, target_phys_addr_t addr,
+static uint64_t hpet_ram_read(void *opaque, hwaddr addr,
unsigned size)
{
HPETState *s = opaque;
return 0;
}
-static void hpet_ram_write(void *opaque, target_phys_addr_t addr,
+static void hpet_ram_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
int i;
},
};
-static void i82378_io_write(void *opaque, target_phys_addr_t addr,
+static void i82378_io_write(void *opaque, hwaddr addr,
uint64_t value, unsigned int size)
{
switch (size) {
}
}
-static uint64_t i82378_io_read(void *opaque, target_phys_addr_t addr,
+static uint64_t i82378_io_read(void *opaque, hwaddr addr,
unsigned int size)
{
DPRINTF("%s: " TARGET_FMT_plx "\n", __func__, addr);
.endianness = DEVICE_LITTLE_ENDIAN,
};
-static void i82378_mem_write(void *opaque, target_phys_addr_t addr,
+static void i82378_mem_write(void *opaque, hwaddr addr,
uint64_t value, unsigned int size)
{
switch (size) {
}
}
-static uint64_t i82378_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t i82378_mem_read(void *opaque, hwaddr addr,
unsigned int size)
{
DPRINTF("%s: " TARGET_FMT_plx "\n", __func__, addr);
pic_init_reset(s);
}
-static void pic_ioport_write(void *opaque, target_phys_addr_t addr64,
+static void pic_ioport_write(void *opaque, hwaddr addr64,
uint64_t val64, unsigned size)
{
PICCommonState *s = opaque;
}
}
-static uint64_t pic_ioport_read(void *opaque, target_phys_addr_t addr,
+static uint64_t pic_ioport_read(void *opaque, hwaddr addr,
unsigned size)
{
PICCommonState *s = opaque;
return (pic_get_irq(s) >= 0);
}
-static void elcr_ioport_write(void *opaque, target_phys_addr_t addr,
+static void elcr_ioport_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
PICCommonState *s = opaque;
s->elcr = val & s->elcr_mask;
}
-static uint64_t elcr_ioport_read(void *opaque, target_phys_addr_t addr,
+static uint64_t elcr_ioport_read(void *opaque, hwaddr addr,
unsigned size)
{
PICCommonState *s = opaque;
void *dbdma, int channel, qemu_irq dma_irq);
/* ide-mmio.c */
-void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2,
+void mmio_ide_init (hwaddr membase, hwaddr membase2,
MemoryRegion *address_space,
qemu_irq irq, int shift,
DriveInfo *hd0, DriveInfo *hd1);
static void map_page(uint8_t **ptr, uint64_t addr, uint32_t wanted)
{
- target_phys_addr_t len = wanted;
+ hwaddr len = wanted;
if (*ptr) {
cpu_physical_memory_unmap(*ptr, len, 1, len);
}
}
-static uint64_t ahci_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t ahci_mem_read(void *opaque, hwaddr addr,
unsigned size)
{
AHCIState *s = opaque;
-static void ahci_mem_write(void *opaque, target_phys_addr_t addr,
+static void ahci_mem_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
AHCIState *s = opaque;
.endianness = DEVICE_LITTLE_ENDIAN,
};
-static uint64_t ahci_idp_read(void *opaque, target_phys_addr_t addr,
+static uint64_t ahci_idp_read(void *opaque, hwaddr addr,
unsigned size)
{
AHCIState *s = opaque;
}
}
-static void ahci_idp_write(void *opaque, target_phys_addr_t addr,
+static void ahci_idp_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
AHCIState *s = opaque;
static void cmd646_update_irq(PCIIDEState *d);
-static uint64_t cmd646_cmd_read(void *opaque, target_phys_addr_t addr,
+static uint64_t cmd646_cmd_read(void *opaque, hwaddr addr,
unsigned size)
{
CMD646BAR *cmd646bar = opaque;
return ide_status_read(cmd646bar->bus, addr + 2);
}
-static void cmd646_cmd_write(void *opaque, target_phys_addr_t addr,
+static void cmd646_cmd_write(void *opaque, hwaddr addr,
uint64_t data, unsigned size)
{
CMD646BAR *cmd646bar = opaque;
.endianness = DEVICE_LITTLE_ENDIAN,
};
-static uint64_t cmd646_data_read(void *opaque, target_phys_addr_t addr,
+static uint64_t cmd646_data_read(void *opaque, hwaddr addr,
unsigned size)
{
CMD646BAR *cmd646bar = opaque;
return ((uint64_t)1 << (size * 8)) - 1;
}
-static void cmd646_data_write(void *opaque, target_phys_addr_t addr,
+static void cmd646_data_write(void *opaque, hwaddr addr,
uint64_t data, unsigned size)
{
CMD646BAR *cmd646bar = opaque;
memory_region_init_io(&bar->data, &cmd646_data_ops, bar, "cmd646-data", 8);
}
-static uint64_t bmdma_read(void *opaque, target_phys_addr_t addr,
+static uint64_t bmdma_read(void *opaque, hwaddr addr,
unsigned size)
{
BMDMAState *bm = opaque;
return val;
}
-static void bmdma_write(void *opaque, target_phys_addr_t addr,
+static void bmdma_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
BMDMAState *bm = opaque;
/* PowerMac IDE memory IO */
static void pmac_ide_writeb (void *opaque,
- target_phys_addr_t addr, uint32_t val)
+ hwaddr addr, uint32_t val)
{
MACIOIDEState *d = opaque;
}
}
-static uint32_t pmac_ide_readb (void *opaque,target_phys_addr_t addr)
+static uint32_t pmac_ide_readb (void *opaque,hwaddr addr)
{
uint8_t retval;
MACIOIDEState *d = opaque;
}
static void pmac_ide_writew (void *opaque,
- target_phys_addr_t addr, uint32_t val)
+ hwaddr addr, uint32_t val)
{
MACIOIDEState *d = opaque;
}
}
-static uint32_t pmac_ide_readw (void *opaque,target_phys_addr_t addr)
+static uint32_t pmac_ide_readw (void *opaque,hwaddr addr)
{
uint16_t retval;
MACIOIDEState *d = opaque;
}
static void pmac_ide_writel (void *opaque,
- target_phys_addr_t addr, uint32_t val)
+ hwaddr addr, uint32_t val)
{
MACIOIDEState *d = opaque;
}
}
-static uint32_t pmac_ide_readl (void *opaque,target_phys_addr_t addr)
+static uint32_t pmac_ide_readl (void *opaque,hwaddr addr)
{
uint32_t retval;
MACIOIDEState *d = opaque;
ide_bus_reset(&s->bus);
}
-static uint64_t mmio_ide_read(void *opaque, target_phys_addr_t addr,
+static uint64_t mmio_ide_read(void *opaque, hwaddr addr,
unsigned size)
{
MMIOState *s = opaque;
return ide_data_readw(&s->bus, 0);
}
-static void mmio_ide_write(void *opaque, target_phys_addr_t addr,
+static void mmio_ide_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
MMIOState *s = opaque;
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static uint64_t mmio_ide_status_read(void *opaque, target_phys_addr_t addr,
+static uint64_t mmio_ide_status_read(void *opaque, hwaddr addr,
unsigned size)
{
MMIOState *s= opaque;
return ide_status_read(&s->bus, 0);
}
-static void mmio_ide_cmd_write(void *opaque, target_phys_addr_t addr,
+static void mmio_ide_cmd_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
MMIOState *s = opaque;
}
};
-void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2,
+void mmio_ide_init (hwaddr membase, hwaddr membase2,
MemoryRegion *address_space,
qemu_irq irq, int shift,
DriveInfo *hd0, DriveInfo *hd1)
bm->cmd = val & 0x09;
}
-static uint64_t bmdma_addr_read(void *opaque, target_phys_addr_t addr,
+static uint64_t bmdma_addr_read(void *opaque, hwaddr addr,
unsigned width)
{
BMDMAState *bm = opaque;
return data;
}
-static void bmdma_addr_write(void *opaque, target_phys_addr_t addr,
+static void bmdma_addr_write(void *opaque, hwaddr addr,
uint64_t data, unsigned width)
{
BMDMAState *bm = opaque;
#include <hw/ide/pci.h>
-static uint64_t bmdma_read(void *opaque, target_phys_addr_t addr, unsigned size)
+static uint64_t bmdma_read(void *opaque, hwaddr addr, unsigned size)
{
BMDMAState *bm = opaque;
uint32_t val;
return val;
}
-static void bmdma_write(void *opaque, target_phys_addr_t addr,
+static void bmdma_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
BMDMAState *bm = opaque;
#include <hw/ide/pci.h>
-static uint64_t bmdma_read(void *opaque, target_phys_addr_t addr,
+static uint64_t bmdma_read(void *opaque, hwaddr addr,
unsigned size)
{
BMDMAState *bm = opaque;
return val;
}
-static void bmdma_write(void *opaque, target_phys_addr_t addr,
+static void bmdma_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
BMDMAState *bm = opaque;
#ifndef IMX_H
#define IMX_H
-void imx_serial_create(int uart, const target_phys_addr_t addr, qemu_irq irq);
+void imx_serial_create(int uart, const hwaddr addr, qemu_irq irq);
typedef enum {
NOCLK,
uint32_t imx_clock_frequency(DeviceState *s, IMXClk clock);
-void imx_timerp_create(const target_phys_addr_t addr,
+void imx_timerp_create(const hwaddr addr,
qemu_irq irq,
DeviceState *ccm);
-void imx_timerg_create(const target_phys_addr_t addr,
+void imx_timerg_create(const hwaddr addr,
qemu_irq irq,
DeviceState *ccm);
static uint64_t imx_avic_read(void *opaque,
- target_phys_addr_t offset, unsigned size)
+ hwaddr offset, unsigned size)
{
IMXAVICState *s = (IMXAVICState *)opaque;
}
}
-static void imx_avic_write(void *opaque, target_phys_addr_t offset,
+static void imx_avic_write(void *opaque, hwaddr offset,
uint64_t val, unsigned size)
{
IMXAVICState *s = (IMXAVICState *)opaque;
update_clocks(s);
}
-static uint64_t imx_ccm_read(void *opaque, target_phys_addr_t offset,
+static uint64_t imx_ccm_read(void *opaque, hwaddr offset,
unsigned size)
{
IMXCCMState *s = (IMXCCMState *)opaque;
return 0;
}
-static void imx_ccm_write(void *opaque, target_phys_addr_t offset,
+static void imx_ccm_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
IMXCCMState *s = (IMXCCMState *)opaque;
}
-static uint64_t imx_serial_read(void *opaque, target_phys_addr_t offset,
+static uint64_t imx_serial_read(void *opaque, hwaddr offset,
unsigned size)
{
IMXSerialState *s = (IMXSerialState *)opaque;
}
}
-static void imx_serial_write(void *opaque, target_phys_addr_t offset,
+static void imx_serial_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
IMXSerialState *s = (IMXSerialState *)opaque;
return 0;
}
-void imx_serial_create(int uart, const target_phys_addr_t addr, qemu_irq irq)
+void imx_serial_create(int uart, const hwaddr addr, qemu_irq irq)
{
DeviceState *dev;
SysBusDevice *bus;
qdev_prop_set_chr(dev, "chardev", chr);
bus = sysbus_from_qdev(dev);
qdev_init_nofail(dev);
- if (addr != (target_phys_addr_t)-1) {
+ if (addr != (hwaddr)-1) {
sysbus_mmio_map(bus, 0, addr);
}
sysbus_connect_irq(bus, 0, irq);
ptimer_set_count(s->timer, diff_cnt);
}
-static uint64_t imx_timerg_read(void *opaque, target_phys_addr_t offset,
+static uint64_t imx_timerg_read(void *opaque, hwaddr offset,
unsigned size)
{
IMXTimerGState *s = (IMXTimerGState *)opaque;
imx_timerg_set_freq(s);
}
-static void imx_timerg_write(void *opaque, target_phys_addr_t offset,
+static void imx_timerg_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
IMXTimerGState *s = (IMXTimerGState *)opaque;
ptimer_set_count(s->timer, TIMER_MAX);
}
-static uint64_t imx_timerp_read(void *opaque, target_phys_addr_t offset,
+static uint64_t imx_timerp_read(void *opaque, hwaddr offset,
unsigned size)
{
IMXTimerPState *s = (IMXTimerPState *)opaque;
}
}
-static void imx_timerp_write(void *opaque, target_phys_addr_t offset,
+static void imx_timerp_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
IMXTimerPState *s = (IMXTimerPState *)opaque;
imx_timerp_update(s);
}
-void imx_timerp_create(const target_phys_addr_t addr,
+void imx_timerp_create(const hwaddr addr,
qemu_irq irq,
DeviceState *ccm)
{
}
-void imx_timerg_create(const target_phys_addr_t addr,
+void imx_timerg_create(const hwaddr addr,
qemu_irq irq,
DeviceState *ccm)
{
0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40
};
-static uint64_t integratorcm_read(void *opaque, target_phys_addr_t offset,
+static uint64_t integratorcm_read(void *opaque, hwaddr offset,
unsigned size)
{
integratorcm_state *s = (integratorcm_state *)opaque;
hw_error("Core module interrupt\n");
}
-static void integratorcm_write(void *opaque, target_phys_addr_t offset,
+static void integratorcm_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
integratorcm_state *s = (integratorcm_state *)opaque;
icp_pic_update(s);
}
-static uint64_t icp_pic_read(void *opaque, target_phys_addr_t offset,
+static uint64_t icp_pic_read(void *opaque, hwaddr offset,
unsigned size)
{
icp_pic_state *s = (icp_pic_state *)opaque;
}
}
-static void icp_pic_write(void *opaque, target_phys_addr_t offset,
+static void icp_pic_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
icp_pic_state *s = (icp_pic_state *)opaque;
/* CP control registers. */
-static uint64_t icp_control_read(void *opaque, target_phys_addr_t offset,
+static uint64_t icp_control_read(void *opaque, hwaddr offset,
unsigned size)
{
switch (offset >> 2) {
}
}
-static void icp_control_write(void *opaque, target_phys_addr_t offset,
+static void icp_control_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
switch (offset >> 2) {
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static void icp_control_init(target_phys_addr_t base)
+static void icp_control_init(hwaddr base)
{
MemoryRegion *io;
/* --------------------------------------------------------------------- */
-static target_phys_addr_t intel_hda_addr(uint32_t lbase, uint32_t ubase)
+static hwaddr intel_hda_addr(uint32_t lbase, uint32_t ubase)
{
- target_phys_addr_t addr;
+ hwaddr addr;
addr = ((uint64_t)ubase << 32) | lbase;
return addr;
static void intel_hda_corb_run(IntelHDAState *d)
{
- target_phys_addr_t addr;
+ hwaddr addr;
uint32_t rp, verb;
if (d->ics & ICH6_IRS_BUSY) {
{
HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
IntelHDAState *d = container_of(bus, IntelHDAState, codecs);
- target_phys_addr_t addr;
+ hwaddr addr;
uint32_t wp, ex;
if (d->ics & ICH6_IRS_BUSY) {
{
HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
IntelHDAState *d = container_of(bus, IntelHDAState, codecs);
- target_phys_addr_t addr;
+ hwaddr addr;
uint32_t s, copy, left;
IntelHDAStream *st;
bool irq = false;
static void intel_hda_parse_bdl(IntelHDAState *d, IntelHDAStream *st)
{
- target_phys_addr_t addr;
+ hwaddr addr;
uint8_t buf[16];
uint32_t i;
};
-static const IntelHDAReg *intel_hda_reg_find(IntelHDAState *d, target_phys_addr_t addr)
+static const IntelHDAReg *intel_hda_reg_find(IntelHDAState *d, hwaddr addr)
{
const IntelHDAReg *reg;
/* --------------------------------------------------------------------- */
-static void intel_hda_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void intel_hda_mmio_writeb(void *opaque, hwaddr addr, uint32_t val)
{
IntelHDAState *d = opaque;
const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
intel_hda_reg_write(d, reg, val, 0xff);
}
-static void intel_hda_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void intel_hda_mmio_writew(void *opaque, hwaddr addr, uint32_t val)
{
IntelHDAState *d = opaque;
const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
intel_hda_reg_write(d, reg, val, 0xffff);
}
-static void intel_hda_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void intel_hda_mmio_writel(void *opaque, hwaddr addr, uint32_t val)
{
IntelHDAState *d = opaque;
const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
intel_hda_reg_write(d, reg, val, 0xffffffff);
}
-static uint32_t intel_hda_mmio_readb(void *opaque, target_phys_addr_t addr)
+static uint32_t intel_hda_mmio_readb(void *opaque, hwaddr addr)
{
IntelHDAState *d = opaque;
const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
return intel_hda_reg_read(d, reg, 0xff);
}
-static uint32_t intel_hda_mmio_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t intel_hda_mmio_readw(void *opaque, hwaddr addr)
{
IntelHDAState *d = opaque;
const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
return intel_hda_reg_read(d, reg, 0xffff);
}
-static uint32_t intel_hda_mmio_readl(void *opaque, target_phys_addr_t addr)
+static uint32_t intel_hda_mmio_readl(void *opaque, hwaddr addr)
{
IntelHDAState *d = opaque;
const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
}
static uint64_t
-ioapic_mem_read(void *opaque, target_phys_addr_t addr, unsigned int size)
+ioapic_mem_read(void *opaque, hwaddr addr, unsigned int size)
{
IOAPICCommonState *s = opaque;
int index;
}
static void
-ioapic_mem_write(void *opaque, target_phys_addr_t addr, uint64_t val,
+ioapic_mem_write(void *opaque, hwaddr addr, uint64_t val,
unsigned int size)
{
IOAPICCommonState *s = opaque;
#include "exec-memory.h"
static ISABus *isabus;
-target_phys_addr_t isa_mem_base = 0;
+hwaddr isa_mem_base = 0;
static void isabus_dev_print(Monitor *mon, DeviceState *dev, int indent);
static char *isabus_get_fw_dev_path(DeviceState *dev);
return DO_UPCAST(ISABus, qbus, d->qdev.parent_bus);
}
-extern target_phys_addr_t isa_mem_base;
+extern hwaddr isa_mem_base;
-void isa_mmio_setup(MemoryRegion *mr, target_phys_addr_t size);
-void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
+void isa_mmio_setup(MemoryRegion *mr, hwaddr size);
+void isa_mmio_init(hwaddr base, hwaddr size);
/* dma.c */
int DMA_get_channel_mode (int nchan);
#include "isa.h"
#include "exec-memory.h"
-static void isa_mmio_writeb (void *opaque, target_phys_addr_t addr,
+static void isa_mmio_writeb (void *opaque, hwaddr addr,
uint32_t val)
{
cpu_outb(addr & IOPORTS_MASK, val);
}
-static void isa_mmio_writew(void *opaque, target_phys_addr_t addr,
+static void isa_mmio_writew(void *opaque, hwaddr addr,
uint32_t val)
{
cpu_outw(addr & IOPORTS_MASK, val);
}
-static void isa_mmio_writel(void *opaque, target_phys_addr_t addr,
+static void isa_mmio_writel(void *opaque, hwaddr addr,
uint32_t val)
{
cpu_outl(addr & IOPORTS_MASK, val);
}
-static uint32_t isa_mmio_readb (void *opaque, target_phys_addr_t addr)
+static uint32_t isa_mmio_readb (void *opaque, hwaddr addr)
{
return cpu_inb(addr & IOPORTS_MASK);
}
-static uint32_t isa_mmio_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t isa_mmio_readw(void *opaque, hwaddr addr)
{
return cpu_inw(addr & IOPORTS_MASK);
}
-static uint32_t isa_mmio_readl(void *opaque, target_phys_addr_t addr)
+static uint32_t isa_mmio_readl(void *opaque, hwaddr addr)
{
return cpu_inl(addr & IOPORTS_MASK);
}
.endianness = DEVICE_LITTLE_ENDIAN,
};
-void isa_mmio_setup(MemoryRegion *mr, target_phys_addr_t size)
+void isa_mmio_setup(MemoryRegion *mr, hwaddr size)
{
memory_region_init_io(mr, &isa_mmio_ops, NULL, "isa-mmio", size);
}
-void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size)
+void isa_mmio_init(hwaddr base, hwaddr size)
{
MemoryRegion *mr = g_malloc(sizeof(*mr));
return ret;
}
-static void ivshmem_io_write(void *opaque, target_phys_addr_t addr,
+static void ivshmem_io_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
IVShmemState *s = opaque;
}
}
-static uint64_t ivshmem_io_read(void *opaque, target_phys_addr_t addr,
+static uint64_t ivshmem_io_read(void *opaque, hwaddr addr,
unsigned size)
{
screen_state_t state;
} LedState;
-static uint64_t jazz_led_read(void *opaque, target_phys_addr_t addr,
+static uint64_t jazz_led_read(void *opaque, hwaddr addr,
unsigned int size)
{
LedState *s = opaque;
return val;
}
-static void jazz_led_write(void *opaque, target_phys_addr_t addr,
+static void jazz_led_write(void *opaque, hwaddr addr,
uint64_t val, unsigned int size)
{
LedState *s = opaque;
run_on_cpu(s->cpu_env, do_inject_external_nmi, s);
}
-static uint64_t kvm_apic_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t kvm_apic_mem_read(void *opaque, hwaddr addr,
unsigned size)
{
return ~(uint64_t)0;
}
-static void kvm_apic_mem_write(void *opaque, target_phys_addr_t addr,
+static void kvm_apic_mem_write(void *opaque, hwaddr addr,
uint64_t data, unsigned size)
{
MSIMessage msg = { .address = addr, .data = data };
int msi_virq_nr;
int *msi_virq;
MSIXTableEntry *msix_table;
- target_phys_addr_t msix_table_addr;
+ hwaddr msix_table_addr;
uint16_t msix_max;
MemoryRegion mmio;
char *configfd_name;
static void assigned_dev_unregister_msix_mmio(AssignedDevice *dev);
static uint64_t assigned_dev_ioport_rw(AssignedDevRegion *dev_region,
- target_phys_addr_t addr, int size,
+ hwaddr addr, int size,
uint64_t *data)
{
uint64_t val = 0;
return val;
}
-static void assigned_dev_ioport_write(void *opaque, target_phys_addr_t addr,
+static void assigned_dev_ioport_write(void *opaque, hwaddr addr,
uint64_t data, unsigned size)
{
assigned_dev_ioport_rw(opaque, addr, size, &data);
}
static uint64_t assigned_dev_ioport_read(void *opaque,
- target_phys_addr_t addr, unsigned size)
+ hwaddr addr, unsigned size)
{
return assigned_dev_ioport_rw(opaque, addr, size, NULL);
}
-static uint32_t slow_bar_readb(void *opaque, target_phys_addr_t addr)
+static uint32_t slow_bar_readb(void *opaque, hwaddr addr)
{
AssignedDevRegion *d = opaque;
uint8_t *in = d->u.r_virtbase + addr;
return r;
}
-static uint32_t slow_bar_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t slow_bar_readw(void *opaque, hwaddr addr)
{
AssignedDevRegion *d = opaque;
uint16_t *in = (uint16_t *)(d->u.r_virtbase + addr);
return r;
}
-static uint32_t slow_bar_readl(void *opaque, target_phys_addr_t addr)
+static uint32_t slow_bar_readl(void *opaque, hwaddr addr)
{
AssignedDevRegion *d = opaque;
uint32_t *in = (uint32_t *)(d->u.r_virtbase + addr);
return r;
}
-static void slow_bar_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void slow_bar_writeb(void *opaque, hwaddr addr, uint32_t val)
{
AssignedDevRegion *d = opaque;
uint8_t *out = d->u.r_virtbase + addr;
*out = val;
}
-static void slow_bar_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void slow_bar_writew(void *opaque, hwaddr addr, uint32_t val)
{
AssignedDevRegion *d = opaque;
uint16_t *out = (uint16_t *)(d->u.r_virtbase + addr);
*out = val;
}
-static void slow_bar_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void slow_bar_writel(void *opaque, hwaddr addr, uint32_t val)
{
AssignedDevRegion *d = opaque;
uint32_t *out = (uint32_t *)(d->u.r_virtbase + addr);
}
static uint64_t
-assigned_dev_msix_mmio_read(void *opaque, target_phys_addr_t addr,
+assigned_dev_msix_mmio_read(void *opaque, hwaddr addr,
unsigned size)
{
AssignedDevice *adev = opaque;
return val;
}
-static void assigned_dev_msix_mmio_write(void *opaque, target_phys_addr_t addr,
+static void assigned_dev_msix_mmio_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
AssignedDevice *adev = opaque;
static int find_real_tpr_addr(VAPICROMState *s, CPUX86State *env)
{
- target_phys_addr_t paddr;
+ hwaddr paddr;
target_ulong addr;
if (s->state == VAPIC_ACTIVE) {
static int update_rom_mapping(VAPICROMState *s, CPUX86State *env, target_ulong ip)
{
- target_phys_addr_t paddr;
+ hwaddr paddr;
uint32_t rom_state_vaddr;
uint32_t pos, patch, offset;
static int vapic_enable(VAPICROMState *s, CPUX86State *env)
{
int cpu_number = get_kpcr_number(env);
- target_phys_addr_t vapic_paddr;
+ hwaddr vapic_paddr;
static const uint8_t enabled = 1;
if (cpu_number < 0) {
return -1;
}
vapic_paddr = s->vapic_paddr +
- (((target_phys_addr_t)cpu_number) << VAPIC_CPU_SHIFT);
+ (((hwaddr)cpu_number) << VAPIC_CPU_SHIFT);
cpu_physical_memory_rw(vapic_paddr + offsetof(VAPICState, enabled),
(void *)&enabled, sizeof(enabled), 1);
apic_enable_vapic(env->apic_state, vapic_paddr);
static void patch_instruction(VAPICROMState *s, CPUX86State *env, target_ulong ip)
{
- target_phys_addr_t paddr;
+ hwaddr paddr;
VAPICHandlers *handlers;
uint8_t opcode[2];
uint32_t imm32;
*/
static int patch_hypercalls(VAPICROMState *s)
{
- target_phys_addr_t rom_paddr = s->rom_state_paddr & ROM_BLOCK_MASK;
+ hwaddr rom_paddr = s->rom_state_paddr & ROM_BLOCK_MASK;
static const uint8_t vmcall_pattern[] = { /* vmcall */
0xb8, 0x1, 0, 0, 0, 0xf, 0x1, 0xc1
};
*/
static void vapic_map_rom_writable(VAPICROMState *s)
{
- target_phys_addr_t rom_paddr = s->rom_state_paddr & ROM_BLOCK_MASK;
+ hwaddr rom_paddr = s->rom_state_paddr & ROM_BLOCK_MASK;
MemoryRegionSection section;
MemoryRegion *as;
size_t rom_size;
return 0;
}
-static void vapic_write(void *opaque, target_phys_addr_t addr, uint64_t data,
+static void vapic_write(void *opaque, hwaddr addr, uint64_t data,
unsigned int size)
{
CPUX86State *env = cpu_single_env;
- target_phys_addr_t rom_paddr;
+ hwaddr rom_paddr;
VAPICROMState *s = opaque;
cpu_synchronize_state(env);
lan9118_update(s);
}
-static void lan9118_writel(void *opaque, target_phys_addr_t offset,
+static void lan9118_writel(void *opaque, hwaddr offset,
uint64_t val, unsigned size)
{
lan9118_state *s = (lan9118_state *)opaque;
lan9118_update(s);
}
-static void lan9118_writew(void *opaque, target_phys_addr_t offset,
+static void lan9118_writew(void *opaque, hwaddr offset,
uint32_t val)
{
lan9118_state *s = (lan9118_state *)opaque;
}
}
-static void lan9118_16bit_mode_write(void *opaque, target_phys_addr_t offset,
+static void lan9118_16bit_mode_write(void *opaque, hwaddr offset,
uint64_t val, unsigned size)
{
switch (size) {
hw_error("lan9118_write: Bad size 0x%x\n", size);
}
-static uint64_t lan9118_readl(void *opaque, target_phys_addr_t offset,
+static uint64_t lan9118_readl(void *opaque, hwaddr offset,
unsigned size)
{
lan9118_state *s = (lan9118_state *)opaque;
return 0;
}
-static uint32_t lan9118_readw(void *opaque, target_phys_addr_t offset)
+static uint32_t lan9118_readw(void *opaque, hwaddr offset)
{
lan9118_state *s = (lan9118_state *)opaque;
uint32_t val;
return val;
}
-static uint64_t lan9118_16bit_mode_read(void *opaque, target_phys_addr_t offset,
+static uint64_t lan9118_16bit_mode_read(void *opaque, hwaddr offset,
unsigned size)
{
switch (size) {
pcnet_h_reset(&d->state);
}
-static void lance_mem_write(void *opaque, target_phys_addr_t addr,
+static void lance_mem_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
SysBusPCNetState *d = opaque;
pcnet_ioport_writew(&d->state, addr, val & 0xffff);
}
-static uint64_t lance_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t lance_mem_read(void *opaque, hwaddr addr,
unsigned size)
{
SysBusPCNetState *d = opaque;
typedef struct {
LM32CPU *cpu;
- target_phys_addr_t bootstrap_pc;
- target_phys_addr_t flash_base;
- target_phys_addr_t hwsetup_base;
- target_phys_addr_t initrd_base;
+ hwaddr bootstrap_pc;
+ hwaddr flash_base;
+ hwaddr hwsetup_base;
+ hwaddr initrd_base;
size_t initrd_size;
- target_phys_addr_t cmdline_base;
+ hwaddr cmdline_base;
} ResetInfo;
static void cpu_irq_handler(void *opaque, int irq, int level)
int i;
/* memory map */
- target_phys_addr_t flash_base = 0x04000000;
+ hwaddr flash_base = 0x04000000;
size_t flash_sector_size = 256 * 1024;
size_t flash_size = 32 * 1024 * 1024;
- target_phys_addr_t ram_base = 0x08000000;
+ hwaddr ram_base = 0x08000000;
size_t ram_size = 64 * 1024 * 1024;
- target_phys_addr_t timer0_base = 0x80002000;
- target_phys_addr_t uart0_base = 0x80006000;
- target_phys_addr_t timer1_base = 0x8000a000;
+ hwaddr timer0_base = 0x80002000;
+ hwaddr uart0_base = 0x80006000;
+ hwaddr timer1_base = 0x8000a000;
int uart0_irq = 0;
int timer0_irq = 1;
int timer1_irq = 3;
int i;
/* memory map */
- target_phys_addr_t flash_base = 0x04000000;
+ hwaddr flash_base = 0x04000000;
size_t flash_sector_size = 256 * 1024;
size_t flash_size = 32 * 1024 * 1024;
- target_phys_addr_t ram_base = 0x08000000;
+ hwaddr ram_base = 0x08000000;
size_t ram_size = 64 * 1024 * 1024;
- target_phys_addr_t uart0_base = 0x80000000;
- target_phys_addr_t timer0_base = 0x80002000;
- target_phys_addr_t timer1_base = 0x80010000;
- target_phys_addr_t timer2_base = 0x80012000;
+ hwaddr uart0_base = 0x80000000;
+ hwaddr timer0_base = 0x80002000;
+ hwaddr timer1_base = 0x80010000;
+ hwaddr timer2_base = 0x80012000;
int uart0_irq = 0;
int timer0_irq = 1;
int timer1_irq = 20;
int timer2_irq = 21;
- target_phys_addr_t hwsetup_base = 0x0bffe000;
- target_phys_addr_t cmdline_base = 0x0bfff000;
- target_phys_addr_t initrd_base = 0x08400000;
+ hwaddr hwsetup_base = 0x0bffe000;
+ hwaddr cmdline_base = 0x0bfff000;
+ hwaddr initrd_base = 0x08400000;
size_t initrd_max = 0x01000000;
reset_info = g_malloc0(sizeof(ResetInfo));
}
static inline void hwsetup_create_rom(HWSetup *hw,
- target_phys_addr_t base)
+ hwaddr base)
{
rom_add_blob("hwsetup", hw->data, TARGET_PAGE_SIZE, base);
}
s->testname[MAX_TESTNAME_LEN - 1] = '\0';
}
-static void sys_write(void *opaque, target_phys_addr_t addr,
+static void sys_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
LM32SysState *s = opaque;
}
}
-static bool sys_ops_accepts(void *opaque, target_phys_addr_t addr,
+static bool sys_ops_accepts(void *opaque, hwaddr addr,
unsigned size, bool is_write)
{
return is_write && size == 4;
qemu_set_irq(s->irq, state);
}
-static uint64_t timer_read(void *opaque, target_phys_addr_t addr, unsigned size)
+static uint64_t timer_read(void *opaque, hwaddr addr, unsigned size)
{
LM32TimerState *s = opaque;
uint32_t r = 0;
return r;
}
-static void timer_write(void *opaque, target_phys_addr_t addr,
+static void timer_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
LM32TimerState *s = opaque;
qemu_set_irq(s->irq, irq);
}
-static uint64_t uart_read(void *opaque, target_phys_addr_t addr,
+static uint64_t uart_read(void *opaque, hwaddr addr,
unsigned size)
{
LM32UartState *s = opaque;
return r;
}
-static void uart_write(void *opaque, target_phys_addr_t addr,
+static void uart_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
LM32UartState *s = opaque;
}
}
-uint32_t lm4549_read(lm4549_state *s, target_phys_addr_t offset)
+uint32_t lm4549_read(lm4549_state *s, hwaddr offset)
{
uint16_t *regfile = s->regfile;
uint32_t value = 0;
}
void lm4549_write(lm4549_state *s,
- target_phys_addr_t offset, uint32_t value)
+ hwaddr offset, uint32_t value)
{
uint16_t *regfile = s->regfile;
void lm4549_init(lm4549_state *s, lm4549_callback data_req, void *opaque);
-uint32_t lm4549_read(lm4549_state *s, target_phys_addr_t offset);
-void lm4549_write(lm4549_state *s, target_phys_addr_t offset, uint32_t value);
+uint32_t lm4549_read(lm4549_state *s, hwaddr offset);
+void lm4549_write(lm4549_state *s, hwaddr offset, uint32_t value);
uint32_t lm4549_write_samples(lm4549_state *s, uint32_t left, uint32_t right);
#endif /* #ifndef HW_LM4549_H */
/* read()-like version */
ssize_t read_targphys(const char *name,
- int fd, target_phys_addr_t dst_addr, size_t nbytes)
+ int fd, hwaddr dst_addr, size_t nbytes)
{
uint8_t *buf;
ssize_t did;
/* return the size or -1 if error */
int load_image_targphys(const char *filename,
- target_phys_addr_t addr, uint64_t max_sz)
+ hwaddr addr, uint64_t max_sz)
{
int size;
return size;
}
-void pstrcpy_targphys(const char *name, target_phys_addr_t dest, int buf_size,
+void pstrcpy_targphys(const char *name, hwaddr dest, int buf_size,
const char *source)
{
const char *nulp;
: (_N_SEGMENT_ROUND (_N_TXTENDADDR(x, target_page_size), target_page_size)))
-int load_aout(const char *filename, target_phys_addr_t addr, int max_sz,
- int bswap_needed, target_phys_addr_t target_page_size)
+int load_aout(const char *filename, hwaddr addr, int max_sz,
+ int bswap_needed, hwaddr target_page_size)
{
int fd;
ssize_t size, ret;
}
/* Load a U-Boot image. */
-int load_uimage(const char *filename, target_phys_addr_t *ep,
- target_phys_addr_t *loadaddr, int *is_linux)
+int load_uimage(const char *filename, hwaddr *ep,
+ hwaddr *loadaddr, int *is_linux)
{
int fd;
int size;
char *fw_dir;
char *fw_file;
- target_phys_addr_t addr;
+ hwaddr addr;
QTAILQ_ENTRY(Rom) next;
};
}
int rom_add_file(const char *file, const char *fw_dir,
- target_phys_addr_t addr, int32_t bootindex)
+ hwaddr addr, int32_t bootindex)
{
Rom *rom;
int rc, fd = -1;
}
int rom_add_blob(const char *name, const void *blob, size_t len,
- target_phys_addr_t addr)
+ hwaddr addr)
{
Rom *rom;
int rom_load_all(void)
{
- target_phys_addr_t addr = 0;
+ hwaddr addr = 0;
MemoryRegionSection section;
Rom *rom;
fw_cfg = f;
}
-static Rom *find_rom(target_phys_addr_t addr)
+static Rom *find_rom(hwaddr addr)
{
Rom *rom;
* a ROM between addr and addr + size is copied. Note that this can involve
* multiple ROMs, which need not start at addr and need not end at addr + size.
*/
-int rom_copy(uint8_t *dest, target_phys_addr_t addr, size_t size)
+int rom_copy(uint8_t *dest, hwaddr addr, size_t size)
{
- target_phys_addr_t end = addr + size;
+ hwaddr end = addr + size;
uint8_t *s, *d = dest;
size_t l = 0;
Rom *rom;
return (d + l) - dest;
}
-void *rom_ptr(target_phys_addr_t addr)
+void *rom_ptr(hwaddr addr)
{
Rom *rom;
/* loader.c */
int get_image_size(const char *filename);
int load_image(const char *filename, uint8_t *addr); /* deprecated */
-int load_image_targphys(const char *filename, target_phys_addr_t,
+int load_image_targphys(const char *filename, hwaddr,
uint64_t max_sz);
int load_elf(const char *filename, uint64_t (*translate_fn)(void *, uint64_t),
void *translate_opaque, uint64_t *pentry, uint64_t *lowaddr,
uint64_t *highaddr, int big_endian, int elf_machine,
int clear_lsb);
-int load_aout(const char *filename, target_phys_addr_t addr, int max_sz,
- int bswap_needed, target_phys_addr_t target_page_size);
-int load_uimage(const char *filename, target_phys_addr_t *ep,
- target_phys_addr_t *loadaddr, int *is_linux);
+int load_aout(const char *filename, hwaddr addr, int max_sz,
+ int bswap_needed, hwaddr target_page_size);
+int load_uimage(const char *filename, hwaddr *ep,
+ hwaddr *loadaddr, int *is_linux);
ssize_t read_targphys(const char *name,
- int fd, target_phys_addr_t dst_addr, size_t nbytes);
+ int fd, hwaddr dst_addr, size_t nbytes);
void pstrcpy_targphys(const char *name,
- target_phys_addr_t dest, int buf_size,
+ hwaddr dest, int buf_size,
const char *source);
int rom_add_file(const char *file, const char *fw_dir,
- target_phys_addr_t addr, int32_t bootindex);
+ hwaddr addr, int32_t bootindex);
int rom_add_blob(const char *name, const void *blob, size_t len,
- target_phys_addr_t addr);
+ hwaddr addr);
int rom_load_all(void);
void rom_set_fw(void *f);
-int rom_copy(uint8_t *dest, target_phys_addr_t addr, size_t size);
-void *rom_ptr(target_phys_addr_t addr);
+int rom_copy(uint8_t *dest, hwaddr addr, size_t size);
+void *rom_ptr(hwaddr addr);
void do_info_roms(Monitor *mon);
#define rom_add_file_fixed(_f, _a, _i) \
#undef CASE_SET_REG32
}
-static void lsi_mmio_write(void *opaque, target_phys_addr_t addr,
+static void lsi_mmio_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
LSIState *s = opaque;
lsi_reg_writeb(s, addr & 0xff, val);
}
-static uint64_t lsi_mmio_read(void *opaque, target_phys_addr_t addr,
+static uint64_t lsi_mmio_read(void *opaque, hwaddr addr,
unsigned size)
{
LSIState *s = opaque;
},
};
-static void lsi_ram_write(void *opaque, target_phys_addr_t addr,
+static void lsi_ram_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
LSIState *s = opaque;
s->script_ram[addr >> 2] = newval;
}
-static uint64_t lsi_ram_read(void *opaque, target_phys_addr_t addr,
+static uint64_t lsi_ram_read(void *opaque, hwaddr addr,
unsigned size)
{
LSIState *s = opaque;
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static uint64_t lsi_io_read(void *opaque, target_phys_addr_t addr,
+static uint64_t lsi_io_read(void *opaque, hwaddr addr,
unsigned size)
{
LSIState *s = opaque;
return lsi_reg_readb(s, addr & 0xff);
}
-static void lsi_io_write(void *opaque, target_phys_addr_t addr,
+static void lsi_io_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
LSIState *s = opaque;
return retval;
}
-static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
+static void nvram_writeb (void *opaque, hwaddr addr, uint32_t value)
{
M48t59State *NVRAM = opaque;
m48t59_write(NVRAM, addr, value & 0xff);
}
-static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
+static void nvram_writew (void *opaque, hwaddr addr, uint32_t value)
{
M48t59State *NVRAM = opaque;
m48t59_write(NVRAM, addr + 1, value & 0xff);
}
-static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
+static void nvram_writel (void *opaque, hwaddr addr, uint32_t value)
{
M48t59State *NVRAM = opaque;
m48t59_write(NVRAM, addr + 3, value & 0xff);
}
-static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
+static uint32_t nvram_readb (void *opaque, hwaddr addr)
{
M48t59State *NVRAM = opaque;
uint32_t retval;
return retval;
}
-static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr)
+static uint32_t nvram_readw (void *opaque, hwaddr addr)
{
M48t59State *NVRAM = opaque;
uint32_t retval;
return retval;
}
-static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr)
+static uint32_t nvram_readl (void *opaque, hwaddr addr)
{
M48t59State *NVRAM = opaque;
uint32_t retval;
};
/* Initialisation routine */
-M48t59State *m48t59_init(qemu_irq IRQ, target_phys_addr_t mem_base,
+M48t59State *m48t59_init(qemu_irq IRQ, hwaddr mem_base,
uint32_t io_base, uint16_t size, int model)
{
DeviceState *dev;
ch->flush(&ch->io);
}
-static void dbdma_write(void *opaque, target_phys_addr_t addr,
+static void dbdma_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
int channel = addr >> DBDMA_CHANNEL_SHIFT;
}
}
-static uint64_t dbdma_read(void *opaque, target_phys_addr_t addr,
+static uint64_t dbdma_read(void *opaque, hwaddr addr,
unsigned size)
{
uint32_t value;
struct DBDMA_io {
void *opaque;
void *channel;
- target_phys_addr_t addr;
+ hwaddr addr;
int len;
int is_last;
int is_dma_out;
}
/* macio style NVRAM device */
-static void macio_nvram_writeb(void *opaque, target_phys_addr_t addr,
+static void macio_nvram_writeb(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
MacIONVRAMState *s = opaque;
NVR_DPRINTF("writeb addr %04x val %x\n", (int)addr, value);
}
-static uint64_t macio_nvram_readb(void *opaque, target_phys_addr_t addr,
+static uint64_t macio_nvram_readb(void *opaque, hwaddr addr,
unsigned size)
{
MacIONVRAMState *s = opaque;
{
}
-MacIONVRAMState *macio_nvram_init (target_phys_addr_t size,
+MacIONVRAMState *macio_nvram_init (hwaddr size,
unsigned int it_shift)
{
MacIONVRAMState *s;
}
void macio_nvram_setup_bar(MacIONVRAMState *s, MemoryRegion *bar,
- target_phys_addr_t mem_base)
+ hwaddr mem_base)
{
memory_region_add_subregion(bar, mem_base, &s->mem);
}
const char *cpu_model, enum mainstone_model_e model, int arm_id)
{
uint32_t sector_len = 256 * 1024;
- target_phys_addr_t mainstone_flash_base[] = { MST_FLASH_0, MST_FLASH_1 };
+ hwaddr mainstone_flash_base[] = { MST_FLASH_0, MST_FLASH_1 };
PXA2xxState *mpu;
DeviceState *mst_irq;
DriveInfo *dinfo;
wm8750_set_bclk_in(s->wm, rate);
}
-static uint64_t mv88w8618_audio_read(void *opaque, target_phys_addr_t offset,
+static uint64_t mv88w8618_audio_read(void *opaque, hwaddr offset,
unsigned size)
{
mv88w8618_audio_state *s = opaque;
}
}
-static void mv88w8618_audio_write(void *opaque, target_phys_addr_t offset,
+static void mv88w8618_audio_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
mv88w8618_audio_state *s = opaque;
struct MemoryRegion;
/* mcf_uart.c */
-uint64_t mcf_uart_read(void *opaque, target_phys_addr_t addr,
+uint64_t mcf_uart_read(void *opaque, hwaddr addr,
unsigned size);
-void mcf_uart_write(void *opaque, target_phys_addr_t addr,
+void mcf_uart_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size);
void *mcf_uart_init(qemu_irq irq, CharDriverState *chr);
void mcf_uart_mm_init(struct MemoryRegion *sysmem,
- target_phys_addr_t base,
+ hwaddr base,
qemu_irq irq, CharDriverState *chr);
/* mcf_intc.c */
qemu_irq *mcf_intc_init(struct MemoryRegion *sysmem,
- target_phys_addr_t base,
+ hwaddr base,
CPUM68KState *env);
/* mcf_fec.c */
void mcf_fec_init(struct MemoryRegion *sysmem, NICInfo *nd,
- target_phys_addr_t base, qemu_irq *irq);
+ hwaddr base, qemu_irq *irq);
/* mcf5206.c */
qemu_irq *mcf5206_init(struct MemoryRegion *sysmem,
/* 1c0-200 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
};
-static uint32_t m5206_mbar_readw(void *opaque, target_phys_addr_t offset);
-static uint32_t m5206_mbar_readl(void *opaque, target_phys_addr_t offset);
+static uint32_t m5206_mbar_readw(void *opaque, hwaddr offset);
+static uint32_t m5206_mbar_readl(void *opaque, hwaddr offset);
-static uint32_t m5206_mbar_readb(void *opaque, target_phys_addr_t offset)
+static uint32_t m5206_mbar_readb(void *opaque, hwaddr offset)
{
m5206_mbar_state *s = (m5206_mbar_state *)opaque;
offset &= 0x3ff;
return m5206_mbar_read(s, offset, 1);
}
-static uint32_t m5206_mbar_readw(void *opaque, target_phys_addr_t offset)
+static uint32_t m5206_mbar_readw(void *opaque, hwaddr offset)
{
m5206_mbar_state *s = (m5206_mbar_state *)opaque;
int width;
return m5206_mbar_read(s, offset, 2);
}
-static uint32_t m5206_mbar_readl(void *opaque, target_phys_addr_t offset)
+static uint32_t m5206_mbar_readl(void *opaque, hwaddr offset)
{
m5206_mbar_state *s = (m5206_mbar_state *)opaque;
int width;
return m5206_mbar_read(s, offset, 4);
}
-static void m5206_mbar_writew(void *opaque, target_phys_addr_t offset,
+static void m5206_mbar_writew(void *opaque, hwaddr offset,
uint32_t value);
-static void m5206_mbar_writel(void *opaque, target_phys_addr_t offset,
+static void m5206_mbar_writel(void *opaque, hwaddr offset,
uint32_t value);
-static void m5206_mbar_writeb(void *opaque, target_phys_addr_t offset,
+static void m5206_mbar_writeb(void *opaque, hwaddr offset,
uint32_t value)
{
m5206_mbar_state *s = (m5206_mbar_state *)opaque;
m5206_mbar_write(s, offset, value, 1);
}
-static void m5206_mbar_writew(void *opaque, target_phys_addr_t offset,
+static void m5206_mbar_writew(void *opaque, hwaddr offset,
uint32_t value)
{
m5206_mbar_state *s = (m5206_mbar_state *)opaque;
m5206_mbar_write(s, offset, value, 2);
}
-static void m5206_mbar_writel(void *opaque, target_phys_addr_t offset,
+static void m5206_mbar_writel(void *opaque, hwaddr offset,
uint32_t value)
{
m5206_mbar_state *s = (m5206_mbar_state *)opaque;
qemu_irq_lower(s->irq);
}
-static void m5208_timer_write(void *opaque, target_phys_addr_t offset,
+static void m5208_timer_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
m5208_timer_state *s = (m5208_timer_state *)opaque;
m5208_timer_update(s);
}
-static uint64_t m5208_timer_read(void *opaque, target_phys_addr_t addr,
+static uint64_t m5208_timer_read(void *opaque, hwaddr addr,
unsigned size)
{
m5208_timer_state *s = (m5208_timer_state *)opaque;
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static uint64_t m5208_sys_read(void *opaque, target_phys_addr_t addr,
+static uint64_t m5208_sys_read(void *opaque, hwaddr addr,
unsigned size)
{
switch (addr) {
}
}
-static void m5208_sys_write(void *opaque, target_phys_addr_t addr,
+static void m5208_sys_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
hw_error("m5208_sys_write: Bad offset 0x%x\n", (int)addr);
CPUM68KState *env;
int kernel_size;
uint64_t elf_entry;
- target_phys_addr_t entry;
+ hwaddr entry;
qemu_irq *pic;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
s->rfsr = 0x500;
}
-static uint64_t mcf_fec_read(void *opaque, target_phys_addr_t addr,
+static uint64_t mcf_fec_read(void *opaque, hwaddr addr,
unsigned size)
{
mcf_fec_state *s = (mcf_fec_state *)opaque;
}
}
-static void mcf_fec_write(void *opaque, target_phys_addr_t addr,
+static void mcf_fec_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
mcf_fec_state *s = (mcf_fec_state *)opaque;
};
void mcf_fec_init(MemoryRegion *sysmem, NICInfo *nd,
- target_phys_addr_t base, qemu_irq *irq)
+ hwaddr base, qemu_irq *irq)
{
mcf_fec_state *s;
m68k_set_irq_level(s->env, best_level, s->active_vector);
}
-static uint64_t mcf_intc_read(void *opaque, target_phys_addr_t addr,
+static uint64_t mcf_intc_read(void *opaque, hwaddr addr,
unsigned size)
{
int offset;
}
}
-static void mcf_intc_write(void *opaque, target_phys_addr_t addr,
+static void mcf_intc_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
int offset;
};
qemu_irq *mcf_intc_init(MemoryRegion *sysmem,
- target_phys_addr_t base,
+ hwaddr base,
CPUM68KState *env)
{
mcf_intc_state *s;
qemu_set_irq(s->irq, (s->isr & s->imr) != 0);
}
-uint64_t mcf_uart_read(void *opaque, target_phys_addr_t addr,
+uint64_t mcf_uart_read(void *opaque, hwaddr addr,
unsigned size)
{
mcf_uart_state *s = (mcf_uart_state *)opaque;
}
}
-void mcf_uart_write(void *opaque, target_phys_addr_t addr,
+void mcf_uart_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
mcf_uart_state *s = (mcf_uart_state *)opaque;
};
void mcf_uart_mm_init(MemoryRegion *sysmem,
- target_phys_addr_t base,
+ hwaddr base,
qemu_irq irq,
CharDriverState *chr)
{
uint16_t count;
uint64_t context;
- target_phys_addr_t pa;
- target_phys_addr_t pa_size;
+ hwaddr pa;
+ hwaddr pa_size;
union mfi_frame *frame;
SCSIRequest *req;
QEMUSGList qsg;
uint8_t sense_len)
{
uint32_t pa_hi = 0, pa_lo;
- target_phys_addr_t pa;
+ hwaddr pa;
if (sense_len > cmd->frame->header.sense_len) {
sense_len = cmd->frame->header.sense_len;
}
static MegasasCmd *megasas_lookup_frame(MegasasState *s,
- target_phys_addr_t frame)
+ hwaddr frame)
{
MegasasCmd *cmd = NULL;
int num = 0, index;
}
static MegasasCmd *megasas_next_frame(MegasasState *s,
- target_phys_addr_t frame)
+ hwaddr frame)
{
MegasasCmd *cmd = NULL;
int num = 0, index;
}
static MegasasCmd *megasas_enqueue_frame(MegasasState *s,
- target_phys_addr_t frame, uint64_t context, int count)
+ hwaddr frame, uint64_t context, int count)
{
MegasasCmd *cmd = NULL;
int frame_size = MFI_FRAME_SIZE * 16;
- target_phys_addr_t frame_size_p = frame_size;
+ hwaddr frame_size_p = frame_size;
cmd = megasas_next_frame(s, frame);
/* All frames busy */
static int megasas_init_firmware(MegasasState *s, MegasasCmd *cmd)
{
uint32_t pa_hi, pa_lo;
- target_phys_addr_t iq_pa, initq_size;
+ hwaddr iq_pa, initq_size;
struct mfi_init_qinfo *initq;
uint32_t flags;
int ret = MFI_STAT_OK;
static int megasas_handle_abort(MegasasState *s, MegasasCmd *cmd)
{
uint64_t abort_ctx = le64_to_cpu(cmd->frame->abort.abort_context);
- target_phys_addr_t abort_addr, addr_hi, addr_lo;
+ hwaddr abort_addr, addr_hi, addr_lo;
MegasasCmd *abort_cmd;
addr_hi = le32_to_cpu(cmd->frame->abort.abort_mfi_addr_hi);
}
}
-static uint64_t megasas_mmio_read(void *opaque, target_phys_addr_t addr,
+static uint64_t megasas_mmio_read(void *opaque, hwaddr addr,
unsigned size)
{
MegasasState *s = opaque;
return retval;
}
-static void megasas_mmio_write(void *opaque, target_phys_addr_t addr,
+static void megasas_mmio_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
MegasasState *s = opaque;
}
};
-static uint64_t megasas_port_read(void *opaque, target_phys_addr_t addr,
+static uint64_t megasas_port_read(void *opaque, hwaddr addr,
unsigned size)
{
return megasas_mmio_read(opaque, addr & 0xff, size);
}
-static void megasas_port_write(void *opaque, target_phys_addr_t addr,
+static void megasas_port_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
megasas_mmio_write(opaque, addr & 0xff, val, size);
}
};
-static uint64_t megasas_queue_read(void *opaque, target_phys_addr_t addr,
+static uint64_t megasas_queue_read(void *opaque, hwaddr addr,
unsigned size)
{
return 0;
}
}
-static int microblaze_load_dtb(target_phys_addr_t addr,
+static int microblaze_load_dtb(hwaddr addr,
uint32_t ramsize,
const char *kernel_cmdline,
const char *dtb_filename)
return addr - 0x30000000LL;
}
-void microblaze_load_kernel(MicroBlazeCPU *cpu, target_phys_addr_t ddr_base,
+void microblaze_load_kernel(MicroBlazeCPU *cpu, hwaddr ddr_base,
uint32_t ramsize, const char *dtb_filename,
void (*machine_cpu_reset)(MicroBlazeCPU *))
{
/* If it wasn't an ELF image, try an u-boot image. */
if (kernel_size < 0) {
- target_phys_addr_t uentry, loadaddr;
+ hwaddr uentry, loadaddr;
kernel_size = load_uimage(kernel_filename, &uentry, &loadaddr, 0);
boot_info.bootstrap_pc = uentry;
#include "hw.h"
-void microblaze_load_kernel(MicroBlazeCPU *cpu, target_phys_addr_t ddr_base,
+void microblaze_load_kernel(MicroBlazeCPU *cpu, hwaddr ddr_base,
uint32_t ramsize, const char *dtb_filename,
void (*machine_cpu_reset)(MicroBlazeCPU *));
}
}
-static uint64_t ac97_read(void *opaque, target_phys_addr_t addr,
+static uint64_t ac97_read(void *opaque, hwaddr addr,
unsigned size)
{
MilkymistAC97State *s = opaque;
return r;
}
-static void ac97_write(void *opaque, target_phys_addr_t addr, uint64_t value,
+static void ac97_write(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
MilkymistAC97State *s = opaque;
};
typedef struct MilkymistHpdmcState MilkymistHpdmcState;
-static uint64_t hpdmc_read(void *opaque, target_phys_addr_t addr,
+static uint64_t hpdmc_read(void *opaque, hwaddr addr,
unsigned size)
{
MilkymistHpdmcState *s = opaque;
return r;
}
-static void hpdmc_write(void *opaque, target_phys_addr_t addr, uint64_t value,
+static void hpdmc_write(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
MilkymistHpdmcState *s = opaque;
#include "qdev.h"
#include "qdev-addr.h"
-static inline DeviceState *milkymist_uart_create(target_phys_addr_t base,
+static inline DeviceState *milkymist_uart_create(hwaddr base,
qemu_irq irq)
{
DeviceState *dev;
return dev;
}
-static inline DeviceState *milkymist_hpdmc_create(target_phys_addr_t base)
+static inline DeviceState *milkymist_hpdmc_create(hwaddr base)
{
DeviceState *dev;
return dev;
}
-static inline DeviceState *milkymist_memcard_create(target_phys_addr_t base)
+static inline DeviceState *milkymist_memcard_create(hwaddr base)
{
DeviceState *dev;
return dev;
}
-static inline DeviceState *milkymist_vgafb_create(target_phys_addr_t base,
+static inline DeviceState *milkymist_vgafb_create(hwaddr base,
uint32_t fb_offset, uint32_t fb_mask)
{
DeviceState *dev;
return dev;
}
-static inline DeviceState *milkymist_sysctl_create(target_phys_addr_t base,
+static inline DeviceState *milkymist_sysctl_create(hwaddr base,
qemu_irq gpio_irq, qemu_irq timer0_irq, qemu_irq timer1_irq,
uint32_t freq_hz, uint32_t system_id, uint32_t capabilities,
uint32_t gpio_strappings)
return dev;
}
-static inline DeviceState *milkymist_pfpu_create(target_phys_addr_t base,
+static inline DeviceState *milkymist_pfpu_create(hwaddr base,
qemu_irq irq)
{
DeviceState *dev;
};
#endif
-static inline DeviceState *milkymist_tmu2_create(target_phys_addr_t base,
+static inline DeviceState *milkymist_tmu2_create(hwaddr base,
qemu_irq irq)
{
#ifdef CONFIG_OPENGL
#endif
}
-static inline DeviceState *milkymist_ac97_create(target_phys_addr_t base,
+static inline DeviceState *milkymist_ac97_create(hwaddr base,
qemu_irq crrequest_irq, qemu_irq crreply_irq, qemu_irq dmar_irq,
qemu_irq dmaw_irq)
{
return dev;
}
-static inline DeviceState *milkymist_minimac_create(target_phys_addr_t base,
+static inline DeviceState *milkymist_minimac_create(hwaddr base,
qemu_irq rx_irq, qemu_irq tx_irq)
{
DeviceState *dev;
return dev;
}
-static inline DeviceState *milkymist_minimac2_create(target_phys_addr_t base,
- target_phys_addr_t buffers_base, qemu_irq rx_irq, qemu_irq tx_irq)
+static inline DeviceState *milkymist_minimac2_create(hwaddr base,
+ hwaddr buffers_base, qemu_irq rx_irq, qemu_irq tx_irq)
{
DeviceState *dev;
return dev;
}
-static inline DeviceState *milkymist_softusb_create(target_phys_addr_t base,
+static inline DeviceState *milkymist_softusb_create(hwaddr base,
qemu_irq irq, uint32_t pmem_base, uint32_t pmem_size,
uint32_t dmem_base, uint32_t dmem_size)
{
}
}
-static uint64_t memcard_read(void *opaque, target_phys_addr_t addr,
+static uint64_t memcard_read(void *opaque, hwaddr addr,
unsigned size)
{
MilkymistMemcardState *s = opaque;
return r;
}
-static void memcard_write(void *opaque, target_phys_addr_t addr, uint64_t value,
+static void memcard_write(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
MilkymistMemcardState *s = opaque;
NICState *nic;
NICConf conf;
char *phy_model;
- target_phys_addr_t buffers_base;
+ hwaddr buffers_base;
MemoryRegion buffers;
MemoryRegion regs_region;
}
static uint64_t
-minimac2_read(void *opaque, target_phys_addr_t addr, unsigned size)
+minimac2_read(void *opaque, hwaddr addr, unsigned size)
{
MilkymistMinimac2State *s = opaque;
uint32_t r = 0;
}
static void
-minimac2_write(void *opaque, target_phys_addr_t addr, uint64_t value,
+minimac2_write(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
MilkymistMinimac2State *s = opaque;
};
typedef struct MilkymistPFPUState MilkymistPFPUState;
-static inline target_phys_addr_t
+static inline hwaddr
get_dma_address(uint32_t base, uint32_t x, uint32_t y)
{
return base + 8 * (128 * y + x);
{
uint32_t a = cpu_to_be32(s->gp_regs[reg_a]);
uint32_t b = cpu_to_be32(s->gp_regs[reg_b]);
- target_phys_addr_t dma_ptr =
+ hwaddr dma_ptr =
get_dma_address(s->regs[R_MESHBASE],
s->gp_regs[GPR_X], s->gp_regs[GPR_Y]);
cpu_physical_memory_write(dma_ptr, (uint8_t *)&a, 4);
return (512 * s->regs[R_CODEPAGE]) + addr - MICROCODE_BEGIN;
}
-static uint64_t pfpu_read(void *opaque, target_phys_addr_t addr,
+static uint64_t pfpu_read(void *opaque, hwaddr addr,
unsigned size)
{
MilkymistPFPUState *s = opaque;
return r;
}
-static void pfpu_write(void *opaque, target_phys_addr_t addr, uint64_t value,
+static void pfpu_write(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
MilkymistPFPUState *s = opaque;
};
typedef struct MilkymistSoftUsbState MilkymistSoftUsbState;
-static uint64_t softusb_read(void *opaque, target_phys_addr_t addr,
+static uint64_t softusb_read(void *opaque, hwaddr addr,
unsigned size)
{
MilkymistSoftUsbState *s = opaque;
}
static void
-softusb_write(void *opaque, target_phys_addr_t addr, uint64_t value,
+softusb_write(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
MilkymistSoftUsbState *s = opaque;
}
}
-static uint64_t sysctl_read(void *opaque, target_phys_addr_t addr,
+static uint64_t sysctl_read(void *opaque, hwaddr addr,
unsigned size)
{
MilkymistSysctlState *s = opaque;
return r;
}
-static void sysctl_write(void *opaque, target_phys_addr_t addr, uint64_t value,
+static void sysctl_write(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
MilkymistSysctlState *s = opaque;
GLXPbuffer pbuffer;
GLuint texture;
void *fb;
- target_phys_addr_t fb_len;
+ hwaddr fb_len;
void *mesh;
- target_phys_addr_t mesh_len;
+ hwaddr mesh_len;
float m;
trace_milkymist_tmu2_start();
qemu_irq_pulse(s->irq);
}
-static uint64_t tmu2_read(void *opaque, target_phys_addr_t addr,
+static uint64_t tmu2_read(void *opaque, hwaddr addr,
unsigned size)
{
MilkymistTMU2State *s = opaque;
}
}
-static void tmu2_write(void *opaque, target_phys_addr_t addr, uint64_t value,
+static void tmu2_write(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
MilkymistTMU2State *s = opaque;
}
}
-static uint64_t uart_read(void *opaque, target_phys_addr_t addr,
+static uint64_t uart_read(void *opaque, hwaddr addr,
unsigned size)
{
MilkymistUartState *s = opaque;
return r;
}
-static void uart_write(void *opaque, target_phys_addr_t addr, uint64_t value,
+static void uart_write(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
MilkymistUartState *s = opaque;
s->invalidate = 1;
}
-static uint64_t vgafb_read(void *opaque, target_phys_addr_t addr,
+static uint64_t vgafb_read(void *opaque, hwaddr addr,
unsigned size)
{
MilkymistVgafbState *s = opaque;
return r;
}
-static void vgafb_write(void *opaque, target_phys_addr_t addr, uint64_t value,
+static void vgafb_write(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
MilkymistVgafbState *s = opaque;
typedef struct {
LM32CPU *cpu;
- target_phys_addr_t bootstrap_pc;
- target_phys_addr_t flash_base;
- target_phys_addr_t initrd_base;
+ hwaddr bootstrap_pc;
+ hwaddr flash_base;
+ hwaddr initrd_base;
size_t initrd_size;
- target_phys_addr_t cmdline_base;
+ hwaddr cmdline_base;
} ResetInfo;
static void cpu_irq_handler(void *opaque, int irq, int level)
ResetInfo *reset_info;
/* memory map */
- target_phys_addr_t flash_base = 0x00000000;
+ hwaddr flash_base = 0x00000000;
size_t flash_sector_size = 128 * 1024;
size_t flash_size = 32 * 1024 * 1024;
- target_phys_addr_t sdram_base = 0x40000000;
+ hwaddr sdram_base = 0x40000000;
size_t sdram_size = 128 * 1024 * 1024;
- target_phys_addr_t initrd_base = sdram_base + 0x1002000;
- target_phys_addr_t cmdline_base = sdram_base + 0x1000000;
+ hwaddr initrd_base = sdram_base + 0x1002000;
+ hwaddr cmdline_base = sdram_base + 0x1000000;
size_t initrd_max = sdram_size - 0x1002000;
reset_info = g_malloc0(sizeof(ResetInfo));
/* rc4030.c */
typedef struct rc4030DMAState *rc4030_dma;
-void rc4030_dma_memory_rw(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write);
+void rc4030_dma_memory_rw(void *opaque, hwaddr addr, uint8_t *buf, int len, int is_write);
void rc4030_dma_read(void *dma, uint8_t *buf, int len);
void rc4030_dma_write(void *dma, uint8_t *buf, int len);
MemoryRegion *sysmem);
/* dp8393x.c */
-void dp83932_init(NICInfo *nd, target_phys_addr_t base, int it_shift,
+void dp83932_init(NICInfo *nd, hwaddr base, int it_shift,
MemoryRegion *address_space,
qemu_irq irq, void* mem_opaque,
- void (*memory_rw)(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write));
+ void (*memory_rw)(void *opaque, hwaddr addr, uint8_t *buf, int len, int is_write));
#endif
cpu_reset(CPU(cpu));
}
-static uint64_t rtc_read(void *opaque, target_phys_addr_t addr, unsigned size)
+static uint64_t rtc_read(void *opaque, hwaddr addr, unsigned size)
{
return cpu_inw(0x71);
}
-static void rtc_write(void *opaque, target_phys_addr_t addr,
+static void rtc_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
cpu_outw(0x71, val & 0xff);
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static uint64_t dma_dummy_read(void *opaque, target_phys_addr_t addr,
+static uint64_t dma_dummy_read(void *opaque, hwaddr addr,
unsigned size)
{
/* Nothing to do. That is only to ensure that
return 0xff;
}
-static void dma_dummy_write(void *opaque, target_phys_addr_t addr,
+static void dma_dummy_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
/* Nothing to do. That is only to ensure that
eeprom.sda = sda;
}
-static uint64_t malta_fpga_read(void *opaque, target_phys_addr_t addr,
+static uint64_t malta_fpga_read(void *opaque, hwaddr addr,
unsigned size)
{
MaltaFPGAState *s = opaque;
return val;
}
-static void malta_fpga_write(void *opaque, target_phys_addr_t addr,
+static void malta_fpga_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
MaltaFPGAState *s = opaque;
}
static MaltaFPGAState *malta_fpga_init(MemoryRegion *address_space,
- target_phys_addr_t base, qemu_irq uart_irq, CharDriverState *uart_chr)
+ hwaddr base, qemu_irq uart_irq, CharDriverState *uart_chr)
{
MaltaFPGAState *s;
const char *initrd_filename;
} loaderparams;
-static void mips_qemu_write (void *opaque, target_phys_addr_t addr,
+static void mips_qemu_write (void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
if ((addr & 0xffff) == 0 && val == 42)
qemu_system_shutdown_request ();
}
-static uint64_t mips_qemu_read (void *opaque, target_phys_addr_t addr,
+static uint64_t mips_qemu_read (void *opaque, hwaddr addr,
unsigned size)
{
return 0;
return size;
}
-static uint64_t mipsnet_ioport_read(void *opaque, target_phys_addr_t addr,
+static uint64_t mipsnet_ioport_read(void *opaque, hwaddr addr,
unsigned int size)
{
MIPSnetState *s = opaque;
return ret;
}
-static void mipsnet_ioport_write(void *opaque, target_phys_addr_t addr,
+static void mipsnet_ioport_write(void *opaque, hwaddr addr,
uint64_t val, unsigned int size)
{
MIPSnetState *s = opaque;
typedef struct GutsState GutsState;
-static uint64_t mpc8544_guts_read(void *opaque, target_phys_addr_t addr,
+static uint64_t mpc8544_guts_read(void *opaque, hwaddr addr,
unsigned size)
{
uint32_t value = 0;
return value;
}
-static void mpc8544_guts_write(void *opaque, target_phys_addr_t addr,
+static void mpc8544_guts_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
addr &= MPC8544_GUTS_MMIO_SIZE - 1;
}
}
-static uint64_t msix_table_mmio_read(void *opaque, target_phys_addr_t addr,
+static uint64_t msix_table_mmio_read(void *opaque, hwaddr addr,
unsigned size)
{
PCIDevice *dev = opaque;
return pci_get_long(dev->msix_table + addr);
}
-static void msix_table_mmio_write(void *opaque, target_phys_addr_t addr,
+static void msix_table_mmio_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
PCIDevice *dev = opaque;
},
};
-static uint64_t msix_pba_mmio_read(void *opaque, target_phys_addr_t addr,
+static uint64_t msix_pba_mmio_read(void *opaque, hwaddr addr,
unsigned size)
{
PCIDevice *dev = opaque;
static uint64_t
-mst_fpga_readb(void *opaque, target_phys_addr_t addr, unsigned size)
+mst_fpga_readb(void *opaque, hwaddr addr, unsigned size)
{
mst_irq_state *s = (mst_irq_state *) opaque;
}
static void
-mst_fpga_writeb(void *opaque, target_phys_addr_t addr, uint64_t value,
+mst_fpga_writeb(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
mst_irq_state *s = (mst_irq_state *) opaque;
/* buffer holding kernel, cmdlines and mb_infos */
void *mb_buf;
/* address in target */
- target_phys_addr_t mb_buf_phys;
+ hwaddr mb_buf_phys;
/* size of mb_buf in bytes */
unsigned mb_buf_size;
/* offset of mb-info's in bytes */
- target_phys_addr_t offset_mbinfo;
+ hwaddr offset_mbinfo;
/* offset in buffer for cmdlines in bytes */
- target_phys_addr_t offset_cmdlines;
+ hwaddr offset_cmdlines;
/* offset of modules in bytes */
- target_phys_addr_t offset_mods;
+ hwaddr offset_mods;
/* available slots for mb modules infos */
int mb_mods_avail;
/* currently used slots of mb modules */
static uint32_t mb_add_cmdline(MultibootState *s, const char *cmdline)
{
- target_phys_addr_t p = s->offset_cmdlines;
+ hwaddr p = s->offset_cmdlines;
char *b = (char *)s->mb_buf + p;
get_opt_value(b, strlen(cmdline) + 1, cmdline);
}
static void mb_add_mod(MultibootState *s,
- target_phys_addr_t start, target_phys_addr_t end,
- target_phys_addr_t cmdline_phys)
+ hwaddr start, hwaddr end,
+ hwaddr cmdline_phys)
{
char *p;
assert(s->mb_mods_count < s->mb_mods_avail);
*next_initrd = '\0';
/* if a space comes after the module filename, treat everything
after that as parameters */
- target_phys_addr_t c = mb_add_cmdline(&mbs, initrd_filename);
+ hwaddr c = mb_add_cmdline(&mbs, initrd_filename);
if ((next_space = strchr(initrd_filename, ' ')))
*next_space = '\0';
mb_debug("multiboot loading module: %s\n", initrd_filename);
} while (desc_addr != s->tx_queue[queue_index]);
}
-static uint64_t mv88w8618_eth_read(void *opaque, target_phys_addr_t offset,
+static uint64_t mv88w8618_eth_read(void *opaque, hwaddr offset,
unsigned size)
{
mv88w8618_eth_state *s = opaque;
}
}
-static void mv88w8618_eth_write(void *opaque, target_phys_addr_t offset,
+static void mv88w8618_eth_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
mv88w8618_eth_state *s = opaque;
s->brightness |= level << irq;
}
-static uint64_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset,
+static uint64_t musicpal_lcd_read(void *opaque, hwaddr offset,
unsigned size)
{
musicpal_lcd_state *s = opaque;
}
}
-static void musicpal_lcd_write(void *opaque, target_phys_addr_t offset,
+static void musicpal_lcd_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
musicpal_lcd_state *s = opaque;
mv88w8618_pic_update(s);
}
-static uint64_t mv88w8618_pic_read(void *opaque, target_phys_addr_t offset,
+static uint64_t mv88w8618_pic_read(void *opaque, hwaddr offset,
unsigned size)
{
mv88w8618_pic_state *s = opaque;
}
}
-static void mv88w8618_pic_write(void *opaque, target_phys_addr_t offset,
+static void mv88w8618_pic_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
mv88w8618_pic_state *s = opaque;
s->ptimer = ptimer_init(bh);
}
-static uint64_t mv88w8618_pit_read(void *opaque, target_phys_addr_t offset,
+static uint64_t mv88w8618_pit_read(void *opaque, hwaddr offset,
unsigned size)
{
mv88w8618_pit_state *s = opaque;
}
}
-static void mv88w8618_pit_write(void *opaque, target_phys_addr_t offset,
+static void mv88w8618_pit_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
mv88w8618_pit_state *s = opaque;
} mv88w8618_flashcfg_state;
static uint64_t mv88w8618_flashcfg_read(void *opaque,
- target_phys_addr_t offset,
+ hwaddr offset,
unsigned size)
{
mv88w8618_flashcfg_state *s = opaque;
}
}
-static void mv88w8618_flashcfg_write(void *opaque, target_phys_addr_t offset,
+static void mv88w8618_flashcfg_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
mv88w8618_flashcfg_state *s = opaque;
#define MP_BOARD_REVISION 0x31
-static uint64_t musicpal_misc_read(void *opaque, target_phys_addr_t offset,
+static uint64_t musicpal_misc_read(void *opaque, hwaddr offset,
unsigned size)
{
switch (offset) {
}
}
-static void musicpal_misc_write(void *opaque, target_phys_addr_t offset,
+static void musicpal_misc_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
}
#define MP_WLAN_MAGIC1 0x11c
#define MP_WLAN_MAGIC2 0x124
-static uint64_t mv88w8618_wlan_read(void *opaque, target_phys_addr_t offset,
+static uint64_t mv88w8618_wlan_read(void *opaque, hwaddr offset,
unsigned size)
{
switch (offset) {
}
}
-static void mv88w8618_wlan_write(void *opaque, target_phys_addr_t offset,
+static void mv88w8618_wlan_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
}
}
}
-static uint64_t musicpal_gpio_read(void *opaque, target_phys_addr_t offset,
+static uint64_t musicpal_gpio_read(void *opaque, hwaddr offset,
unsigned size)
{
musicpal_gpio_state *s = opaque;
}
}
-static void musicpal_gpio_write(void *opaque, target_phys_addr_t offset,
+static void musicpal_gpio_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
musicpal_gpio_state *s = opaque;
}
};
-static uint64_t ne2000_read(void *opaque, target_phys_addr_t addr,
+static uint64_t ne2000_read(void *opaque, hwaddr addr,
unsigned size)
{
NE2000State *s = opaque;
return ((uint64_t)1 << (size * 8)) - 1;
}
-static void ne2000_write(void *opaque, target_phys_addr_t addr,
+static void ne2000_write(void *opaque, hwaddr addr,
uint64_t data, unsigned size)
{
NE2000State *s = opaque;
void m48t59_toggle_lock (void *private, int lock);
M48t59State *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size,
int type);
-M48t59State *m48t59_init(qemu_irq IRQ, target_phys_addr_t mem_base,
+M48t59State *m48t59_init(qemu_irq IRQ, hwaddr mem_base,
uint32_t io_base, uint16_t size, int type);
void m48t59_set_addr (void *opaque, uint32_t addr);
/* OMAP2 l4 Interconnect */
struct omap_l4_s;
struct omap_l4_region_s {
- target_phys_addr_t offset;
+ hwaddr offset;
size_t size;
int access;
};
struct omap_l4_s *bus;
int regions;
const struct omap_l4_region_s *start;
- target_phys_addr_t base;
+ hwaddr base;
uint32_t component;
uint32_t control;
uint32_t status;
};
struct omap_l4_s *omap_l4_init(MemoryRegion *address_space,
- target_phys_addr_t base, int ta_num);
+ hwaddr base, int ta_num);
struct omap_target_agent_s;
struct omap_target_agent_s *omap_l4ta_get(
const struct omap_l4_region_s *regions,
const struct omap_l4_agent_info_s *agents,
int cs);
-target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta,
+hwaddr omap_l4_attach(struct omap_target_agent_s *ta,
int region, MemoryRegion *mr);
-target_phys_addr_t omap_l4_region_base(struct omap_target_agent_s *ta,
+hwaddr omap_l4_region_base(struct omap_target_agent_s *ta,
int region);
-target_phys_addr_t omap_l4_region_size(struct omap_target_agent_s *ta,
+hwaddr omap_l4_region_size(struct omap_target_agent_s *ta,
int region);
/* OMAP2 SDRAM controller */
struct omap_sdrc_s;
struct omap_sdrc_s *omap_sdrc_init(MemoryRegion *sysmem,
- target_phys_addr_t base);
+ hwaddr base);
void omap_sdrc_reset(struct omap_sdrc_s *s);
/* OMAP2 general purpose memory controller */
struct omap_gpmc_s;
struct omap_gpmc_s *omap_gpmc_init(struct omap_mpu_state_s *mpu,
- target_phys_addr_t base,
+ hwaddr base,
qemu_irq irq, qemu_irq drq);
void omap_gpmc_reset(struct omap_gpmc_s *s);
void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem);
};
struct soc_dma_s;
-struct soc_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
+struct soc_dma_s *omap_dma_init(hwaddr base, qemu_irq *irqs,
MemoryRegion *sysmem,
qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
enum omap_dma_model model);
-struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,
+struct soc_dma_s *omap_dma4_init(hwaddr base, qemu_irq *irqs,
MemoryRegion *sysmem,
struct omap_mpu_state_s *mpu, int fifo,
int chans, omap_clk iclk, omap_clk fclk);
/* Only used in OMAP DMA 3.x gigacells */
struct omap_dma_lcd_channel_s {
enum omap_dma_port src;
- target_phys_addr_t src_f1_top;
- target_phys_addr_t src_f1_bottom;
- target_phys_addr_t src_f2_top;
- target_phys_addr_t src_f2_bottom;
+ hwaddr src_f1_top;
+ hwaddr src_f1_bottom;
+ hwaddr src_f2_top;
+ hwaddr src_f2_bottom;
/* Used in OMAP DMA 3.2 gigacell */
unsigned char brust_f1;
int dual;
int current_frame;
- target_phys_addr_t phys_framebuffer[2];
+ hwaddr phys_framebuffer[2];
qemu_irq irq;
struct omap_mpu_state_s *mpu;
} *omap_dma_get_lcdch(struct soc_dma_s *s);
void omap_synctimer_reset(struct omap_synctimer_s *s);
struct omap_uart_s;
-struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
+struct omap_uart_s *omap_uart_init(hwaddr base,
qemu_irq irq, omap_clk fclk, omap_clk iclk,
qemu_irq txdma, qemu_irq rxdma,
const char *label, CharDriverState *chr);
struct omap_lcd_panel_s;
void omap_lcdc_reset(struct omap_lcd_panel_s *s);
struct omap_lcd_panel_s *omap_lcdc_init(MemoryRegion *sysmem,
- target_phys_addr_t base,
+ hwaddr base,
qemu_irq irq,
struct omap_dma_lcd_channel_s *dma,
omap_clk clk);
void omap_dss_reset(struct omap_dss_s *s);
struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,
MemoryRegion *sysmem,
- target_phys_addr_t l3_base,
+ hwaddr l3_base,
qemu_irq irq, qemu_irq drq,
omap_clk fck1, omap_clk fck2, omap_clk ck54m,
omap_clk ick1, omap_clk ick2);
/* omap_mmc.c */
struct omap_mmc_s;
-struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base,
+struct omap_mmc_s *omap_mmc_init(hwaddr base,
MemoryRegion *sysmem,
BlockDriverState *bd,
qemu_irq irq, qemu_irq dma[], omap_clk clk);
struct omap_dma_port_if_s {
uint32_t (*read[3])(struct omap_mpu_state_s *s,
- target_phys_addr_t offset);
+ hwaddr offset);
void (*write[3])(struct omap_mpu_state_s *s,
- target_phys_addr_t offset, uint32_t value);
+ hwaddr offset, uint32_t value);
int (*addr_valid)(struct omap_mpu_state_s *s,
- target_phys_addr_t addr);
+ hwaddr addr);
} port[__omap_dma_port_last];
unsigned long sdram_size;
unsigned long sdram_size,
const char *core);
-#define OMAP_FMT_plx "%#08" TARGET_PRIxPHYS
+#define OMAP_FMT_plx "%#08" HWADDR_PRIx
-uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr);
-void omap_badwidth_write8(void *opaque, target_phys_addr_t addr,
+uint32_t omap_badwidth_read8(void *opaque, hwaddr addr);
+void omap_badwidth_write8(void *opaque, hwaddr addr,
uint32_t value);
-uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr);
-void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,
+uint32_t omap_badwidth_read16(void *opaque, hwaddr addr);
+void omap_badwidth_write16(void *opaque, hwaddr addr,
uint32_t value);
-uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr);
-void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
+uint32_t omap_badwidth_read32(void *opaque, hwaddr addr);
+void omap_badwidth_write32(void *opaque, hwaddr addr,
uint32_t value);
void omap_mpu_wakeup(void *opaque, int irq, int req);
#include "sysbus.h"
/* Should signal the TCMI/GPMC */
-uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr)
+uint32_t omap_badwidth_read8(void *opaque, hwaddr addr)
{
uint8_t ret;
return ret;
}
-void omap_badwidth_write8(void *opaque, target_phys_addr_t addr,
+void omap_badwidth_write8(void *opaque, hwaddr addr,
uint32_t value)
{
uint8_t val8 = value;
cpu_physical_memory_write(addr, (void *) &val8, 1);
}
-uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr)
+uint32_t omap_badwidth_read16(void *opaque, hwaddr addr)
{
uint16_t ret;
return ret;
}
-void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,
+void omap_badwidth_write16(void *opaque, hwaddr addr,
uint32_t value)
{
uint16_t val16 = value;
cpu_physical_memory_write(addr, (void *) &val16, 2);
}
-uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr)
+uint32_t omap_badwidth_read32(void *opaque, hwaddr addr)
{
uint32_t ret;
return ret;
}
-void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
+void omap_badwidth_write32(void *opaque, hwaddr addr,
uint32_t value)
{
OMAP_32B_REG(addr);
timer->rate = omap_clk_getrate(timer->clk);
}
-static uint64_t omap_mpu_timer_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_mpu_timer_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
return 0;
}
-static void omap_mpu_timer_write(void *opaque, target_phys_addr_t addr,
+static void omap_mpu_timer_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
}
static struct omap_mpu_timer_s *omap_mpu_timer_init(MemoryRegion *system_memory,
- target_phys_addr_t base,
+ hwaddr base,
qemu_irq irq, omap_clk clk)
{
struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *)
int reset;
};
-static uint64_t omap_wd_timer_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_wd_timer_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
return 0;
}
-static void omap_wd_timer_write(void *opaque, target_phys_addr_t addr,
+static void omap_wd_timer_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
}
static struct omap_watchdog_timer_s *omap_wd_timer_init(MemoryRegion *memory,
- target_phys_addr_t base,
+ hwaddr base,
qemu_irq irq, omap_clk clk)
{
struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *)
MemoryRegion iomem;
};
-static uint64_t omap_os_timer_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_os_timer_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
return 0;
}
-static void omap_os_timer_write(void *opaque, target_phys_addr_t addr,
+static void omap_os_timer_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
}
static struct omap_32khz_timer_s *omap_os_timer_init(MemoryRegion *memory,
- target_phys_addr_t base,
+ hwaddr base,
qemu_irq irq, omap_clk clk)
{
struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *)
}
/* Ultra Low-Power Device Module */
-static uint64_t omap_ulpd_pm_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_ulpd_pm_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
omap_clk_canidle(omap_findclk(s, "usb_clk0"), (~value >> 3) & 1);
}
-static void omap_ulpd_pm_write(void *opaque, target_phys_addr_t addr,
+static void omap_ulpd_pm_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
}
static void omap_ulpd_pm_init(MemoryRegion *system_memory,
- target_phys_addr_t base,
+ hwaddr base,
struct omap_mpu_state_s *mpu)
{
memory_region_init_io(&mpu->ulpd_pm_iomem, &omap_ulpd_pm_ops, mpu,
}
/* OMAP Pin Configuration */
-static uint64_t omap_pin_cfg_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_pin_cfg_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
omap_clk_onoff(omap_findclk(s, "usb_hhc_ck"), (value >> 9) & 1);
}
-static void omap_pin_cfg_write(void *opaque, target_phys_addr_t addr,
+static void omap_pin_cfg_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
}
static void omap_pin_cfg_init(MemoryRegion *system_memory,
- target_phys_addr_t base,
+ hwaddr base,
struct omap_mpu_state_s *mpu)
{
memory_region_init_io(&mpu->pin_cfg_iomem, &omap_pin_cfg_ops, mpu,
}
/* Device Identification, Die Identification */
-static uint64_t omap_id_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_id_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
return 0;
}
-static void omap_id_write(void *opaque, target_phys_addr_t addr,
+static void omap_id_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
if (size != 4) {
}
/* MPUI Control (Dummy) */
-static uint64_t omap_mpui_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_mpui_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
return 0;
}
-static void omap_mpui_write(void *opaque, target_phys_addr_t addr,
+static void omap_mpui_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
s->mpui_ctrl = 0x0003ff1b;
}
-static void omap_mpui_init(MemoryRegion *memory, target_phys_addr_t base,
+static void omap_mpui_init(MemoryRegion *memory, hwaddr base,
struct omap_mpu_state_s *mpu)
{
memory_region_init_io(&mpu->mpui_iomem, &omap_mpui_ops, mpu,
uint16_t enh_control;
};
-static uint64_t omap_tipb_bridge_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_tipb_bridge_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
return 0;
}
-static void omap_tipb_bridge_write(void *opaque, target_phys_addr_t addr,
+static void omap_tipb_bridge_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
}
static struct omap_tipb_bridge_s *omap_tipb_bridge_init(
- MemoryRegion *memory, target_phys_addr_t base,
+ MemoryRegion *memory, hwaddr base,
qemu_irq abort_irq, omap_clk clk)
{
struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *)
}
/* Dummy Traffic Controller's Memory Interface */
-static uint64_t omap_tcmi_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_tcmi_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
return 0;
}
-static void omap_tcmi_write(void *opaque, target_phys_addr_t addr,
+static void omap_tcmi_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
mpu->tcmi_regs[0x40 >> 2] = 0x00000000;
}
-static void omap_tcmi_init(MemoryRegion *memory, target_phys_addr_t base,
+static void omap_tcmi_init(MemoryRegion *memory, hwaddr base,
struct omap_mpu_state_s *mpu)
{
memory_region_init_io(&mpu->tcmi_iomem, &omap_tcmi_ops, mpu,
omap_clk dpll;
};
-static uint64_t omap_dpll_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_dpll_read(void *opaque, hwaddr addr,
unsigned size)
{
struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
return 0;
}
-static void omap_dpll_write(void *opaque, target_phys_addr_t addr,
+static void omap_dpll_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
}
static struct dpll_ctl_s *omap_dpll_init(MemoryRegion *memory,
- target_phys_addr_t base, omap_clk clk)
+ hwaddr base, omap_clk clk)
{
struct dpll_ctl_s *s = g_malloc0(sizeof(*s));
memory_region_init_io(&s->iomem, &omap_dpll_ops, s, "omap-dpll", 0x100);
}
/* MPU Clock/Reset/Power Mode Control */
-static uint64_t omap_clkm_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_clkm_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
}
}
-static void omap_clkm_write(void *opaque, target_phys_addr_t addr,
+static void omap_clkm_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static uint64_t omap_clkdsp_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_clkdsp_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
SET_ONOFF("dspxor_ck", 1); /* EN_XORPCK */
}
-static void omap_clkdsp_write(void *opaque, target_phys_addr_t addr,
+static void omap_clkdsp_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
s->clkm.dsp_rstct2 = 0x0000;
}
-static void omap_clkm_init(MemoryRegion *memory, target_phys_addr_t mpu_base,
- target_phys_addr_t dsp_base, struct omap_mpu_state_s *s)
+static void omap_clkm_init(MemoryRegion *memory, hwaddr mpu_base,
+ hwaddr dsp_base, struct omap_mpu_state_s *s)
{
memory_region_init_io(&s->clkm_iomem, &omap_clkm_ops, s,
"omap-clkm", 0x100);
s->row_latch = ~rows;
}
-static uint64_t omap_mpuio_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_mpuio_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
return 0;
}
-static void omap_mpuio_write(void *opaque, target_phys_addr_t addr,
+static void omap_mpuio_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
}
static struct omap_mpuio_s *omap_mpuio_init(MemoryRegion *memory,
- target_phys_addr_t base,
+ hwaddr base,
qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup,
omap_clk clk)
{
}
}
-static uint64_t omap_uwire_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_uwire_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
return 0;
}
-static void omap_uwire_write(void *opaque, target_phys_addr_t addr,
+static void omap_uwire_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
}
static struct omap_uwire_s *omap_uwire_init(MemoryRegion *system_memory,
- target_phys_addr_t base,
+ hwaddr base,
qemu_irq txirq, qemu_irq rxirq,
qemu_irq dma,
omap_clk clk)
}
}
-static uint64_t omap_pwl_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_pwl_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_pwl_s *s = (struct omap_pwl_s *) opaque;
return 0;
}
-static void omap_pwl_write(void *opaque, target_phys_addr_t addr,
+static void omap_pwl_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_pwl_s *s = (struct omap_pwl_s *) opaque;
}
static struct omap_pwl_s *omap_pwl_init(MemoryRegion *system_memory,
- target_phys_addr_t base,
+ hwaddr base,
omap_clk clk)
{
struct omap_pwl_s *s = g_malloc0(sizeof(*s));
omap_clk clk;
};
-static uint64_t omap_pwt_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_pwt_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_pwt_s *s = (struct omap_pwt_s *) opaque;
return 0;
}
-static void omap_pwt_write(void *opaque, target_phys_addr_t addr,
+static void omap_pwt_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_pwt_s *s = (struct omap_pwt_s *) opaque;
}
static struct omap_pwt_s *omap_pwt_init(MemoryRegion *system_memory,
- target_phys_addr_t base,
+ hwaddr base,
omap_clk clk)
{
struct omap_pwt_s *s = g_malloc0(sizeof(*s));
printf("%s: conversion failed\n", __FUNCTION__);
}
-static uint64_t omap_rtc_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_rtc_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
return 0;
}
-static void omap_rtc_write(void *opaque, target_phys_addr_t addr,
+static void omap_rtc_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
}
static struct omap_rtc_s *omap_rtc_init(MemoryRegion *system_memory,
- target_phys_addr_t base,
+ hwaddr base,
qemu_irq timerirq, qemu_irq alarmirq,
omap_clk clk)
{
omap_mcbsp_rx_stop(s);
}
-static uint64_t omap_mcbsp_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_mcbsp_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
return 0;
}
-static void omap_mcbsp_writeh(void *opaque, target_phys_addr_t addr,
+static void omap_mcbsp_writeh(void *opaque, hwaddr addr,
uint32_t value)
{
struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
OMAP_BAD_REG(addr);
}
-static void omap_mcbsp_writew(void *opaque, target_phys_addr_t addr,
+static void omap_mcbsp_writew(void *opaque, hwaddr addr,
uint32_t value)
{
struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
omap_badwidth_write16(opaque, addr, value);
}
-static void omap_mcbsp_write(void *opaque, target_phys_addr_t addr,
+static void omap_mcbsp_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
switch (size) {
}
static struct omap_mcbsp_s *omap_mcbsp_init(MemoryRegion *system_memory,
- target_phys_addr_t base,
+ hwaddr base,
qemu_irq txirq, qemu_irq rxirq,
qemu_irq *dma, omap_clk clk)
{
omap_lpg_update(s);
}
-static uint64_t omap_lpg_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_lpg_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
return 0;
}
-static void omap_lpg_write(void *opaque, target_phys_addr_t addr,
+static void omap_lpg_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
}
static struct omap_lpg_s *omap_lpg_init(MemoryRegion *system_memory,
- target_phys_addr_t base, omap_clk clk)
+ hwaddr base, omap_clk clk)
{
struct omap_lpg_s *s = (struct omap_lpg_s *)
g_malloc0(sizeof(struct omap_lpg_s));
}
/* MPUI Peripheral Bridge configuration */
-static uint64_t omap_mpui_io_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_mpui_io_read(void *opaque, hwaddr addr,
unsigned size)
{
if (size != 2) {
return 0;
}
-static void omap_mpui_io_write(void *opaque, target_phys_addr_t addr,
+static void omap_mpui_io_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
/* FIXME: infinite loop */
}
static const struct omap_map_s {
- target_phys_addr_t phys_dsp;
- target_phys_addr_t phys_mpu;
+ hwaddr phys_dsp;
+ hwaddr phys_mpu;
uint32_t size;
const char *name;
} omap15xx_dsp_mm[] = {
/* DMA ports for OMAP1 */
static int omap_validate_emiff_addr(struct omap_mpu_state_s *s,
- target_phys_addr_t addr)
+ hwaddr addr)
{
return range_covers_byte(OMAP_EMIFF_BASE, s->sdram_size, addr);
}
static int omap_validate_emifs_addr(struct omap_mpu_state_s *s,
- target_phys_addr_t addr)
+ hwaddr addr)
{
return range_covers_byte(OMAP_EMIFS_BASE, OMAP_EMIFF_BASE - OMAP_EMIFS_BASE,
addr);
}
static int omap_validate_imif_addr(struct omap_mpu_state_s *s,
- target_phys_addr_t addr)
+ hwaddr addr)
{
return range_covers_byte(OMAP_IMIF_BASE, s->sram_size, addr);
}
static int omap_validate_tipb_addr(struct omap_mpu_state_s *s,
- target_phys_addr_t addr)
+ hwaddr addr)
{
return range_covers_byte(0xfffb0000, 0xffff0000 - 0xfffb0000, addr);
}
static int omap_validate_local_addr(struct omap_mpu_state_s *s,
- target_phys_addr_t addr)
+ hwaddr addr)
{
return range_covers_byte(OMAP_LOCALBUS_BASE, 0x1000000, addr);
}
static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s,
- target_phys_addr_t addr)
+ hwaddr addr)
{
return range_covers_byte(0xe1010000, 0xe1020004 - 0xe1010000, addr);
}
omap_eac_interrupt_update(s);
}
-static uint64_t omap_eac_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_eac_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_eac_s *s = (struct omap_eac_s *) opaque;
return 0;
}
-static void omap_eac_write(void *opaque, target_phys_addr_t addr,
+static void omap_eac_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_eac_s *s = (struct omap_eac_s *) opaque;
omap_sti_interrupt_update(s);
}
-static uint64_t omap_sti_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_sti_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_sti_s *s = (struct omap_sti_s *) opaque;
return 0;
}
-static void omap_sti_write(void *opaque, target_phys_addr_t addr,
+static void omap_sti_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_sti_s *s = (struct omap_sti_s *) opaque;
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static uint64_t omap_sti_fifo_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_sti_fifo_read(void *opaque, hwaddr addr,
unsigned size)
{
OMAP_BAD_REG(addr);
return 0;
}
-static void omap_sti_fifo_write(void *opaque, target_phys_addr_t addr,
+static void omap_sti_fifo_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_sti_s *s = (struct omap_sti_s *) opaque;
static struct omap_sti_s *omap_sti_init(struct omap_target_agent_s *ta,
MemoryRegion *sysmem,
- target_phys_addr_t channel_base, qemu_irq irq, omap_clk clk,
+ hwaddr channel_base, qemu_irq irq, omap_clk clk,
CharDriverState *chr)
{
struct omap_sti_s *s = (struct omap_sti_s *)
/* XXX or is the mask applied before PRCM_IRQSTATUS_* ? */
}
-static uint64_t omap_prcm_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_prcm_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
}
}
-static void omap_prcm_write(void *opaque, target_phys_addr_t addr,
+static void omap_prcm_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
uint32_t msuspendmux[5];
};
-static uint32_t omap_sysctl_read8(void *opaque, target_phys_addr_t addr)
+static uint32_t omap_sysctl_read8(void *opaque, hwaddr addr)
{
struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
return 0;
}
-static uint32_t omap_sysctl_read(void *opaque, target_phys_addr_t addr)
+static uint32_t omap_sysctl_read(void *opaque, hwaddr addr)
{
struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
return 0;
}
-static void omap_sysctl_write8(void *opaque, target_phys_addr_t addr,
+static void omap_sysctl_write8(void *opaque, hwaddr addr,
uint32_t value)
{
struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
}
}
-static void omap_sysctl_write(void *opaque, target_phys_addr_t addr,
+static void omap_sysctl_write(void *opaque, hwaddr addr,
uint32_t value)
{
struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
}
static int omap2_validate_addr(struct omap_mpu_state_s *s,
- target_phys_addr_t addr)
+ hwaddr addr)
{
return 1;
}
int endian_lock[2];
int translate[2];
enum omap_dma_port port[2];
- target_phys_addr_t addr[2];
+ hwaddr addr[2];
omap_dma_addressing_t mode[2];
uint32_t elements;
uint16_t frames;
struct omap_dma_channel_s *sibling;
struct omap_dma_reg_set_s {
- target_phys_addr_t src, dest;
+ hwaddr src, dest;
int frame;
int element;
int pck_element;
break;
case 0x06: /* SYS_DMA_CSR_CH0 */
- OMAP_RO_REG((target_phys_addr_t) reg);
+ OMAP_RO_REG((hwaddr) reg);
break;
case 0x08: /* SYS_DMA_CSSA_L_CH0 */
break;
case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */
- OMAP_RO_REG((target_phys_addr_t) reg);
+ OMAP_RO_REG((hwaddr) reg);
break;
case 0x1c: /* DMA_CDEI */
return 0;
}
-static uint64_t omap_dma_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_dma_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_dma_s *s = (struct omap_dma_s *) opaque;
return 0;
}
-static void omap_dma_write(void *opaque, target_phys_addr_t addr,
+static void omap_dma_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_dma_s *s = (struct omap_dma_s *) opaque;
}
}
-struct soc_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
+struct soc_dma_s *omap_dma_init(hwaddr base, qemu_irq *irqs,
MemoryRegion *sysmem,
qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
enum omap_dma_model model)
qemu_irq_raise(s->irq[3]);
}
-static uint64_t omap_dma4_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_dma4_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_dma_s *s = (struct omap_dma_s *) opaque;
}
}
-static void omap_dma4_write(void *opaque, target_phys_addr_t addr,
+static void omap_dma4_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_dma_s *s = (struct omap_dma_s *) opaque;
break;
case 0x1c: /* DMA4_CSSA */
- ch->addr[0] = (target_phys_addr_t) (uint32_t) value;
+ ch->addr[0] = (hwaddr) (uint32_t) value;
ch->set_update = 1;
break;
case 0x20: /* DMA4_CDSA */
- ch->addr[1] = (target_phys_addr_t) (uint32_t) value;
+ ch->addr[1] = (hwaddr) (uint32_t) value;
ch->set_update = 1;
break;
.endianness = DEVICE_NATIVE_ENDIAN,
};
-struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,
+struct soc_dma_s *omap_dma4_init(hwaddr base, qemu_irq *irqs,
MemoryRegion *sysmem,
struct omap_mpu_state_s *mpu, int fifo,
int chans, omap_clk iclk, omap_clk fclk)
int nx;
int ny;
- target_phys_addr_t addr[3];
+ hwaddr addr[3];
uint32_t attr;
uint32_t tresh;
omap_dispc_interrupt_update(s);
}
-static uint64_t omap_diss_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_diss_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
return 0;
}
-static void omap_diss_write(void *opaque, target_phys_addr_t addr,
+static void omap_diss_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static uint64_t omap_disc_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_disc_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
return 0;
}
-static void omap_disc_write(void *opaque, target_phys_addr_t addr,
+static void omap_disc_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
s->dispc.invalidate = 1;
break;
case 0x080: /* DISPC_GFX_BA0 */
- s->dispc.l[0].addr[0] = (target_phys_addr_t) value;
+ s->dispc.l[0].addr[0] = (hwaddr) value;
s->dispc.invalidate = 1;
break;
case 0x084: /* DISPC_GFX_BA1 */
- s->dispc.l[0].addr[1] = (target_phys_addr_t) value;
+ s->dispc.l[0].addr[1] = (hwaddr) value;
s->dispc.invalidate = 1;
break;
case 0x088: /* DISPC_GFX_POSITION */
s->dispc.l[0].wininc = value;
break;
case 0x0b8: /* DISPC_GFX_TABLE_BA */
- s->dispc.l[0].addr[2] = (target_phys_addr_t) value;
+ s->dispc.l[0].addr[2] = (hwaddr) value;
s->dispc.invalidate = 1;
break;
static void omap_rfbi_transfer_start(struct omap_dss_s *s)
{
void *data;
- target_phys_addr_t len;
- target_phys_addr_t data_addr;
+ hwaddr len;
+ hwaddr data_addr;
int pitch;
static void *bounce_buffer;
- static target_phys_addr_t bounce_len;
+ static hwaddr bounce_len;
if (!s->rfbi.enable || s->rfbi.busy)
return;
omap_dispc_interrupt_update(s);
}
-static uint64_t omap_rfbi_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_rfbi_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
return 0;
}
-static void omap_rfbi_write(void *opaque, target_phys_addr_t addr,
+static void omap_rfbi_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static uint64_t omap_venc_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_venc_read(void *opaque, hwaddr addr,
unsigned size)
{
if (size != 4) {
return 0;
}
-static void omap_venc_write(void *opaque, target_phys_addr_t addr,
+static void omap_venc_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
if (size != 4) {
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static uint64_t omap_im3_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_im3_read(void *opaque, hwaddr addr,
unsigned size)
{
if (size != 4) {
return 0;
}
-static void omap_im3_write(void *opaque, target_phys_addr_t addr,
+static void omap_im3_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
if (size != 4) {
struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,
MemoryRegion *sysmem,
- target_phys_addr_t l3_base,
+ hwaddr l3_base,
qemu_irq irq, qemu_irq drq,
omap_clk fck1, omap_clk fck2, omap_clk ck54m,
omap_clk ick1, omap_clk ick2)
}
}
-static uint64_t omap_gpio_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_gpio_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
return 0;
}
-static void omap_gpio_write(void *opaque, target_phys_addr_t addr,
+static void omap_gpio_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
s->delay = 0;
}
-static uint32_t omap2_gpio_module_read(void *opaque, target_phys_addr_t addr)
+static uint32_t omap2_gpio_module_read(void *opaque, hwaddr addr)
{
struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
return 0;
}
-static void omap2_gpio_module_write(void *opaque, target_phys_addr_t addr,
+static void omap2_gpio_module_write(void *opaque, hwaddr addr,
uint32_t value)
{
struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
}
}
-static uint32_t omap2_gpio_module_readp(void *opaque, target_phys_addr_t addr)
+static uint32_t omap2_gpio_module_readp(void *opaque, hwaddr addr)
{
return omap2_gpio_module_read(opaque, addr & ~3) >> ((addr & 3) << 3);
}
-static void omap2_gpio_module_writep(void *opaque, target_phys_addr_t addr,
+static void omap2_gpio_module_writep(void *opaque, hwaddr addr,
uint32_t value)
{
uint32_t cur = 0;
s->gpo = 0;
}
-static uint64_t omap2_gpif_top_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap2_gpif_top_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap2_gpif_s *s = (struct omap2_gpif_s *) opaque;
return 0;
}
-static void omap2_gpif_top_write(void *opaque, target_phys_addr_t addr,
+static void omap2_gpif_top_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap2_gpif_s *s = (struct omap2_gpif_s *) opaque;
* all addresses in the region behave like accesses to the relevant
* GPMC_NAND_DATA_i register (which is actually implemented to call these)
*/
-static uint64_t omap_nand_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_nand_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_gpmc_cs_file_s *f = (struct omap_gpmc_cs_file_s *)opaque;
}
}
-static void omap_nand_write(void *opaque, target_phys_addr_t addr,
+static void omap_nand_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_gpmc_cs_file_s *f = (struct omap_gpmc_cs_file_s *)opaque;
* engine is enabled -- all addresses in the region behave alike:
* data is read or written to the FIFO.
*/
-static uint64_t omap_gpmc_prefetch_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_gpmc_prefetch_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
return data;
}
-static void omap_gpmc_prefetch_write(void *opaque, target_phys_addr_t addr,
+static void omap_gpmc_prefetch_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
ecc_reset(&s->ecc[i]);
}
-static int gpmc_wordaccess_only(target_phys_addr_t addr)
+static int gpmc_wordaccess_only(hwaddr addr)
{
/* Return true if the register offset is to a register that
* only permits word width accesses.
return 1;
}
-static uint64_t omap_gpmc_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_gpmc_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
return 0;
}
-static void omap_gpmc_write(void *opaque, target_phys_addr_t addr,
+static void omap_gpmc_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
};
struct omap_gpmc_s *omap_gpmc_init(struct omap_mpu_state_s *mpu,
- target_phys_addr_t base,
+ hwaddr base,
qemu_irq irq, qemu_irq drq)
{
int cs;
omap_gp_timer_update(s);
}
-static uint32_t omap_gp_timer_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t omap_gp_timer_readw(void *opaque, hwaddr addr)
{
struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
return 0;
}
-static uint32_t omap_gp_timer_readh(void *opaque, target_phys_addr_t addr)
+static uint32_t omap_gp_timer_readh(void *opaque, hwaddr addr)
{
struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
uint32_t ret;
}
}
-static void omap_gp_timer_write(void *opaque, target_phys_addr_t addr,
+static void omap_gp_timer_write(void *opaque, hwaddr addr,
uint32_t value)
{
struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
}
}
-static void omap_gp_timer_writeh(void *opaque, target_phys_addr_t addr,
+static void omap_gp_timer_writeh(void *opaque, hwaddr addr,
uint32_t value)
{
struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
s->test = 0;
}
-static uint32_t omap_i2c_read(void *opaque, target_phys_addr_t addr)
+static uint32_t omap_i2c_read(void *opaque, hwaddr addr)
{
OMAPI2CState *s = opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
return 0;
}
-static void omap_i2c_write(void *opaque, target_phys_addr_t addr,
+static void omap_i2c_write(void *opaque, hwaddr addr,
uint32_t value)
{
OMAPI2CState *s = opaque;
}
}
-static void omap_i2c_writeb(void *opaque, target_phys_addr_t addr,
+static void omap_i2c_writeb(void *opaque, hwaddr addr,
uint32_t value)
{
OMAPI2CState *s = opaque;
bank->irqs = (bank->inputs &= ~(1 << n)) | bank->swi;
}
-static uint64_t omap_inth_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_inth_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
return 0;
}
-static void omap_inth_write(void *opaque, target_phys_addr_t addr,
+static void omap_inth_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
.class_init = omap_intc_class_init,
};
-static uint64_t omap2_inth_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap2_inth_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
return 0;
}
-static void omap2_inth_write(void *opaque, target_phys_addr_t addr,
+static void omap2_inth_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
struct omap_l4_s {
MemoryRegion *address_space;
- target_phys_addr_t base;
+ hwaddr base;
int ta_num;
struct omap_target_agent_s ta[0];
};
struct omap_l4_s *omap_l4_init(MemoryRegion *address_space,
- target_phys_addr_t base, int ta_num)
+ hwaddr base, int ta_num)
{
struct omap_l4_s *bus = g_malloc0(
sizeof(*bus) + ta_num * sizeof(*bus->ta));
return bus;
}
-target_phys_addr_t omap_l4_region_base(struct omap_target_agent_s *ta,
+hwaddr omap_l4_region_base(struct omap_target_agent_s *ta,
int region)
{
return ta->bus->base + ta->start[region].offset;
}
-target_phys_addr_t omap_l4_region_size(struct omap_target_agent_s *ta,
+hwaddr omap_l4_region_size(struct omap_target_agent_s *ta,
int region)
{
return ta->start[region].size;
}
-static uint64_t omap_l4ta_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_l4ta_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;
return 0;
}
-static void omap_l4ta_write(void *opaque, target_phys_addr_t addr,
+static void omap_l4ta_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;
return ta;
}
-target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta,
+hwaddr omap_l4_attach(struct omap_target_agent_s *ta,
int region, MemoryRegion *mr)
{
- target_phys_addr_t base;
+ hwaddr base;
if (region < 0 || region >= ta->regions) {
fprintf(stderr, "%s: bad io region (%i)\n", __FUNCTION__, region);
draw_line_func draw_line;
int size, height, first, last;
int width, linesize, step, bpp, frame_offset;
- target_phys_addr_t frame_base;
+ hwaddr frame_base;
if (!omap_lcd || omap_lcd->plm == 1 ||
!omap_lcd->enable || !ds_get_bits_per_pixel(omap_lcd->state))
}
}
-static uint64_t omap_lcdc_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_lcdc_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque;
return 0;
}
-static void omap_lcdc_write(void *opaque, target_phys_addr_t addr,
+static void omap_lcdc_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque;
}
struct omap_lcd_panel_s *omap_lcdc_init(MemoryRegion *sysmem,
- target_phys_addr_t base,
+ hwaddr base,
qemu_irq irq,
struct omap_dma_lcd_channel_s *dma,
omap_clk clk)
host->clkdiv = 0;
}
-static uint64_t omap_mmc_read(void *opaque, target_phys_addr_t offset,
+static uint64_t omap_mmc_read(void *opaque, hwaddr offset,
unsigned size)
{
uint16_t i;
return 0;
}
-static void omap_mmc_write(void *opaque, target_phys_addr_t offset,
+static void omap_mmc_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
int i;
}
}
-struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base,
+struct omap_mmc_s *omap_mmc_init(hwaddr base,
MemoryRegion *sysmem,
BlockDriverState *bd,
qemu_irq irq, qemu_irq dma[], omap_clk clk)
s->config = 0x10;
}
-static uint64_t omap_sdrc_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_sdrc_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque;
return 0;
}
-static void omap_sdrc_write(void *opaque, target_phys_addr_t addr,
+static void omap_sdrc_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque;
};
struct omap_sdrc_s *omap_sdrc_init(MemoryRegion *sysmem,
- target_phys_addr_t base)
+ hwaddr base)
{
struct omap_sdrc_s *s = (struct omap_sdrc_s *)
g_malloc0(sizeof(struct omap_sdrc_s));
omap_mcspi_interrupt_update(s);
}
-static uint64_t omap_mcspi_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_mcspi_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
return 0;
}
-static void omap_mcspi_write(void *opaque, target_phys_addr_t addr,
+static void omap_mcspi_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
* - 1 RTC
*/
-static uint64_t static_read(void *opaque, target_phys_addr_t offset,
+static uint64_t static_read(void *opaque, hwaddr offset,
unsigned size)
{
uint32_t *val = (uint32_t *) opaque;
return *val >> ((offset & mask) << 3);
}
-static void static_write(void *opaque, target_phys_addr_t offset,
+static void static_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
#ifdef SPY
s->val = omap_synctimer_read(s);
}
-static uint32_t omap_synctimer_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t omap_synctimer_readw(void *opaque, hwaddr addr)
{
struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque;
return 0;
}
-static uint32_t omap_synctimer_readh(void *opaque, target_phys_addr_t addr)
+static uint32_t omap_synctimer_readh(void *opaque, hwaddr addr)
{
struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque;
uint32_t ret;
}
}
-static void omap_synctimer_write(void *opaque, target_phys_addr_t addr,
+static void omap_synctimer_write(void *opaque, hwaddr addr,
uint32_t value)
{
OMAP_BAD_REG(addr);
#include "omap.h"
/* TEST-Chip-level TAP */
-static uint64_t omap_tap_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_tap_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
return 0;
}
-static void omap_tap_write(void *opaque, target_phys_addr_t addr,
+static void omap_tap_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
if (size != 4) {
/* UARTs */
struct omap_uart_s {
MemoryRegion iomem;
- target_phys_addr_t base;
+ hwaddr base;
SerialState *serial; /* TODO */
struct omap_target_agent_s *ta;
omap_clk fclk;
s->clksel = 0;
}
-struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
+struct omap_uart_s *omap_uart_init(hwaddr base,
qemu_irq irq, omap_clk fclk, omap_clk iclk,
qemu_irq txdma, qemu_irq rxdma,
const char *label, CharDriverState *chr)
return s;
}
-static uint64_t omap_uart_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_uart_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_uart_s *s = (struct omap_uart_s *) opaque;
return 0;
}
-static void omap_uart_write(void *opaque, target_phys_addr_t addr,
+static void omap_uart_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_uart_s *s = (struct omap_uart_s *) opaque;
qemu_irq txdma, qemu_irq rxdma,
const char *label, CharDriverState *chr)
{
- target_phys_addr_t base = omap_l4_attach(ta, 0, NULL);
+ hwaddr base = omap_l4_attach(ta, 0, NULL);
struct omap_uart_s *s = omap_uart_init(base, irq,
fclk, iclk, txdma, rxdma, label, chr);
uint16_t ver;
} id;
int shift;
- target_phys_addr_t base;
+ hwaddr base;
qemu_irq intr;
qemu_irq rdy;
BlockDriverState *bdrv;
onenand_intr_update(s);
}
-static uint64_t onenand_read(void *opaque, target_phys_addr_t addr,
+static uint64_t onenand_read(void *opaque, hwaddr addr,
unsigned size)
{
OneNANDState *s = (OneNANDState *) opaque;
return 0;
}
-static void onenand_write(void *opaque, target_phys_addr_t addr,
+static void onenand_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
OneNANDState *s = (OneNANDState *) opaque;
OneNANDState *s = (OneNANDState *)dev;
uint32_t size = 1 << (24 + ((s->id.dev >> 4) & 7));
void *ram;
- s->base = (target_phys_addr_t)-1;
+ s->base = (hwaddr)-1;
s->rdy = NULL;
s->blocks = size >> BLOCK_SHIFT;
s->secs = size >> 9;
}
static uint64_t open_eth_reg_read(void *opaque,
- target_phys_addr_t addr, unsigned int size)
+ hwaddr addr, unsigned int size)
{
static uint32_t (*reg_read[REG_MAX])(OpenEthState *s) = {
};
}
static void open_eth_reg_write(void *opaque,
- target_phys_addr_t addr, uint64_t val, unsigned int size)
+ hwaddr addr, uint64_t val, unsigned int size)
{
static void (*reg_write[REG_MAX])(OpenEthState *s, uint32_t val) = {
[MODER] = open_eth_moder_host_write,
}
static uint64_t open_eth_desc_read(void *opaque,
- target_phys_addr_t addr, unsigned int size)
+ hwaddr addr, unsigned int size)
{
OpenEthState *s = opaque;
uint64_t v = 0;
}
static void open_eth_desc_write(void *opaque,
- target_phys_addr_t addr, uint64_t val, unsigned int size)
+ hwaddr addr, uint64_t val, unsigned int size)
{
OpenEthState *s = opaque;
return cpu_single_env->cpu_index;
}
-static uint32_t openpic_cpu_read_internal(void *opaque, target_phys_addr_t addr,
+static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr,
int idx);
-static void openpic_cpu_write_internal(void *opaque, target_phys_addr_t addr,
+static void openpic_cpu_write_internal(void *opaque, hwaddr addr,
uint32_t val, int idx);
enum {
#endif
#endif /* 0 : Code provision for Intel model */
-static void openpic_gbl_write (void *opaque, target_phys_addr_t addr, uint32_t val)
+static void openpic_gbl_write (void *opaque, hwaddr addr, uint32_t val)
{
openpic_t *opp = opaque;
IRQ_dst_t *dst;
}
}
-static uint32_t openpic_gbl_read (void *opaque, target_phys_addr_t addr)
+static uint32_t openpic_gbl_read (void *opaque, hwaddr addr)
{
openpic_t *opp = opaque;
uint32_t retval;
return retval;
}
-static void openpic_cpu_write_internal(void *opaque, target_phys_addr_t addr,
+static void openpic_cpu_write_internal(void *opaque, hwaddr addr,
uint32_t val, int idx)
{
openpic_t *opp = opaque;
}
}
-static void openpic_cpu_write(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void openpic_cpu_write(void *opaque, hwaddr addr, uint32_t val)
{
openpic_cpu_write_internal(opaque, addr, val, (addr & 0x1f000) >> 12);
}
-static uint32_t openpic_cpu_read_internal(void *opaque, target_phys_addr_t addr,
+static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr,
int idx)
{
openpic_t *opp = opaque;
return retval;
}
-static uint32_t openpic_cpu_read(void *opaque, target_phys_addr_t addr)
+static uint32_t openpic_cpu_read(void *opaque, hwaddr addr)
{
return openpic_cpu_read_internal(opaque, addr, (addr & 0x1f000) >> 12);
}
static void openpic_buggy_write (void *opaque,
- target_phys_addr_t addr, uint32_t val)
+ hwaddr addr, uint32_t val)
{
printf("Invalid OPENPIC write access !\n");
}
-static uint32_t openpic_buggy_read (void *opaque, target_phys_addr_t addr)
+static uint32_t openpic_buggy_read (void *opaque, hwaddr addr)
{
printf("Invalid OPENPIC read access !\n");
}
static void openpic_writel (void *opaque,
- target_phys_addr_t addr, uint32_t val)
+ hwaddr addr, uint32_t val)
{
openpic_t *opp = opaque;
}
}
-static uint32_t openpic_readl (void *opaque,target_phys_addr_t addr)
+static uint32_t openpic_readl (void *opaque,hwaddr addr)
{
openpic_t *opp = opaque;
uint32_t retval;
return retval;
}
-static uint64_t openpic_read(void *opaque, target_phys_addr_t addr,
+static uint64_t openpic_read(void *opaque, hwaddr addr,
unsigned size)
{
openpic_t *opp = opaque;
}
}
-static void openpic_write(void *opaque, target_phys_addr_t addr,
+static void openpic_write(void *opaque, hwaddr addr,
uint64_t data, unsigned size)
{
openpic_t *opp = opaque;
mpp->glbc = 0x00000000;
}
-static void mpic_timer_write (void *opaque, target_phys_addr_t addr, uint32_t val)
+static void mpic_timer_write (void *opaque, hwaddr addr, uint32_t val)
{
openpic_t *mpp = opaque;
int idx, cpu;
}
}
-static uint32_t mpic_timer_read (void *opaque, target_phys_addr_t addr)
+static uint32_t mpic_timer_read (void *opaque, hwaddr addr)
{
openpic_t *mpp = opaque;
uint32_t retval;
return retval;
}
-static void mpic_src_ext_write (void *opaque, target_phys_addr_t addr,
+static void mpic_src_ext_write (void *opaque, hwaddr addr,
uint32_t val)
{
openpic_t *mpp = opaque;
}
}
-static uint32_t mpic_src_ext_read (void *opaque, target_phys_addr_t addr)
+static uint32_t mpic_src_ext_read (void *opaque, hwaddr addr)
{
openpic_t *mpp = opaque;
uint32_t retval;
return retval;
}
-static void mpic_src_int_write (void *opaque, target_phys_addr_t addr,
+static void mpic_src_int_write (void *opaque, hwaddr addr,
uint32_t val)
{
openpic_t *mpp = opaque;
}
}
-static uint32_t mpic_src_int_read (void *opaque, target_phys_addr_t addr)
+static uint32_t mpic_src_int_read (void *opaque, hwaddr addr)
{
openpic_t *mpp = opaque;
uint32_t retval;
return retval;
}
-static void mpic_src_msg_write (void *opaque, target_phys_addr_t addr,
+static void mpic_src_msg_write (void *opaque, hwaddr addr,
uint32_t val)
{
openpic_t *mpp = opaque;
}
}
-static uint32_t mpic_src_msg_read (void *opaque, target_phys_addr_t addr)
+static uint32_t mpic_src_msg_read (void *opaque, hwaddr addr)
{
openpic_t *mpp = opaque;
uint32_t retval;
return retval;
}
-static void mpic_src_msi_write (void *opaque, target_phys_addr_t addr,
+static void mpic_src_msi_write (void *opaque, hwaddr addr,
uint32_t val)
{
openpic_t *mpp = opaque;
}
}
}
-static uint32_t mpic_src_msi_read (void *opaque, target_phys_addr_t addr)
+static uint32_t mpic_src_msi_read (void *opaque, hwaddr addr)
{
openpic_t *mpp = opaque;
uint32_t retval;
.endianness = DEVICE_BIG_ENDIAN,
};
-qemu_irq *mpic_init (MemoryRegion *address_space, target_phys_addr_t base,
+qemu_irq *mpic_init (MemoryRegion *address_space, hwaddr base,
int nb_cpus, qemu_irq **irqs, qemu_irq irq_out)
{
openpic_t *mpp;
struct {
const char *name;
MemoryRegionOps const *ops;
- target_phys_addr_t start_addr;
+ hwaddr start_addr;
ram_addr_t size;
} const list[] = {
{"glb", &mpic_glb_ops, MPIC_GLB_REG_START, MPIC_GLB_REG_SIZE},
qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
qemu_irq **irqs, qemu_irq irq_out);
-qemu_irq *mpic_init (MemoryRegion *address_space, target_phys_addr_t base,
+qemu_irq *mpic_init (MemoryRegion *address_space, hwaddr base,
int nb_cpus, qemu_irq **irqs, qemu_irq irq_out);
#endif /* __OPENPIC_H__ */
}
static void openrisc_sim_net_init(MemoryRegion *address_space,
- target_phys_addr_t base,
- target_phys_addr_t descriptors,
+ hwaddr base,
+ hwaddr descriptors,
qemu_irq irq, NICInfo *nd)
{
DeviceState *dev;
{
long kernel_size;
uint64_t elf_entry;
- target_phys_addr_t entry;
+ hwaddr entry;
if (kernel_filename && !qtest_enabled()) {
kernel_size = load_elf(kernel_filename, NULL, NULL,
#include "loader.h"
#include "exec-memory.h"
-static uint32_t static_readb(void *opaque, target_phys_addr_t offset)
+static uint32_t static_readb(void *opaque, hwaddr offset)
{
uint32_t *val = (uint32_t *) opaque;
return *val >> ((offset & 3) << 3);
}
-static uint32_t static_readh(void *opaque, target_phys_addr_t offset)
+static uint32_t static_readh(void *opaque, hwaddr offset)
{
uint32_t *val = (uint32_t *) opaque;
return *val >> ((offset & 1) << 3);
}
-static uint32_t static_readw(void *opaque, target_phys_addr_t offset)
+static uint32_t static_readw(void *opaque, hwaddr offset)
{
uint32_t *val = (uint32_t *) opaque;
return *val >> ((offset & 0) << 3);
}
-static void static_write(void *opaque, target_phys_addr_t offset,
+static void static_write(void *opaque, hwaddr offset,
uint32_t value)
{
#ifdef SPY
}
/* Memory mapped interface */
-static uint32_t parallel_mm_readb (void *opaque, target_phys_addr_t addr)
+static uint32_t parallel_mm_readb (void *opaque, hwaddr addr)
{
ParallelState *s = opaque;
}
static void parallel_mm_writeb (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
ParallelState *s = opaque;
parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFF);
}
-static uint32_t parallel_mm_readw (void *opaque, target_phys_addr_t addr)
+static uint32_t parallel_mm_readw (void *opaque, hwaddr addr)
{
ParallelState *s = opaque;
}
static void parallel_mm_writew (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
ParallelState *s = opaque;
parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFFFF);
}
-static uint32_t parallel_mm_readl (void *opaque, target_phys_addr_t addr)
+static uint32_t parallel_mm_readl (void *opaque, hwaddr addr)
{
ParallelState *s = opaque;
}
static void parallel_mm_writel (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
ParallelState *s = opaque;
/* If fd is zero, it means that the parallel device uses the console */
bool parallel_mm_init(MemoryRegion *address_space,
- target_phys_addr_t base, int it_shift, qemu_irq irq,
+ hwaddr base, int it_shift, qemu_irq irq,
CharDriverState *chr)
{
ParallelState *s;
const char *kernel_filename,
const char *initrd_filename,
const char *kernel_cmdline,
- target_phys_addr_t max_ram_size)
+ hwaddr max_ram_size)
{
uint16_t protocol;
int setup_size, kernel_size, initrd_size = 0, cmdline_size;
uint32_t initrd_max;
uint8_t header[8192], *setup, *kernel, *initrd_data;
- target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
+ hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
FILE *f;
char *vmode;
}
bool parallel_mm_init(MemoryRegion *address_space,
- target_phys_addr_t base, int it_shift, qemu_irq irq,
+ hwaddr base, int it_shift, qemu_irq irq,
CharDriverState *chr);
/* i8259.c */
void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
MemoryRegion *region, ram_addr_t size,
- target_phys_addr_t mask);
+ hwaddr mask);
void i8042_isa_mouse_fake_event(void *opaque);
void i8042_setup_a20_line(ISADevice *dev, qemu_irq *a20_out);
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
ram_addr_t ram_size,
- target_phys_addr_t pci_hole_start,
- target_phys_addr_t pci_hole_size,
- target_phys_addr_t pci_hole64_start,
- target_phys_addr_t pci_hole64_size,
+ hwaddr pci_hole_start,
+ hwaddr pci_hole_size,
+ hwaddr pci_hole64_start,
+ hwaddr pci_hole64_size,
MemoryRegion *pci_memory,
MemoryRegion *ram_memory);
extern enum vga_retrace_method vga_retrace_method;
-int isa_vga_mm_init(target_phys_addr_t vram_base,
- target_phys_addr_t ctrl_base, int it_shift,
+int isa_vga_mm_init(hwaddr vram_base,
+ hwaddr ctrl_base, int it_shift,
MemoryRegion *address_space);
/* ne2000.c */
below_4g_mem_size,
0x100000000ULL - below_4g_mem_size,
0x100000000ULL + above_4g_mem_size,
- (sizeof(target_phys_addr_t) == 4
+ (sizeof(hwaddr) == 4
? 0
: ((uint64_t)1 << 62)),
pci_memory, ram_memory);
{
BlockDriverState *bdrv;
int64_t size;
- target_phys_addr_t phys_addr;
+ hwaddr phys_addr;
int sector_bits, sector_size;
pflash_t *system_flash;
MemoryRegion *flash_mem;
* to >4G. Check it. TODO: we might need to support
* it in the future for e.g. PAE.
*/
- if (last_addr >= TARGET_PHYS_ADDR_MAX) {
+ if (last_addr >= HWADDR_MAX) {
return PCI_BAR_UNMAPPED;
}
return val;
}
-static void pci_host_config_write(void *opaque, target_phys_addr_t addr,
+static void pci_host_config_write(void *opaque, hwaddr addr,
uint64_t val, unsigned len)
{
PCIHostState *s = opaque;
s->config_reg = val;
}
-static uint64_t pci_host_config_read(void *opaque, target_phys_addr_t addr,
+static uint64_t pci_host_config_read(void *opaque, hwaddr addr,
unsigned len)
{
PCIHostState *s = opaque;
return val;
}
-static void pci_host_data_write(void *opaque, target_phys_addr_t addr,
+static void pci_host_data_write(void *opaque, hwaddr addr,
uint64_t val, unsigned len)
{
PCIHostState *s = opaque;
}
static uint64_t pci_host_data_read(void *opaque,
- target_phys_addr_t addr, unsigned len)
+ hwaddr addr, unsigned len)
{
PCIHostState *s = opaque;
uint32_t val;
PCIE_MMCFG_DEVFN(mmcfg_addr));
}
-static void pcie_mmcfg_data_write(void *opaque, target_phys_addr_t mmcfg_addr,
+static void pcie_mmcfg_data_write(void *opaque, hwaddr mmcfg_addr,
uint64_t val, unsigned len)
{
PCIExpressHost *e = opaque;
}
static uint64_t pcie_mmcfg_data_read(void *opaque,
- target_phys_addr_t mmcfg_addr,
+ hwaddr mmcfg_addr,
unsigned len)
{
PCIExpressHost *e = opaque;
};
/* pcie_host::base_addr == PCIE_BASE_ADDR_UNMAPPED when it isn't mapped. */
-#define PCIE_BASE_ADDR_UNMAPPED ((target_phys_addr_t)-1ULL)
+#define PCIE_BASE_ADDR_UNMAPPED ((hwaddr)-1ULL)
int pcie_host_init(PCIExpressHost *e, uint32_t size)
{
}
}
-void pcie_host_mmcfg_map(PCIExpressHost *e, target_phys_addr_t addr)
+void pcie_host_mmcfg_map(PCIExpressHost *e, hwaddr addr)
{
e->base_addr = addr;
memory_region_add_subregion(get_system_memory(), e->base_addr, &e->mmio);
void pcie_host_mmcfg_update(PCIExpressHost *e,
int enable,
- target_phys_addr_t addr)
+ hwaddr addr)
{
pcie_host_mmcfg_unmap(e);
if (enable) {
/* express part */
/* base address where MMCONFIG area is mapped. */
- target_phys_addr_t base_addr;
+ hwaddr base_addr;
/* the size of MMCONFIG area. It's host bridge dependent */
- target_phys_addr_t size;
+ hwaddr size;
/* MMCONFIG mmio area */
MemoryRegion mmio;
int pcie_host_init(PCIExpressHost *e, uint32_t size);
void pcie_host_mmcfg_unmap(PCIExpressHost *e);
-void pcie_host_mmcfg_map(PCIExpressHost *e, target_phys_addr_t addr);
+void pcie_host_mmcfg_map(PCIExpressHost *e, hwaddr addr);
void pcie_host_mmcfg_update(PCIExpressHost *e,
int enable,
- target_phys_addr_t addr);
+ hwaddr addr);
#endif /* PCIE_HOST_H */
qemu_irq irq_kbd;
qemu_irq irq_mouse;
qemu_irq *a20_out;
- target_phys_addr_t mask;
+ hwaddr mask;
} KBDState;
/* update irq and KBD_STAT_[MOUSE_]OBF */
};
/* Memory mapped interface */
-static uint32_t kbd_mm_readb (void *opaque, target_phys_addr_t addr)
+static uint32_t kbd_mm_readb (void *opaque, hwaddr addr)
{
KBDState *s = opaque;
return kbd_read_data(s, 0) & 0xff;
}
-static void kbd_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
+static void kbd_mm_writeb (void *opaque, hwaddr addr, uint32_t value)
{
KBDState *s = opaque;
void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
MemoryRegion *region, ram_addr_t size,
- target_phys_addr_t mask)
+ hwaddr mask)
{
KBDState *s = g_malloc0(sizeof(KBDState));
return val;
}
-static uint64_t pcnet_ioport_read(void *opaque, target_phys_addr_t addr,
+static uint64_t pcnet_ioport_read(void *opaque, hwaddr addr,
unsigned size)
{
PCNetState *d = opaque;
return ((uint64_t)1 << (size * 8)) - 1;
}
-static void pcnet_ioport_write(void *opaque, target_phys_addr_t addr,
+static void pcnet_ioport_write(void *opaque, hwaddr addr,
uint64_t data, unsigned size)
{
PCNetState *d = opaque;
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static void pcnet_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void pcnet_mmio_writeb(void *opaque, hwaddr addr, uint32_t val)
{
PCNetState *d = opaque;
#ifdef PCNET_DEBUG_IO
pcnet_aprom_writeb(d, addr & 0x0f, val);
}
-static uint32_t pcnet_mmio_readb(void *opaque, target_phys_addr_t addr)
+static uint32_t pcnet_mmio_readb(void *opaque, hwaddr addr)
{
PCNetState *d = opaque;
uint32_t val = -1;
return val;
}
-static void pcnet_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void pcnet_mmio_writew(void *opaque, hwaddr addr, uint32_t val)
{
PCNetState *d = opaque;
#ifdef PCNET_DEBUG_IO
}
}
-static uint32_t pcnet_mmio_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t pcnet_mmio_readw(void *opaque, hwaddr addr)
{
PCNetState *d = opaque;
uint32_t val = -1;
return val;
}
-static void pcnet_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void pcnet_mmio_writel(void *opaque, hwaddr addr, uint32_t val)
{
PCNetState *d = opaque;
#ifdef PCNET_DEBUG_IO
}
}
-static uint32_t pcnet_mmio_readl(void *opaque, target_phys_addr_t addr)
+static uint32_t pcnet_mmio_readl(void *opaque, hwaddr addr)
{
PCNetState *d = opaque;
uint32_t val;
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static void pci_physical_memory_write(void *dma_opaque, target_phys_addr_t addr,
+static void pci_physical_memory_write(void *dma_opaque, hwaddr addr,
uint8_t *buf, int len, int do_bswap)
{
pci_dma_write(dma_opaque, addr, buf, len);
}
-static void pci_physical_memory_read(void *dma_opaque, target_phys_addr_t addr,
+static void pci_physical_memory_read(void *dma_opaque, hwaddr addr,
uint8_t *buf, int len, int do_bswap)
{
pci_dma_read(dma_opaque, addr, buf, len);
GET_FIELD((R)->msg_length, RMDM, ZEROS))
static inline void pcnet_tmd_load(PCNetState *s, struct pcnet_TMD *tmd,
- target_phys_addr_t addr)
+ hwaddr addr)
{
if (!BCR_SSIZE32(s)) {
struct {
}
static inline void pcnet_tmd_store(PCNetState *s, const struct pcnet_TMD *tmd,
- target_phys_addr_t addr)
+ hwaddr addr)
{
if (!BCR_SSIZE32(s)) {
struct {
}
static inline void pcnet_rmd_load(PCNetState *s, struct pcnet_RMD *rmd,
- target_phys_addr_t addr)
+ hwaddr addr)
{
if (!BCR_SSIZE32(s)) {
struct {
}
static inline void pcnet_rmd_store(PCNetState *s, struct pcnet_RMD *rmd,
- target_phys_addr_t addr)
+ hwaddr addr)
{
if (!BCR_SSIZE32(s)) {
struct {
return 0;
}
-static inline target_phys_addr_t pcnet_rdra_addr(PCNetState *s, int idx)
+static inline hwaddr pcnet_rdra_addr(PCNetState *s, int idx)
{
while (idx < 1) idx += CSR_RCVRL(s);
return s->rdra + ((CSR_RCVRL(s) - idx) * (BCR_SWSTYLE(s) ? 16 : 8));
if (s->rdra) {
int bad = 0;
#if 1
- target_phys_addr_t crda = pcnet_rdra_addr(s, CSR_RCVRC(s));
- target_phys_addr_t nrda = pcnet_rdra_addr(s, -1 + CSR_RCVRC(s));
- target_phys_addr_t nnrd = pcnet_rdra_addr(s, -2 + CSR_RCVRC(s));
+ hwaddr crda = pcnet_rdra_addr(s, CSR_RCVRC(s));
+ hwaddr nrda = pcnet_rdra_addr(s, -1 + CSR_RCVRC(s));
+ hwaddr nnrd = pcnet_rdra_addr(s, -2 + CSR_RCVRC(s));
#else
- target_phys_addr_t crda = s->rdra +
+ hwaddr crda = s->rdra +
(CSR_RCVRL(s) - CSR_RCVRC(s)) *
(BCR_SWSTYLE(s) ? 16 : 8 );
int nrdc = CSR_RCVRC(s)<=1 ? CSR_RCVRL(s) : CSR_RCVRC(s)-1;
- target_phys_addr_t nrda = s->rdra +
+ hwaddr nrda = s->rdra +
(CSR_RCVRL(s) - nrdc) *
(BCR_SWSTYLE(s) ? 16 : 8 );
int nnrc = nrdc<=1 ? CSR_RCVRL(s) : nrdc-1;
- target_phys_addr_t nnrd = s->rdra +
+ hwaddr nnrd = s->rdra +
(CSR_RCVRL(s) - nnrc) *
(BCR_SWSTYLE(s) ? 16 : 8 );
#endif
{
s->csr[34] = s->csr[35] = 0;
if (s->tdra) {
- target_phys_addr_t cxda = s->tdra +
+ hwaddr cxda = s->tdra +
(CSR_XMTRL(s) - CSR_XMTRC(s)) *
(BCR_SWSTYLE(s) ? 16 : 8);
int bad = 0;
if (!(CSR_CRST(s) & 0x8000) && s->rdra) {
struct pcnet_RMD rmd;
int rcvrc = CSR_RCVRC(s)-1,i;
- target_phys_addr_t nrda;
+ hwaddr nrda;
for (i = CSR_RCVRL(s)-1; i > 0; i--, rcvrc--) {
if (rcvrc <= 1)
rcvrc = CSR_RCVRL(s);
CSR_MISSC(s)++;
} else {
uint8_t *src = s->buffer;
- target_phys_addr_t crda = CSR_CRDA(s);
+ hwaddr crda = CSR_CRDA(s);
struct pcnet_RMD rmd;
int pktcount = 0;
#define PCNET_RECV_STORE() do { \
int count = MIN(4096 - GET_FIELD(rmd.buf_length, RMDL, BCNT),remaining); \
- target_phys_addr_t rbadr = PHYSADDR(s, rmd.rbadr); \
+ hwaddr rbadr = PHYSADDR(s, rmd.rbadr); \
s->phys_mem_write(s->dma_opaque, rbadr, src, count, CSR_BSWP(s)); \
src += count; remaining -= count; \
SET_FIELD(&rmd.status, RMDS, OWN, 0); \
remaining = size;
PCNET_RECV_STORE();
if ((remaining > 0) && CSR_NRDA(s)) {
- target_phys_addr_t nrda = CSR_NRDA(s);
+ hwaddr nrda = CSR_NRDA(s);
#ifdef PCNET_DEBUG_RMD
PRINT_RMD(&rmd);
#endif
static void pcnet_transmit(PCNetState *s)
{
- target_phys_addr_t xmit_cxda = 0;
+ hwaddr xmit_cxda = 0;
int count = CSR_XMTRL(s)-1;
int add_crc = 0;
MemoryRegion mmio;
uint8_t buffer[4096];
qemu_irq irq;
- void (*phys_mem_read)(void *dma_opaque, target_phys_addr_t addr,
+ void (*phys_mem_read)(void *dma_opaque, hwaddr addr,
uint8_t *buf, int len, int do_bswap);
- void (*phys_mem_write)(void *dma_opaque, target_phys_addr_t addr,
+ void (*phys_mem_write)(void *dma_opaque, hwaddr addr,
uint8_t *buf, int len, int do_bswap);
void *dma_opaque;
int tx_busy;
return 0;
}
-static uint64_t pcspk_io_read(void *opaque, target_phys_addr_t addr,
+static uint64_t pcspk_io_read(void *opaque, hwaddr addr,
unsigned size)
{
PCSpkState *s = opaque;
(ch.out << 5);
}
-static void pcspk_io_write(void *opaque, target_phys_addr_t addr, uint64_t val,
+static void pcspk_io_write(void *opaque, hwaddr addr, uint64_t val,
unsigned size)
{
PCSpkState *s = opaque;
CPUMBState *env;
DriveInfo *dinfo;
int i;
- target_phys_addr_t ddr_base = MEMORY_BASEADDR;
+ hwaddr ddr_base = MEMORY_BASEADDR;
MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1);
MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
qemu_irq irq[32], *cpu_irq;
CPUMBState *env;
DriveInfo *dinfo;
int i;
- target_phys_addr_t ddr_base = MEMORY_BASEADDR;
+ hwaddr ddr_base = MEMORY_BASEADDR;
MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1);
MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
qemu_irq irq[32], *cpu_irq;
struct pflash_t {
BlockDriverState *bs;
- target_phys_addr_t base;
- target_phys_addr_t sector_len;
- target_phys_addr_t total_len;
+ hwaddr base;
+ hwaddr sector_len;
+ hwaddr total_len;
int width;
int wcycle; /* if 0, the flash is read normally */
int bypass;
uint16_t ident[4];
uint8_t cfi_len;
uint8_t cfi_table[0x52];
- target_phys_addr_t counter;
+ hwaddr counter;
unsigned int writeblock_size;
QEMUTimer *timer;
MemoryRegion mem;
pfl->cmd = 0;
}
-static uint32_t pflash_read (pflash_t *pfl, target_phys_addr_t offset,
+static uint32_t pflash_read (pflash_t *pfl, hwaddr offset,
int width, int be)
{
- target_phys_addr_t boff;
+ hwaddr boff;
uint32_t ret;
uint8_t *p;
}
}
-static inline void pflash_data_write(pflash_t *pfl, target_phys_addr_t offset,
+static inline void pflash_data_write(pflash_t *pfl, hwaddr offset,
uint32_t value, int width, int be)
{
uint8_t *p = pfl->storage;
}
-static void pflash_write(pflash_t *pfl, target_phys_addr_t offset,
+static void pflash_write(pflash_t *pfl, hwaddr offset,
uint32_t value, int width, int be)
{
uint8_t *p;
pfl->status |= 0x80;
if (!pfl->counter) {
- target_phys_addr_t mask = pfl->writeblock_size - 1;
+ hwaddr mask = pfl->writeblock_size - 1;
mask = ~mask;
DPRINTF("%s: block write finished\n", __func__);
}
-static uint32_t pflash_readb_be(void *opaque, target_phys_addr_t addr)
+static uint32_t pflash_readb_be(void *opaque, hwaddr addr)
{
return pflash_read(opaque, addr, 1, 1);
}
-static uint32_t pflash_readb_le(void *opaque, target_phys_addr_t addr)
+static uint32_t pflash_readb_le(void *opaque, hwaddr addr)
{
return pflash_read(opaque, addr, 1, 0);
}
-static uint32_t pflash_readw_be(void *opaque, target_phys_addr_t addr)
+static uint32_t pflash_readw_be(void *opaque, hwaddr addr)
{
pflash_t *pfl = opaque;
return pflash_read(pfl, addr, 2, 1);
}
-static uint32_t pflash_readw_le(void *opaque, target_phys_addr_t addr)
+static uint32_t pflash_readw_le(void *opaque, hwaddr addr)
{
pflash_t *pfl = opaque;
return pflash_read(pfl, addr, 2, 0);
}
-static uint32_t pflash_readl_be(void *opaque, target_phys_addr_t addr)
+static uint32_t pflash_readl_be(void *opaque, hwaddr addr)
{
pflash_t *pfl = opaque;
return pflash_read(pfl, addr, 4, 1);
}
-static uint32_t pflash_readl_le(void *opaque, target_phys_addr_t addr)
+static uint32_t pflash_readl_le(void *opaque, hwaddr addr)
{
pflash_t *pfl = opaque;
return pflash_read(pfl, addr, 4, 0);
}
-static void pflash_writeb_be(void *opaque, target_phys_addr_t addr,
+static void pflash_writeb_be(void *opaque, hwaddr addr,
uint32_t value)
{
pflash_write(opaque, addr, value, 1, 1);
}
-static void pflash_writeb_le(void *opaque, target_phys_addr_t addr,
+static void pflash_writeb_le(void *opaque, hwaddr addr,
uint32_t value)
{
pflash_write(opaque, addr, value, 1, 0);
}
-static void pflash_writew_be(void *opaque, target_phys_addr_t addr,
+static void pflash_writew_be(void *opaque, hwaddr addr,
uint32_t value)
{
pflash_t *pfl = opaque;
pflash_write(pfl, addr, value, 2, 1);
}
-static void pflash_writew_le(void *opaque, target_phys_addr_t addr,
+static void pflash_writew_le(void *opaque, hwaddr addr,
uint32_t value)
{
pflash_t *pfl = opaque;
pflash_write(pfl, addr, value, 2, 0);
}
-static void pflash_writel_be(void *opaque, target_phys_addr_t addr,
+static void pflash_writel_be(void *opaque, hwaddr addr,
uint32_t value)
{
pflash_t *pfl = opaque;
pflash_write(pfl, addr, value, 4, 1);
}
-static void pflash_writel_le(void *opaque, target_phys_addr_t addr,
+static void pflash_writel_le(void *opaque, hwaddr addr,
uint32_t value)
{
pflash_t *pfl = opaque;
.endianness = DEVICE_NATIVE_ENDIAN,
};
-pflash_t *pflash_cfi01_register(target_phys_addr_t base,
+pflash_t *pflash_cfi01_register(hwaddr base,
DeviceState *qdev, const char *name,
- target_phys_addr_t size,
+ hwaddr size,
BlockDriverState *bs, uint32_t sector_len,
int nb_blocs, int width,
uint16_t id0, uint16_t id1,
uint16_t id2, uint16_t id3, int be)
{
pflash_t *pfl;
- target_phys_addr_t total_len;
+ hwaddr total_len;
int ret;
total_len = sector_len * nb_blocs;
struct pflash_t {
BlockDriverState *bs;
- target_phys_addr_t base;
+ hwaddr base;
uint32_t sector_len;
uint32_t chip_len;
int mappings;
static void pflash_setup_mappings(pflash_t *pfl)
{
unsigned i;
- target_phys_addr_t size = memory_region_size(&pfl->orig_mem);
+ hwaddr size = memory_region_size(&pfl->orig_mem);
memory_region_init(&pfl->mem, "pflash", pfl->mappings * size);
pfl->mem_mappings = g_new(MemoryRegion, pfl->mappings);
pfl->cmd = 0;
}
-static uint32_t pflash_read (pflash_t *pfl, target_phys_addr_t offset,
+static uint32_t pflash_read (pflash_t *pfl, hwaddr offset,
int width, int be)
{
- target_phys_addr_t boff;
+ hwaddr boff;
uint32_t ret;
uint8_t *p;
}
}
-static void pflash_write (pflash_t *pfl, target_phys_addr_t offset,
+static void pflash_write (pflash_t *pfl, hwaddr offset,
uint32_t value, int width, int be)
{
- target_phys_addr_t boff;
+ hwaddr boff;
uint8_t *p;
uint8_t cmd;
}
-static uint32_t pflash_readb_be(void *opaque, target_phys_addr_t addr)
+static uint32_t pflash_readb_be(void *opaque, hwaddr addr)
{
return pflash_read(opaque, addr, 1, 1);
}
-static uint32_t pflash_readb_le(void *opaque, target_phys_addr_t addr)
+static uint32_t pflash_readb_le(void *opaque, hwaddr addr)
{
return pflash_read(opaque, addr, 1, 0);
}
-static uint32_t pflash_readw_be(void *opaque, target_phys_addr_t addr)
+static uint32_t pflash_readw_be(void *opaque, hwaddr addr)
{
pflash_t *pfl = opaque;
return pflash_read(pfl, addr, 2, 1);
}
-static uint32_t pflash_readw_le(void *opaque, target_phys_addr_t addr)
+static uint32_t pflash_readw_le(void *opaque, hwaddr addr)
{
pflash_t *pfl = opaque;
return pflash_read(pfl, addr, 2, 0);
}
-static uint32_t pflash_readl_be(void *opaque, target_phys_addr_t addr)
+static uint32_t pflash_readl_be(void *opaque, hwaddr addr)
{
pflash_t *pfl = opaque;
return pflash_read(pfl, addr, 4, 1);
}
-static uint32_t pflash_readl_le(void *opaque, target_phys_addr_t addr)
+static uint32_t pflash_readl_le(void *opaque, hwaddr addr)
{
pflash_t *pfl = opaque;
return pflash_read(pfl, addr, 4, 0);
}
-static void pflash_writeb_be(void *opaque, target_phys_addr_t addr,
+static void pflash_writeb_be(void *opaque, hwaddr addr,
uint32_t value)
{
pflash_write(opaque, addr, value, 1, 1);
}
-static void pflash_writeb_le(void *opaque, target_phys_addr_t addr,
+static void pflash_writeb_le(void *opaque, hwaddr addr,
uint32_t value)
{
pflash_write(opaque, addr, value, 1, 0);
}
-static void pflash_writew_be(void *opaque, target_phys_addr_t addr,
+static void pflash_writew_be(void *opaque, hwaddr addr,
uint32_t value)
{
pflash_t *pfl = opaque;
pflash_write(pfl, addr, value, 2, 1);
}
-static void pflash_writew_le(void *opaque, target_phys_addr_t addr,
+static void pflash_writew_le(void *opaque, hwaddr addr,
uint32_t value)
{
pflash_t *pfl = opaque;
pflash_write(pfl, addr, value, 2, 0);
}
-static void pflash_writel_be(void *opaque, target_phys_addr_t addr,
+static void pflash_writel_be(void *opaque, hwaddr addr,
uint32_t value)
{
pflash_t *pfl = opaque;
pflash_write(pfl, addr, value, 4, 1);
}
-static void pflash_writel_le(void *opaque, target_phys_addr_t addr,
+static void pflash_writel_le(void *opaque, hwaddr addr,
uint32_t value)
{
pflash_t *pfl = opaque;
.endianness = DEVICE_NATIVE_ENDIAN,
};
-pflash_t *pflash_cfi02_register(target_phys_addr_t base,
+pflash_t *pflash_cfi02_register(hwaddr base,
DeviceState *qdev, const char *name,
- target_phys_addr_t size,
+ hwaddr size,
BlockDriverState *bs, uint32_t sector_len,
int nb_blocs, int nb_mappings, int width,
uint16_t id0, uint16_t id1,
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
ram_addr_t ram_size,
- target_phys_addr_t pci_hole_start,
- target_phys_addr_t pci_hole_size,
- target_phys_addr_t pci_hole64_start,
- target_phys_addr_t pci_hole64_size,
+ hwaddr pci_hole_start,
+ hwaddr pci_hole_size,
+ hwaddr pci_hole64_start,
+ hwaddr pci_hole64_size,
MemoryRegion *pci_address_space,
MemoryRegion *ram_memory)
{
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
ram_addr_t ram_size,
- target_phys_addr_t pci_hole_start,
- target_phys_addr_t pci_hole_size,
- target_phys_addr_t pci_hole64_start,
- target_phys_addr_t pci_hole64_size,
+ hwaddr pci_hole_start,
+ hwaddr pci_hole_size,
+ hwaddr pci_hole64_start,
+ hwaddr pci_hole64_size,
MemoryRegion *pci_memory, MemoryRegion *ram_memory)
{
qemu_set_irq(s->irq, flags != 0);
}
-static uint64_t pl011_read(void *opaque, target_phys_addr_t offset,
+static uint64_t pl011_read(void *opaque, hwaddr offset,
unsigned size)
{
pl011_state *s = (pl011_state *)opaque;
s->read_trigger = 1;
}
-static void pl011_write(void *opaque, target_phys_addr_t offset,
+static void pl011_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
pl011_state *s = (pl011_state *)opaque;
pl022_update(s);
}
-static uint64_t pl022_read(void *opaque, target_phys_addr_t offset,
+static uint64_t pl022_read(void *opaque, hwaddr offset,
unsigned size)
{
pl022_state *s = (pl022_state *)opaque;
}
}
-static void pl022_write(void *opaque, target_phys_addr_t offset,
+static void pl022_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
pl022_state *s = (pl022_state *)opaque;
}
}
-static uint64_t pl031_read(void *opaque, target_phys_addr_t offset,
+static uint64_t pl031_read(void *opaque, hwaddr offset,
unsigned size)
{
pl031_state *s = (pl031_state *)opaque;
return 0;
}
-static void pl031_write(void * opaque, target_phys_addr_t offset,
+static void pl031_write(void * opaque, hwaddr offset,
uint64_t value, unsigned size)
{
pl031_state *s = (pl031_state *)opaque;
#if defined(PL041_DEBUG_LEVEL)
-static const char *get_reg_name(target_phys_addr_t offset)
+static const char *get_reg_name(hwaddr offset)
{
if (offset <= PL041_dr1_7) {
return pl041_regs_name[offset >> 2];
pl041_isr1_update(s);
}
-static uint64_t pl041_read(void *opaque, target_phys_addr_t offset,
+static uint64_t pl041_read(void *opaque, hwaddr offset,
unsigned size)
{
pl041_state *s = (pl041_state *)opaque;
return value;
}
-static void pl041_write(void *opaque, target_phys_addr_t offset,
+static void pl041_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
pl041_state *s = (pl041_state *)opaque;
qemu_set_irq(s->irq, raise);
}
-static uint64_t pl050_read(void *opaque, target_phys_addr_t offset,
+static uint64_t pl050_read(void *opaque, hwaddr offset,
unsigned size)
{
pl050_state *s = (pl050_state *)opaque;
}
}
-static void pl050_write(void *opaque, target_phys_addr_t offset,
+static void pl050_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
pl050_state *s = (pl050_state *)opaque;
/* FIXME: Implement input interrupts. */
}
-static uint64_t pl061_read(void *opaque, target_phys_addr_t offset,
+static uint64_t pl061_read(void *opaque, hwaddr offset,
unsigned size)
{
pl061_state *s = (pl061_state *)opaque;
}
}
-static void pl061_write(void *opaque, target_phys_addr_t offset,
+static void pl061_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
pl061_state *s = (pl061_state *)opaque;
}
}
-static uint64_t pl080_read(void *opaque, target_phys_addr_t offset,
+static uint64_t pl080_read(void *opaque, hwaddr offset,
unsigned size)
{
pl080_state *s = (pl080_state *)opaque;
}
}
-static void pl080_write(void *opaque, target_phys_addr_t offset,
+static void pl080_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
pl080_state *s = (pl080_state *)opaque;
/* TODO: Implement interrupts. */
}
-static uint64_t pl110_read(void *opaque, target_phys_addr_t offset,
+static uint64_t pl110_read(void *opaque, hwaddr offset,
unsigned size)
{
pl110_state *s = (pl110_state *)opaque;
}
}
-static void pl110_write(void *opaque, target_phys_addr_t offset,
+static void pl110_write(void *opaque, hwaddr offset,
uint64_t val, unsigned size)
{
pl110_state *s = (pl110_state *)opaque;
}
}
-static uint64_t pl181_read(void *opaque, target_phys_addr_t offset,
+static uint64_t pl181_read(void *opaque, hwaddr offset,
unsigned size)
{
pl181_state *s = (pl181_state *)opaque;
}
}
-static void pl181_write(void *opaque, target_phys_addr_t offset,
+static void pl181_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
pl181_state *s = (pl181_state *)opaque;
pl190_update(s);
}
-static uint64_t pl190_read(void *opaque, target_phys_addr_t offset,
+static uint64_t pl190_read(void *opaque, hwaddr offset,
unsigned size)
{
pl190_state *s = (pl190_state *)opaque;
}
}
-static void pl190_write(void *opaque, target_phys_addr_t offset,
+static void pl190_write(void *opaque, hwaddr offset,
uint64_t val, unsigned size)
{
pl190_state *s = (pl190_state *)opaque;
static int ppce500_load_device_tree(CPUPPCState *env,
PPCE500Params *params,
- target_phys_addr_t addr,
- target_phys_addr_t initrd_base,
- target_phys_addr_t initrd_size)
+ hwaddr addr,
+ hwaddr initrd_base,
+ hwaddr initrd_size)
{
int ret = -1;
uint64_t mem_reg_property[] = { 0, cpu_to_be64(params->ram_size) };
}
/* Create -kernel TLB entries for BookE. */
-static inline target_phys_addr_t booke206_page_size_to_tlb(uint64_t size)
+static inline hwaddr booke206_page_size_to_tlb(uint64_t size)
{
return 63 - clz64(size >> 10);
}
{
struct boot_info *bi = env->load_info;
ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0);
- target_phys_addr_t size, dt_end;
+ hwaddr size, dt_end;
int ps;
/* Our initial TLB entry needs to cover everything from 0 to
CPUPPCState *env = NULL;
uint64_t elf_entry;
uint64_t elf_lowaddr;
- target_phys_addr_t entry=0;
- target_phys_addr_t loadaddr=UIMAGE_LOAD_BASE;
+ hwaddr entry=0;
+ hwaddr loadaddr=UIMAGE_LOAD_BASE;
target_long kernel_size=0;
target_ulong dt_base = 0;
target_ulong initrd_base = 0;
CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem,
MemoryRegion ram_memories[4],
- target_phys_addr_t ram_bases[4],
- target_phys_addr_t ram_sizes[4],
+ hwaddr ram_bases[4],
+ hwaddr ram_sizes[4],
uint32_t sysclk, qemu_irq **picp,
int do_init);
CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem,
MemoryRegion ram_memories[2],
- target_phys_addr_t ram_bases[2],
- target_phys_addr_t ram_sizes[2],
+ hwaddr ram_bases[2],
+ hwaddr ram_sizes[2],
uint32_t sysclk, qemu_irq **picp,
int do_init);
/* IBM STBxxx microcontrollers */
CPUPPCState *ppc_stb025_init (MemoryRegion ram_memories[2],
- target_phys_addr_t ram_bases[2],
- target_phys_addr_t ram_sizes[2],
+ hwaddr ram_bases[2],
+ hwaddr ram_sizes[2],
uint32_t sysclk, qemu_irq **picp,
ram_addr_t *offsetp);
uint8_t reg1;
};
-static uint32_t ref405ep_fpga_readb (void *opaque, target_phys_addr_t addr)
+static uint32_t ref405ep_fpga_readb (void *opaque, hwaddr addr)
{
ref405ep_fpga_t *fpga;
uint32_t ret;
}
static void ref405ep_fpga_writeb (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
ref405ep_fpga_t *fpga;
}
}
-static uint32_t ref405ep_fpga_readw (void *opaque, target_phys_addr_t addr)
+static uint32_t ref405ep_fpga_readw (void *opaque, hwaddr addr)
{
uint32_t ret;
}
static void ref405ep_fpga_writew (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
ref405ep_fpga_writeb(opaque, addr, (value >> 8) & 0xFF);
ref405ep_fpga_writeb(opaque, addr + 1, value & 0xFF);
}
-static uint32_t ref405ep_fpga_readl (void *opaque, target_phys_addr_t addr)
+static uint32_t ref405ep_fpga_readl (void *opaque, hwaddr addr)
{
uint32_t ret;
}
static void ref405ep_fpga_writel (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
ref405ep_fpga_writeb(opaque, addr, (value >> 24) & 0xFF);
ref405ep_fpga_writeb(opaque, addr + 1, (value >> 16) & 0xFF);
MemoryRegion *sram = g_new(MemoryRegion, 1);
ram_addr_t bdloc;
MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories));
- target_phys_addr_t ram_bases[2], ram_sizes[2];
+ hwaddr ram_bases[2], ram_sizes[2];
target_ulong sram_size;
long bios_size;
//int phy_addr = 0;
uint8_t reg1;
};
-static uint32_t taihu_cpld_readb (void *opaque, target_phys_addr_t addr)
+static uint32_t taihu_cpld_readb (void *opaque, hwaddr addr)
{
taihu_cpld_t *cpld;
uint32_t ret;
}
static void taihu_cpld_writeb (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
taihu_cpld_t *cpld;
}
}
-static uint32_t taihu_cpld_readw (void *opaque, target_phys_addr_t addr)
+static uint32_t taihu_cpld_readw (void *opaque, hwaddr addr)
{
uint32_t ret;
}
static void taihu_cpld_writew (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
taihu_cpld_writeb(opaque, addr, (value >> 8) & 0xFF);
taihu_cpld_writeb(opaque, addr + 1, value & 0xFF);
}
-static uint32_t taihu_cpld_readl (void *opaque, target_phys_addr_t addr)
+static uint32_t taihu_cpld_readl (void *opaque, hwaddr addr)
{
uint32_t ret;
}
static void taihu_cpld_writel (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
taihu_cpld_writel(opaque, addr, (value >> 24) & 0xFF);
taihu_cpld_writel(opaque, addr + 1, (value >> 16) & 0xFF);
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *bios;
MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories));
- target_phys_addr_t ram_bases[2], ram_sizes[2];
+ hwaddr ram_bases[2], ram_sizes[2];
long bios_size;
target_ulong kernel_base, initrd_base;
long kernel_size, initrd_size;
uint8_t pr;
};
-static uint32_t opba_readb (void *opaque, target_phys_addr_t addr)
+static uint32_t opba_readb (void *opaque, hwaddr addr)
{
ppc4xx_opba_t *opba;
uint32_t ret;
}
static void opba_writeb (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
ppc4xx_opba_t *opba;
}
}
-static uint32_t opba_readw (void *opaque, target_phys_addr_t addr)
+static uint32_t opba_readw (void *opaque, hwaddr addr)
{
uint32_t ret;
}
static void opba_writew (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
#ifdef DEBUG_OPBA
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
opba_writeb(opaque, addr + 1, value);
}
-static uint32_t opba_readl (void *opaque, target_phys_addr_t addr)
+static uint32_t opba_readl (void *opaque, hwaddr addr)
{
uint32_t ret;
}
static void opba_writel (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
#ifdef DEBUG_OPBA
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
opba->pr = 0x11;
}
-static void ppc4xx_opba_init(target_phys_addr_t base)
+static void ppc4xx_opba_init(hwaddr base)
{
ppc4xx_opba_t *opba;
uint32_t isr1l;
};
-static uint32_t ppc405_gpio_readb (void *opaque, target_phys_addr_t addr)
+static uint32_t ppc405_gpio_readb (void *opaque, hwaddr addr)
{
#ifdef DEBUG_GPIO
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
}
static void ppc405_gpio_writeb (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
#ifdef DEBUG_GPIO
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
#endif
}
-static uint32_t ppc405_gpio_readw (void *opaque, target_phys_addr_t addr)
+static uint32_t ppc405_gpio_readw (void *opaque, hwaddr addr)
{
#ifdef DEBUG_GPIO
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
}
static void ppc405_gpio_writew (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
#ifdef DEBUG_GPIO
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
#endif
}
-static uint32_t ppc405_gpio_readl (void *opaque, target_phys_addr_t addr)
+static uint32_t ppc405_gpio_readl (void *opaque, hwaddr addr)
{
#ifdef DEBUG_GPIO
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
}
static void ppc405_gpio_writel (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
#ifdef DEBUG_GPIO
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
{
}
-static void ppc405_gpio_init(target_phys_addr_t base)
+static void ppc405_gpio_init(hwaddr base)
{
ppc405_gpio_t *gpio;
uint8_t directcntl;
};
-static uint32_t ppc4xx_i2c_readb (void *opaque, target_phys_addr_t addr)
+static uint32_t ppc4xx_i2c_readb (void *opaque, hwaddr addr)
{
ppc4xx_i2c_t *i2c;
uint32_t ret;
}
static void ppc4xx_i2c_writeb (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
ppc4xx_i2c_t *i2c;
}
}
-static uint32_t ppc4xx_i2c_readw (void *opaque, target_phys_addr_t addr)
+static uint32_t ppc4xx_i2c_readw (void *opaque, hwaddr addr)
{
uint32_t ret;
}
static void ppc4xx_i2c_writew (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
#ifdef DEBUG_I2C
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
ppc4xx_i2c_writeb(opaque, addr + 1, value);
}
-static uint32_t ppc4xx_i2c_readl (void *opaque, target_phys_addr_t addr)
+static uint32_t ppc4xx_i2c_readl (void *opaque, hwaddr addr)
{
uint32_t ret;
}
static void ppc4xx_i2c_writel (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
#ifdef DEBUG_I2C
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
i2c->directcntl = 0x0F;
}
-static void ppc405_i2c_init(target_phys_addr_t base, qemu_irq irq)
+static void ppc405_i2c_init(hwaddr base, qemu_irq irq)
{
ppc4xx_i2c_t *i2c;
uint32_t mask[5];
};
-static uint32_t ppc4xx_gpt_readb (void *opaque, target_phys_addr_t addr)
+static uint32_t ppc4xx_gpt_readb (void *opaque, hwaddr addr)
{
#ifdef DEBUG_GPT
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
}
static void ppc4xx_gpt_writeb (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
#ifdef DEBUG_I2C
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
/* XXX: generate a bus fault */
}
-static uint32_t ppc4xx_gpt_readw (void *opaque, target_phys_addr_t addr)
+static uint32_t ppc4xx_gpt_readw (void *opaque, hwaddr addr)
{
#ifdef DEBUG_GPT
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
}
static void ppc4xx_gpt_writew (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
#ifdef DEBUG_I2C
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
/* XXX: TODO */
}
-static uint32_t ppc4xx_gpt_readl (void *opaque, target_phys_addr_t addr)
+static uint32_t ppc4xx_gpt_readl (void *opaque, hwaddr addr)
{
ppc4xx_gpt_t *gpt;
uint32_t ret;
}
static void ppc4xx_gpt_writel (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
ppc4xx_gpt_t *gpt;
int idx;
}
}
-static void ppc4xx_gpt_init(target_phys_addr_t base, qemu_irq irqs[5])
+static void ppc4xx_gpt_init(hwaddr base, qemu_irq irqs[5])
{
ppc4xx_gpt_t *gpt;
int i;
CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem,
MemoryRegion ram_memories[4],
- target_phys_addr_t ram_bases[4],
- target_phys_addr_t ram_sizes[4],
+ hwaddr ram_bases[4],
+ hwaddr ram_sizes[4],
uint32_t sysclk, qemu_irq **picp,
int do_init)
{
CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem,
MemoryRegion ram_memories[2],
- target_phys_addr_t ram_bases[2],
- target_phys_addr_t ram_sizes[2],
+ hwaddr ram_bases[2],
+ hwaddr ram_sizes[2],
uint32_t sysclk, qemu_irq **picp,
int do_init)
{
256<<20, 128<<20, 64<<20, 32<<20, 16<<20, 8<<20, 0
};
-static target_phys_addr_t entry;
+static hwaddr entry;
-static int bamboo_load_device_tree(target_phys_addr_t addr,
+static int bamboo_load_device_tree(hwaddr addr,
uint32_t ramsize,
- target_phys_addr_t initrd_base,
- target_phys_addr_t initrd_size,
+ hwaddr initrd_base,
+ hwaddr initrd_size,
const char *kernel_cmdline)
{
int ret = -1;
/* Create reset TLB entries for BookE, spanning the 32bit addr space. */
static void mmubooke_create_initial_mapping(CPUPPCState *env,
target_ulong va,
- target_phys_addr_t pa)
+ hwaddr pa)
{
ppcemb_tlb_t *tlb = &env->tlb.tlbe[0];
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ram_memories
= g_malloc(PPC440EP_SDRAM_NR_BANKS * sizeof(*ram_memories));
- target_phys_addr_t ram_bases[PPC440EP_SDRAM_NR_BANKS];
- target_phys_addr_t ram_sizes[PPC440EP_SDRAM_NR_BANKS];
+ hwaddr ram_bases[PPC440EP_SDRAM_NR_BANKS];
+ hwaddr ram_sizes[PPC440EP_SDRAM_NR_BANKS];
qemu_irq *pic;
qemu_irq *irqs;
PCIBus *pcibus;
CPUPPCState *env;
uint64_t elf_entry;
uint64_t elf_lowaddr;
- target_phys_addr_t loadaddr = 0;
+ hwaddr loadaddr = 0;
target_long initrd_size = 0;
DeviceState *dev;
int success;
ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
MemoryRegion ram_memories[],
- target_phys_addr_t ram_bases[],
- target_phys_addr_t ram_sizes[],
+ hwaddr ram_bases[],
+ hwaddr ram_sizes[],
const unsigned int sdram_bank_sizes[]);
void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks,
MemoryRegion ram_memories[],
- target_phys_addr_t *ram_bases,
- target_phys_addr_t *ram_sizes,
+ hwaddr *ram_bases,
+ hwaddr *ram_sizes,
int do_init);
#define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
PCIBus *ppc4xx_pci_init(CPUPPCState *env, qemu_irq pci_irqs[4],
- target_phys_addr_t config_space,
- target_phys_addr_t int_ack,
- target_phys_addr_t special_cycle,
- target_phys_addr_t registers);
+ hwaddr config_space,
+ hwaddr int_ack,
+ hwaddr special_cycle,
+ hwaddr registers);
#endif /* !defined(PPC_4XX_H) */
int nbanks;
MemoryRegion containers[4]; /* used for clipping */
MemoryRegion *ram_memories;
- target_phys_addr_t ram_bases[4];
- target_phys_addr_t ram_sizes[4];
+ hwaddr ram_bases[4];
+ hwaddr ram_sizes[4];
uint32_t besr0;
uint32_t besr1;
uint32_t bear;
};
/* XXX: TOFIX: some patches have made this code become inconsistent:
- * there are type inconsistencies, mixing target_phys_addr_t, target_ulong
+ * there are type inconsistencies, mixing hwaddr, target_ulong
* and uint32_t
*/
-static uint32_t sdram_bcr (target_phys_addr_t ram_base,
- target_phys_addr_t ram_size)
+static uint32_t sdram_bcr (hwaddr ram_base,
+ hwaddr ram_size)
{
uint32_t bcr;
return bcr;
}
-static inline target_phys_addr_t sdram_base(uint32_t bcr)
+static inline hwaddr sdram_base(uint32_t bcr)
{
return bcr & 0xFF800000;
}
void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks,
MemoryRegion *ram_memories,
- target_phys_addr_t *ram_bases,
- target_phys_addr_t *ram_sizes,
+ hwaddr *ram_bases,
+ hwaddr *ram_sizes,
int do_init)
{
ppc4xx_sdram_t *sdram;
sdram->irq = irq;
sdram->nbanks = nbanks;
sdram->ram_memories = ram_memories;
- memset(sdram->ram_bases, 0, 4 * sizeof(target_phys_addr_t));
+ memset(sdram->ram_bases, 0, 4 * sizeof(hwaddr));
memcpy(sdram->ram_bases, ram_bases,
- nbanks * sizeof(target_phys_addr_t));
- memset(sdram->ram_sizes, 0, 4 * sizeof(target_phys_addr_t));
+ nbanks * sizeof(hwaddr));
+ memset(sdram->ram_sizes, 0, 4 * sizeof(hwaddr));
memcpy(sdram->ram_sizes, ram_sizes,
- nbanks * sizeof(target_phys_addr_t));
+ nbanks * sizeof(hwaddr));
qemu_register_reset(&sdram_reset, sdram);
ppc_dcr_register(env, SDRAM0_CFGADDR,
sdram, &dcr_read_sdram, &dcr_write_sdram);
* sizes varies by SoC. */
ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
MemoryRegion ram_memories[],
- target_phys_addr_t ram_bases[],
- target_phys_addr_t ram_sizes[],
+ hwaddr ram_bases[],
+ hwaddr ram_sizes[],
const unsigned int sdram_bank_sizes[])
{
ram_addr_t size_left = ram_size;
#define PCI_ALL_SIZE (PCI_REG_BASE + PCI_REG_SIZE)
-static uint64_t pci4xx_cfgaddr_read(void *opaque, target_phys_addr_t addr,
+static uint64_t pci4xx_cfgaddr_read(void *opaque, hwaddr addr,
unsigned size)
{
PPC4xxPCIState *ppc4xx_pci = opaque;
return phb->config_reg;
}
-static void pci4xx_cfgaddr_write(void *opaque, target_phys_addr_t addr,
+static void pci4xx_cfgaddr_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
PPC4xxPCIState *ppc4xx_pci = opaque;
.endianness = DEVICE_LITTLE_ENDIAN,
};
-static void ppc4xx_pci_reg_write4(void *opaque, target_phys_addr_t offset,
+static void ppc4xx_pci_reg_write4(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
struct PPC4xxPCIState *pci = opaque;
}
}
-static uint64_t ppc4xx_pci_reg_read4(void *opaque, target_phys_addr_t offset,
+static uint64_t ppc4xx_pci_reg_read4(void *opaque, hwaddr offset,
unsigned size)
{
struct PPC4xxPCIState *pci = opaque;
/* Mac NVRAM */
typedef struct MacIONVRAMState MacIONVRAMState;
-MacIONVRAMState *macio_nvram_init (target_phys_addr_t size,
+MacIONVRAMState *macio_nvram_init (hwaddr size,
unsigned int it_shift);
void macio_nvram_setup_bar(MacIONVRAMState *s, MemoryRegion *bar,
- target_phys_addr_t mem_base);
+ hwaddr mem_base);
void pmac_format_nvram_partition (MacIONVRAMState *nvr, int len);
uint32_t macio_nvram_read (void *opaque, uint32_t addr);
void macio_nvram_write (void *opaque, uint32_t addr, uint32_t val);
#endif
/* UniN device */
-static void unin_write(void *opaque, target_phys_addr_t addr, uint64_t value,
+static void unin_write(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
UNIN_DPRINTF("write addr " TARGET_FMT_plx " val %"PRIx64"\n", addr, value);
}
-static uint64_t unin_read(void *opaque, target_phys_addr_t addr, unsigned size)
+static uint64_t unin_read(void *opaque, hwaddr addr, unsigned size)
{
uint32_t value;
return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
}
-static target_phys_addr_t round_page(target_phys_addr_t addr)
+static hwaddr round_page(hwaddr addr)
{
return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
}
MemoryRegion *unin_memory = g_new(MemoryRegion, 1);
int linux_boot, i;
MemoryRegion *ram = g_new(MemoryRegion, 1), *bios = g_new(MemoryRegion, 1);
- target_phys_addr_t kernel_base, initrd_base, cmdline_base = 0;
+ hwaddr kernel_base, initrd_base, cmdline_base = 0;
long kernel_size, initrd_size;
PCIBus *pci_bus;
MacIONVRAMState *nvr;
return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
}
-static target_phys_addr_t round_page(target_phys_addr_t addr)
+static hwaddr round_page(hwaddr addr)
{
return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
}
} XCSR;
static void PPC_XCSR_writeb (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
value);
}
static void PPC_XCSR_writew (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
value);
}
static void PPC_XCSR_writel (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
value);
}
-static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr)
+static uint32_t PPC_XCSR_readb (void *opaque, hwaddr addr)
{
uint32_t retval = 0;
return retval;
}
-static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr)
+static uint32_t PPC_XCSR_readw (void *opaque, hwaddr addr)
{
uint32_t retval = 0;
return retval;
}
-static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr)
+static uint32_t PPC_XCSR_readl (void *opaque, hwaddr addr)
{
uint32_t retval = 0;
return retval;
}
-static inline target_phys_addr_t prep_IO_address(sysctrl_t *sysctrl,
- target_phys_addr_t addr)
+static inline hwaddr prep_IO_address(sysctrl_t *sysctrl,
+ hwaddr addr)
{
if (sysctrl->contiguous_map == 0) {
/* 64 KB contiguous space for IOs */
return addr;
}
-static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr,
+static void PPC_prep_io_writeb (void *opaque, hwaddr addr,
uint32_t value)
{
sysctrl_t *sysctrl = opaque;
cpu_outb(addr, value);
}
-static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr)
+static uint32_t PPC_prep_io_readb (void *opaque, hwaddr addr)
{
sysctrl_t *sysctrl = opaque;
uint32_t ret;
return ret;
}
-static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr,
+static void PPC_prep_io_writew (void *opaque, hwaddr addr,
uint32_t value)
{
sysctrl_t *sysctrl = opaque;
cpu_outw(addr, value);
}
-static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr)
+static uint32_t PPC_prep_io_readw (void *opaque, hwaddr addr)
{
sysctrl_t *sysctrl = opaque;
uint32_t ret;
return ret;
}
-static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr,
+static void PPC_prep_io_writel (void *opaque, hwaddr addr,
uint32_t value)
{
sysctrl_t *sysctrl = opaque;
cpu_outl(addr, value);
}
-static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr)
+static uint32_t PPC_prep_io_readl (void *opaque, hwaddr addr)
{
sysctrl_t *sysctrl = opaque;
uint32_t ret;
bios_size = -1;
}
if (bios_size > 0 && bios_size <= BIOS_SIZE) {
- target_phys_addr_t bios_addr;
+ hwaddr bios_addr;
bios_size = (bios_size + 0xfff) & ~0xfff;
bios_addr = (uint32_t)(-bios_size);
bios_size = load_image_targphys(filename, bios_addr, bios_size);
typedef struct PPCE500PCIState PPCE500PCIState;
-static uint64_t pci_reg_read4(void *opaque, target_phys_addr_t addr,
+static uint64_t pci_reg_read4(void *opaque, hwaddr addr,
unsigned size)
{
PPCE500PCIState *pci = opaque;
return value;
}
-static void pci_reg_write4(void *opaque, target_phys_addr_t addr,
+static void pci_reg_write4(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
PPCE500PCIState *pci = opaque;
}
/* Create -kernel TLB entries for BookE, linearly spanning 256MB. */
-static inline target_phys_addr_t booke206_page_size_to_tlb(uint64_t size)
+static inline hwaddr booke206_page_size_to_tlb(uint64_t size)
{
return (ffs(size >> 10) - 1) >> 1;
}
static void mmubooke_create_initial_mapping(CPUPPCState *env,
target_ulong va,
- target_phys_addr_t pa,
- target_phys_addr_t len)
+ hwaddr pa,
+ hwaddr len)
{
ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 1);
- target_phys_addr_t size;
+ hwaddr size;
size = (booke206_page_size_to_tlb(len) << MAS1_TSIZE_SHIFT);
tlb->mas1 = MAS1_VALID | size;
SpinKick *kick = data;
CPUPPCState *env = kick->env;
SpinInfo *curspin = kick->spin;
- target_phys_addr_t map_size = 64 * 1024 * 1024;
- target_phys_addr_t map_start;
+ hwaddr map_size = 64 * 1024 * 1024;
+ hwaddr map_start;
cpu_synchronize_state(env);
stl_p(&curspin->pir, env->spr[SPR_PIR]);
qemu_cpu_kick(env);
}
-static void spin_write(void *opaque, target_phys_addr_t addr, uint64_t value,
+static void spin_write(void *opaque, hwaddr addr, uint64_t value,
unsigned len)
{
SpinState *s = opaque;
}
}
-static uint64_t spin_read(void *opaque, target_phys_addr_t addr, unsigned len)
+static uint64_t spin_read(void *opaque, hwaddr addr, unsigned len)
{
SpinState *s = opaque;
uint8_t *spin_p = &((uint8_t*)s->spin)[addr];
PCIDevice dev;
} RavenPCIState;
-static inline uint32_t PPC_PCIIO_config(target_phys_addr_t addr)
+static inline uint32_t PPC_PCIIO_config(hwaddr addr)
{
int i;
return (addr & 0x7ff) | (i << 11);
}
-static void ppc_pci_io_write(void *opaque, target_phys_addr_t addr,
+static void ppc_pci_io_write(void *opaque, hwaddr addr,
uint64_t val, unsigned int size)
{
PREPPCIState *s = opaque;
pci_data_write(phb->bus, PPC_PCIIO_config(addr), val, size);
}
-static uint64_t ppc_pci_io_read(void *opaque, target_phys_addr_t addr,
+static uint64_t ppc_pci_io_read(void *opaque, hwaddr addr,
unsigned int size)
{
PREPPCIState *s = opaque;
.endianness = DEVICE_LITTLE_ENDIAN,
};
-static uint64_t ppc_intack_read(void *opaque, target_phys_addr_t addr,
+static uint64_t ppc_intack_read(void *opaque, hwaddr addr,
unsigned int size)
{
return pic_read_irq(isa_pic);
uint32_t reg_CFG[PUV3_DMA_CH_NR];
} PUV3DMAState;
-static uint64_t puv3_dma_read(void *opaque, target_phys_addr_t offset,
+static uint64_t puv3_dma_read(void *opaque, hwaddr offset,
unsigned size)
{
PUV3DMAState *s = opaque;
return ret;
}
-static void puv3_dma_write(void *opaque, target_phys_addr_t offset,
+static void puv3_dma_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
PUV3DMAState *s = opaque;
uint32_t reg_GPIR;
} PUV3GPIOState;
-static uint64_t puv3_gpio_read(void *opaque, target_phys_addr_t offset,
+static uint64_t puv3_gpio_read(void *opaque, hwaddr offset,
unsigned size)
{
PUV3GPIOState *s = opaque;
return ret;
}
-static void puv3_gpio_write(void *opaque, target_phys_addr_t offset,
+static void puv3_gpio_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
PUV3GPIOState *s = opaque;
puv3_intc_update(s);
}
-static uint64_t puv3_intc_read(void *opaque, target_phys_addr_t offset,
+static uint64_t puv3_intc_read(void *opaque, hwaddr offset,
unsigned size)
{
PUV3INTCState *s = opaque;
return ret;
}
-static void puv3_intc_write(void *opaque, target_phys_addr_t offset,
+static void puv3_intc_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
PUV3INTCState *s = opaque;
uint32_t reg_OIER;
} PUV3OSTState;
-static uint64_t puv3_ost_read(void *opaque, target_phys_addr_t offset,
+static uint64_t puv3_ost_read(void *opaque, hwaddr offset,
unsigned size)
{
PUV3OSTState *s = opaque;
return ret;
}
-static void puv3_ost_write(void *opaque, target_phys_addr_t offset,
+static void puv3_ost_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
PUV3OSTState *s = opaque;
uint32_t reg_DIVCFG;
} PUV3PMState;
-static uint64_t puv3_pm_read(void *opaque, target_phys_addr_t offset,
+static uint64_t puv3_pm_read(void *opaque, hwaddr offset,
unsigned size)
{
PUV3PMState *s = opaque;
return ret;
}
-static void puv3_pm_write(void *opaque, target_phys_addr_t offset,
+static void puv3_pm_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
PUV3PMState *s = opaque;
# define PXA2XX_INTERNAL_SIZE 0x40000
/* pxa2xx_pic.c */
-DeviceState *pxa2xx_pic_init(target_phys_addr_t base, ARMCPU *cpu);
+DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu);
/* pxa2xx_gpio.c */
-DeviceState *pxa2xx_gpio_init(target_phys_addr_t base,
+DeviceState *pxa2xx_gpio_init(hwaddr base,
CPUARMState *env, DeviceState *pic, int lines);
void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler);
/* pxa2xx_dma.c */
-DeviceState *pxa255_dma_init(target_phys_addr_t base, qemu_irq irq);
-DeviceState *pxa27x_dma_init(target_phys_addr_t base, qemu_irq irq);
+DeviceState *pxa255_dma_init(hwaddr base, qemu_irq irq);
+DeviceState *pxa27x_dma_init(hwaddr base, qemu_irq irq);
/* pxa2xx_lcd.c */
typedef struct PXA2xxLCDState PXA2xxLCDState;
PXA2xxLCDState *pxa2xx_lcdc_init(MemoryRegion *sysmem,
- target_phys_addr_t base, qemu_irq irq);
+ hwaddr base, qemu_irq irq);
void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler);
void pxa2xx_lcdc_oritentation(void *opaque, int angle);
/* pxa2xx_mmci.c */
typedef struct PXA2xxMMCIState PXA2xxMMCIState;
PXA2xxMMCIState *pxa2xx_mmci_init(MemoryRegion *sysmem,
- target_phys_addr_t base,
+ hwaddr base,
BlockDriverState *bd, qemu_irq irq,
qemu_irq rx_dma, qemu_irq tx_dma);
void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
/* pxa2xx_pcmcia.c */
typedef struct PXA2xxPCMCIAState PXA2xxPCMCIAState;
PXA2xxPCMCIAState *pxa2xx_pcmcia_init(MemoryRegion *sysmem,
- target_phys_addr_t base);
+ hwaddr base);
int pxa2xx_pcmcia_attach(void *opaque, PCMCIACardState *card);
int pxa2xx_pcmcia_dettach(void *opaque);
void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq);
};
typedef struct PXA2xxKeyPadState PXA2xxKeyPadState;
PXA2xxKeyPadState *pxa27x_keypad_init(MemoryRegion *sysmem,
- target_phys_addr_t base,
+ hwaddr base,
qemu_irq irq);
void pxa27x_register_keypad(PXA2xxKeyPadState *kp, struct keymap *map,
int size);
/* pxa2xx.c */
typedef struct PXA2xxI2CState PXA2xxI2CState;
-PXA2xxI2CState *pxa2xx_i2c_init(target_phys_addr_t base,
+PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base,
qemu_irq irq, uint32_t page_size);
i2c_bus *pxa2xx_i2c_bus(PXA2xxI2CState *s);
PXA2xxKeyPadState *kp;
/* Power management */
- target_phys_addr_t pm_base;
+ hwaddr pm_base;
uint32_t pm_regs[0x40];
/* Clock management */
- target_phys_addr_t cm_base;
+ hwaddr cm_base;
uint32_t cm_regs[4];
uint32_t clkcfg;
/* Memory management */
- target_phys_addr_t mm_base;
+ hwaddr mm_base;
uint32_t mm_regs[0x1a];
/* Performance monitoring */
#include "blockdev.h"
static struct {
- target_phys_addr_t io_base;
+ hwaddr io_base;
int irqn;
} pxa255_serial[] = {
{ 0x40100000, PXA2XX_PIC_FFUART },
};
typedef struct PXASSPDef {
- target_phys_addr_t io_base;
+ hwaddr io_base;
int irqn;
} PXASSPDef;
#define PCMD0 0x80 /* Power Manager I2C Command register File 0 */
#define PCMD31 0xfc /* Power Manager I2C Command register File 31 */
-static uint64_t pxa2xx_pm_read(void *opaque, target_phys_addr_t addr,
+static uint64_t pxa2xx_pm_read(void *opaque, hwaddr addr,
unsigned size)
{
PXA2xxState *s = (PXA2xxState *) opaque;
return 0;
}
-static void pxa2xx_pm_write(void *opaque, target_phys_addr_t addr,
+static void pxa2xx_pm_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
PXA2xxState *s = (PXA2xxState *) opaque;
#define OSCC 0x08 /* Oscillator Configuration register */
#define CCSR 0x0c /* Core Clock Status register */
-static uint64_t pxa2xx_cm_read(void *opaque, target_phys_addr_t addr,
+static uint64_t pxa2xx_cm_read(void *opaque, hwaddr addr,
unsigned size)
{
PXA2xxState *s = (PXA2xxState *) opaque;
return 0;
}
-static void pxa2xx_cm_write(void *opaque, target_phys_addr_t addr,
+static void pxa2xx_cm_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
PXA2xxState *s = (PXA2xxState *) opaque;
#define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */
#define SA1110 0x64 /* SA-1110 Memory Compatibility register */
-static uint64_t pxa2xx_mm_read(void *opaque, target_phys_addr_t addr,
+static uint64_t pxa2xx_mm_read(void *opaque, hwaddr addr,
unsigned size)
{
PXA2xxState *s = (PXA2xxState *) opaque;
return 0;
}
-static void pxa2xx_mm_write(void *opaque, target_phys_addr_t addr,
+static void pxa2xx_mm_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
PXA2xxState *s = (PXA2xxState *) opaque;
pxa2xx_ssp_int_update(s);
}
-static uint64_t pxa2xx_ssp_read(void *opaque, target_phys_addr_t addr,
+static uint64_t pxa2xx_ssp_read(void *opaque, hwaddr addr,
unsigned size)
{
PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
return 0;
}
-static void pxa2xx_ssp_write(void *opaque, target_phys_addr_t addr,
+static void pxa2xx_ssp_write(void *opaque, hwaddr addr,
uint64_t value64, unsigned size)
{
PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
pxa2xx_rtc_int_update(s);
}
-static uint64_t pxa2xx_rtc_read(void *opaque, target_phys_addr_t addr,
+static uint64_t pxa2xx_rtc_read(void *opaque, hwaddr addr,
unsigned size)
{
PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
return 0;
}
-static void pxa2xx_rtc_write(void *opaque, target_phys_addr_t addr,
+static void pxa2xx_rtc_write(void *opaque, hwaddr addr,
uint64_t value64, unsigned size)
{
PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
return 1;
}
-static uint64_t pxa2xx_i2c_read(void *opaque, target_phys_addr_t addr,
+static uint64_t pxa2xx_i2c_read(void *opaque, hwaddr addr,
unsigned size)
{
PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
return 0;
}
-static void pxa2xx_i2c_write(void *opaque, target_phys_addr_t addr,
+static void pxa2xx_i2c_write(void *opaque, hwaddr addr,
uint64_t value64, unsigned size)
{
PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
.class_init = pxa2xx_i2c_slave_class_init,
};
-PXA2xxI2CState *pxa2xx_i2c_init(target_phys_addr_t base,
+PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base,
qemu_irq irq, uint32_t region_size)
{
DeviceState *dev;
#define SADIV 0x60 /* Serial Audio Clock Divider register */
#define SADR 0x80 /* Serial Audio Data register */
-static uint64_t pxa2xx_i2s_read(void *opaque, target_phys_addr_t addr,
+static uint64_t pxa2xx_i2s_read(void *opaque, hwaddr addr,
unsigned size)
{
PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
return 0;
}
-static void pxa2xx_i2s_write(void *opaque, target_phys_addr_t addr,
+static void pxa2xx_i2s_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
}
static PXA2xxI2SState *pxa2xx_i2s_init(MemoryRegion *sysmem,
- target_phys_addr_t base,
+ hwaddr base,
qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma)
{
PXA2xxI2SState *s = (PXA2xxI2SState *)
#define ICSR1 0x18 /* FICP Status register 1 */
#define ICFOR 0x1c /* FICP FIFO Occupancy Status register */
-static uint64_t pxa2xx_fir_read(void *opaque, target_phys_addr_t addr,
+static uint64_t pxa2xx_fir_read(void *opaque, hwaddr addr,
unsigned size)
{
PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
return 0;
}
-static void pxa2xx_fir_write(void *opaque, target_phys_addr_t addr,
+static void pxa2xx_fir_write(void *opaque, hwaddr addr,
uint64_t value64, unsigned size)
{
PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
}
static PXA2xxFIrState *pxa2xx_fir_init(MemoryRegion *sysmem,
- target_phys_addr_t base,
+ hwaddr base,
qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma,
CharDriverState *chr)
{
PXA2xxDMAState *s, int ch)
{
uint32_t desc[4];
- target_phys_addr_t daddr = s->chan[ch].descr & ~0xf;
+ hwaddr daddr = s->chan[ch].descr & ~0xf;
if ((s->chan[ch].descr & DDADR_BREN) && (s->chan[ch].state & DCSR_CMPST))
daddr += 32;
}
}
-static uint64_t pxa2xx_dma_read(void *opaque, target_phys_addr_t offset,
+static uint64_t pxa2xx_dma_read(void *opaque, hwaddr offset,
unsigned size)
{
PXA2xxDMAState *s = (PXA2xxDMAState *) opaque;
return 7;
}
-static void pxa2xx_dma_write(void *opaque, target_phys_addr_t offset,
+static void pxa2xx_dma_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
PXA2xxDMAState *s = (PXA2xxDMAState *) opaque;
return 0;
}
-DeviceState *pxa27x_dma_init(target_phys_addr_t base, qemu_irq irq)
+DeviceState *pxa27x_dma_init(hwaddr base, qemu_irq irq)
{
DeviceState *dev;
return dev;
}
-DeviceState *pxa255_dma_init(target_phys_addr_t base, qemu_irq irq)
+DeviceState *pxa255_dma_init(hwaddr base, qemu_irq irq)
{
DeviceState *dev;
}
}
-static uint64_t pxa2xx_gpio_read(void *opaque, target_phys_addr_t offset,
+static uint64_t pxa2xx_gpio_read(void *opaque, hwaddr offset,
unsigned size)
{
PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
return 0;
}
-static void pxa2xx_gpio_write(void *opaque, target_phys_addr_t offset,
+static void pxa2xx_gpio_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
.endianness = DEVICE_NATIVE_ENDIAN,
};
-DeviceState *pxa2xx_gpio_init(target_phys_addr_t base,
+DeviceState *pxa2xx_gpio_init(hwaddr base,
CPUARMState *env, DeviceState *pic, int lines)
{
DeviceState *dev;
}
}
-static uint64_t pxa2xx_keypad_read(void *opaque, target_phys_addr_t offset,
+static uint64_t pxa2xx_keypad_read(void *opaque, hwaddr offset,
unsigned size)
{
PXA2xxKeyPadState *s = (PXA2xxKeyPadState *) opaque;
return 0;
}
-static void pxa2xx_keypad_write(void *opaque, target_phys_addr_t offset,
+static void pxa2xx_keypad_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
PXA2xxKeyPadState *s = (PXA2xxKeyPadState *) opaque;
};
PXA2xxKeyPadState *pxa27x_keypad_init(MemoryRegion *sysmem,
- target_phys_addr_t base,
+ hwaddr base,
qemu_irq irq)
{
PXA2xxKeyPadState *s;
uint8_t up;
uint8_t palette[1024];
uint8_t pbuffer[1024];
- void (*redraw)(PXA2xxLCDState *s, target_phys_addr_t addr,
+ void (*redraw)(PXA2xxLCDState *s, hwaddr addr,
int *miny, int *maxy);
uint32_t descriptor;
static void pxa2xx_descriptor_load(PXA2xxLCDState *s)
{
PXAFrameDescriptor desc;
- target_phys_addr_t descptr;
+ hwaddr descptr;
int i;
for (i = 0; i < PXA_LCDDMA_CHANS; i ++) {
}
}
-static uint64_t pxa2xx_lcdc_read(void *opaque, target_phys_addr_t offset,
+static uint64_t pxa2xx_lcdc_read(void *opaque, hwaddr offset,
unsigned size)
{
PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
return 0;
}
-static void pxa2xx_lcdc_write(void *opaque, target_phys_addr_t offset,
+static void pxa2xx_lcdc_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
}
static void pxa2xx_lcdc_dma0_redraw_rot0(PXA2xxLCDState *s,
- target_phys_addr_t addr, int *miny, int *maxy)
+ hwaddr addr, int *miny, int *maxy)
{
int src_width, dest_width;
drawfn fn = NULL;
}
static void pxa2xx_lcdc_dma0_redraw_rot90(PXA2xxLCDState *s,
- target_phys_addr_t addr, int *miny, int *maxy)
+ hwaddr addr, int *miny, int *maxy)
{
int src_width, dest_width;
drawfn fn = NULL;
}
static void pxa2xx_lcdc_dma0_redraw_rot180(PXA2xxLCDState *s,
- target_phys_addr_t addr, int *miny, int *maxy)
+ hwaddr addr, int *miny, int *maxy)
{
int src_width, dest_width;
drawfn fn = NULL;
}
static void pxa2xx_lcdc_dma0_redraw_rot270(PXA2xxLCDState *s,
- target_phys_addr_t addr, int *miny, int *maxy)
+ hwaddr addr, int *miny, int *maxy)
{
int src_width, dest_width;
drawfn fn = NULL;
static void pxa2xx_update_display(void *opaque)
{
PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
- target_phys_addr_t fbptr;
+ hwaddr fbptr;
int miny, maxy;
int ch;
if (!(s->control[0] & LCCR0_ENB))
#include "pxa2xx_template.h"
PXA2xxLCDState *pxa2xx_lcdc_init(MemoryRegion *sysmem,
- target_phys_addr_t base, qemu_irq irq)
+ hwaddr base, qemu_irq irq)
{
PXA2xxLCDState *s;
pxa2xx_mmci_fifo_update(s);
}
-static uint32_t pxa2xx_mmci_read(void *opaque, target_phys_addr_t offset)
+static uint32_t pxa2xx_mmci_read(void *opaque, hwaddr offset)
{
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
uint32_t ret;
}
static void pxa2xx_mmci_write(void *opaque,
- target_phys_addr_t offset, uint32_t value)
+ hwaddr offset, uint32_t value)
{
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
}
}
-static uint32_t pxa2xx_mmci_readb(void *opaque, target_phys_addr_t offset)
+static uint32_t pxa2xx_mmci_readb(void *opaque, hwaddr offset)
{
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
s->ac_width = 1;
return pxa2xx_mmci_read(opaque, offset);
}
-static uint32_t pxa2xx_mmci_readh(void *opaque, target_phys_addr_t offset)
+static uint32_t pxa2xx_mmci_readh(void *opaque, hwaddr offset)
{
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
s->ac_width = 2;
return pxa2xx_mmci_read(opaque, offset);
}
-static uint32_t pxa2xx_mmci_readw(void *opaque, target_phys_addr_t offset)
+static uint32_t pxa2xx_mmci_readw(void *opaque, hwaddr offset)
{
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
s->ac_width = 4;
}
static void pxa2xx_mmci_writeb(void *opaque,
- target_phys_addr_t offset, uint32_t value)
+ hwaddr offset, uint32_t value)
{
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
s->ac_width = 1;
}
static void pxa2xx_mmci_writeh(void *opaque,
- target_phys_addr_t offset, uint32_t value)
+ hwaddr offset, uint32_t value)
{
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
s->ac_width = 2;
}
static void pxa2xx_mmci_writew(void *opaque,
- target_phys_addr_t offset, uint32_t value)
+ hwaddr offset, uint32_t value)
{
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
s->ac_width = 4;
}
PXA2xxMMCIState *pxa2xx_mmci_init(MemoryRegion *sysmem,
- target_phys_addr_t base,
+ hwaddr base,
BlockDriverState *bd, qemu_irq irq,
qemu_irq rx_dma, qemu_irq tx_dma)
{
};
static uint64_t pxa2xx_pcmcia_common_read(void *opaque,
- target_phys_addr_t offset, unsigned size)
+ hwaddr offset, unsigned size)
{
PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
return 0;
}
-static void pxa2xx_pcmcia_common_write(void *opaque, target_phys_addr_t offset,
+static void pxa2xx_pcmcia_common_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
}
static uint64_t pxa2xx_pcmcia_attr_read(void *opaque,
- target_phys_addr_t offset, unsigned size)
+ hwaddr offset, unsigned size)
{
PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
return 0;
}
-static void pxa2xx_pcmcia_attr_write(void *opaque, target_phys_addr_t offset,
+static void pxa2xx_pcmcia_attr_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
}
static uint64_t pxa2xx_pcmcia_io_read(void *opaque,
- target_phys_addr_t offset, unsigned size)
+ hwaddr offset, unsigned size)
{
PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
return 0;
}
-static void pxa2xx_pcmcia_io_write(void *opaque, target_phys_addr_t offset,
+static void pxa2xx_pcmcia_io_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
}
PXA2xxPCMCIAState *pxa2xx_pcmcia_init(MemoryRegion *sysmem,
- target_phys_addr_t base)
+ hwaddr base)
{
PXA2xxPCMCIAState *s;
return ichp;
}
-static uint64_t pxa2xx_pic_mem_read(void *opaque, target_phys_addr_t offset,
+static uint64_t pxa2xx_pic_mem_read(void *opaque, hwaddr offset,
unsigned size)
{
PXA2xxPICState *s = (PXA2xxPICState *) opaque;
}
}
-static void pxa2xx_pic_mem_write(void *opaque, target_phys_addr_t offset,
+static void pxa2xx_pic_mem_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
PXA2xxPICState *s = (PXA2xxPICState *) opaque;
return 0;
}
-DeviceState *pxa2xx_pic_init(target_phys_addr_t base, ARMCPU *cpu)
+DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu)
{
CPUARMState *env = &cpu->env;
DeviceState *dev = qdev_create(NULL, "pxa2xx_pic");
qemu_mod_timer(s->tm4[n].tm.qtimer, new_qemu);
}
-static uint64_t pxa2xx_timer_read(void *opaque, target_phys_addr_t offset,
+static uint64_t pxa2xx_timer_read(void *opaque, hwaddr offset,
unsigned size)
{
PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
return 0;
}
-static void pxa2xx_timer_write(void *opaque, target_phys_addr_t offset,
+static void pxa2xx_timer_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
int i, tm = 0;
#include "qdev.h"
#include "qdev-addr.h"
-#include "targphys.h"
+#include "hwaddr.h"
/* --- target physical address --- */
static int parse_taddr(DeviceState *dev, Property *prop, const char *str)
{
- target_phys_addr_t *ptr = qdev_get_prop_ptr(dev, prop);
+ hwaddr *ptr = qdev_get_prop_ptr(dev, prop);
*ptr = strtoull(str, NULL, 16);
return 0;
static int print_taddr(DeviceState *dev, Property *prop, char *dest, size_t len)
{
- target_phys_addr_t *ptr = qdev_get_prop_ptr(dev, prop);
+ hwaddr *ptr = qdev_get_prop_ptr(dev, prop);
return snprintf(dest, len, "0x" TARGET_FMT_plx, *ptr);
}
{
DeviceState *dev = DEVICE(obj);
Property *prop = opaque;
- target_phys_addr_t *ptr = qdev_get_prop_ptr(dev, prop);
+ hwaddr *ptr = qdev_get_prop_ptr(dev, prop);
int64_t value;
value = *ptr;
{
DeviceState *dev = DEVICE(obj);
Property *prop = opaque;
- target_phys_addr_t *ptr = qdev_get_prop_ptr(dev, prop);
+ hwaddr *ptr = qdev_get_prop_ptr(dev, prop);
Error *local_err = NULL;
int64_t value;
error_propagate(errp, local_err);
return;
}
- if ((uint64_t)value <= (uint64_t) ~(target_phys_addr_t)0) {
+ if ((uint64_t)value <= (uint64_t) ~(hwaddr)0) {
*ptr = value;
} else {
error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE,
dev->id?:"", name, value, (uint64_t) 0,
- (uint64_t) ~(target_phys_addr_t)0);
+ (uint64_t) ~(hwaddr)0);
}
}
.set = set_taddr,
};
-void qdev_prop_set_taddr(DeviceState *dev, const char *name, target_phys_addr_t value)
+void qdev_prop_set_taddr(DeviceState *dev, const char *name, hwaddr value)
{
Error *errp = NULL;
object_property_set_int(OBJECT(dev), value, name, &errp);
#define DEFINE_PROP_TADDR(_n, _s, _f, _d) \
- DEFINE_PROP_DEFAULT(_n, _s, _f, _d, qdev_prop_taddr, target_phys_addr_t)
+ DEFINE_PROP_DEFAULT(_n, _s, _f, _d, qdev_prop_taddr, hwaddr)
extern PropertyInfo qdev_prop_taddr;
-void qdev_prop_set_taddr(DeviceState *dev, const char *name, target_phys_addr_t value);
+void qdev_prop_set_taddr(DeviceState *dev, const char *name, hwaddr value);
qxl_rom_set_dirty(d);
}
-static void ioport_write(void *opaque, target_phys_addr_t addr,
+static void ioport_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
PCIQXLDevice *d = opaque;
}
}
-static uint64_t ioport_read(void *opaque, target_phys_addr_t addr,
+static uint64_t ioport_read(void *opaque, hwaddr addr,
unsigned size)
{
PCIQXLDevice *qxl = opaque;
update_irl(fpga);
}
-static uint32_t r2d_fpga_read(void *opaque, target_phys_addr_t addr)
+static uint32_t r2d_fpga_read(void *opaque, hwaddr addr)
{
r2d_fpga_t *s = opaque;
}
static void
-r2d_fpga_write(void *opaque, target_phys_addr_t addr, uint32_t value)
+r2d_fpga_write(void *opaque, hwaddr addr, uint32_t value)
{
r2d_fpga_t *s = opaque;
};
static qemu_irq *r2d_fpga_init(MemoryRegion *sysmem,
- target_phys_addr_t base, qemu_irq irl)
+ hwaddr base, qemu_irq irl)
{
r2d_fpga_t *s;
}
/* called for accesses to rc4030 */
-static uint32_t rc4030_readl(void *opaque, target_phys_addr_t addr)
+static uint32_t rc4030_readl(void *opaque, hwaddr addr)
{
rc4030State *s = opaque;
uint32_t val;
return val;
}
-static uint32_t rc4030_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t rc4030_readw(void *opaque, hwaddr addr)
{
uint32_t v = rc4030_readl(opaque, addr & ~0x3);
if (addr & 0x2)
return v & 0xffff;
}
-static uint32_t rc4030_readb(void *opaque, target_phys_addr_t addr)
+static uint32_t rc4030_readb(void *opaque, hwaddr addr)
{
uint32_t v = rc4030_readl(opaque, addr & ~0x3);
return (v >> (8 * (addr & 0x3))) & 0xff;
}
-static void rc4030_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void rc4030_writel(void *opaque, hwaddr addr, uint32_t val)
{
rc4030State *s = opaque;
addr &= 0x3fff;
case 0x0060:
/* HACK */
if (s->cache_ltag == 0x80000001 && s->cache_bmask == 0xf0f0f0f) {
- target_phys_addr_t dest = s->cache_ptag & ~0x1;
+ hwaddr dest = s->cache_ptag & ~0x1;
dest += (s->cache_maint & 0x3) << 3;
cpu_physical_memory_write(dest, &val, 4);
}
}
}
-static void rc4030_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void rc4030_writew(void *opaque, hwaddr addr, uint32_t val)
{
uint32_t old_val = rc4030_readl(opaque, addr & ~0x3);
rc4030_writel(opaque, addr & ~0x3, val);
}
-static void rc4030_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void rc4030_writeb(void *opaque, hwaddr addr, uint32_t val)
{
uint32_t old_val = rc4030_readl(opaque, addr & ~0x3);
qemu_irq_raise(s->timer_irq);
}
-static uint32_t jazzio_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t jazzio_readw(void *opaque, hwaddr addr)
{
rc4030State *s = opaque;
uint32_t val;
return val;
}
-static uint32_t jazzio_readb(void *opaque, target_phys_addr_t addr)
+static uint32_t jazzio_readb(void *opaque, hwaddr addr)
{
uint32_t v;
v = jazzio_readw(opaque, addr & ~0x1);
return (v >> (8 * (addr & 0x1))) & 0xff;
}
-static uint32_t jazzio_readl(void *opaque, target_phys_addr_t addr)
+static uint32_t jazzio_readl(void *opaque, hwaddr addr)
{
uint32_t v;
v = jazzio_readw(opaque, addr);
return v;
}
-static void jazzio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void jazzio_writew(void *opaque, hwaddr addr, uint32_t val)
{
rc4030State *s = opaque;
addr &= 0xfff;
}
}
-static void jazzio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void jazzio_writeb(void *opaque, hwaddr addr, uint32_t val)
{
uint32_t old_val = jazzio_readw(opaque, addr & ~0x1);
jazzio_writew(opaque, addr & ~0x1, val);
}
-static void jazzio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void jazzio_writel(void *opaque, hwaddr addr, uint32_t val)
{
jazzio_writew(opaque, addr, val & 0xffff);
jazzio_writew(opaque, addr + 2, (val >> 16) & 0xffff);
qemu_put_be32(f, s->itr);
}
-void rc4030_dma_memory_rw(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write)
+void rc4030_dma_memory_rw(void *opaque, hwaddr addr, uint8_t *buf, int len, int is_write)
{
rc4030State *s = opaque;
- target_phys_addr_t entry_addr;
- target_phys_addr_t phys_addr;
+ hwaddr entry_addr;
+ hwaddr phys_addr;
dma_pagetable_entry entry;
int index;
int ncpy, i;
static void rc4030_do_dma(void *opaque, int n, uint8_t *buf, int len, int is_write)
{
rc4030State *s = opaque;
- target_phys_addr_t dma_addr;
+ hwaddr dma_addr;
int dev_to_mem;
s->dma_regs[n][DMA_REG_ENABLE] &= ~(DMA_FLAG_TC_INTR | DMA_FLAG_MEM_INTR | DMA_FLAG_ADDR_INTR);
sysbus_mmio_map(sysbus_from_qdev(sysctl), 0, 0x10000000);
if (is_mpcore) {
- target_phys_addr_t periphbase;
+ hwaddr periphbase;
dev = qdev_create(NULL, is_pb ? "a9mpcore_priv": "realview_mpcore");
qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
qdev_init_nofail(dev);
if (descriptor == 0 && (val & 0x8))
{
- target_phys_addr_t tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]);
+ hwaddr tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]);
/* dump tally counters to specified memory location */
RTL8139TallyCounters_dma_write(s, tc_addr);
/* */
-static void rtl8139_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void rtl8139_mmio_writeb(void *opaque, hwaddr addr, uint32_t val)
{
rtl8139_io_writeb(opaque, addr & 0xFF, val);
}
-static void rtl8139_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void rtl8139_mmio_writew(void *opaque, hwaddr addr, uint32_t val)
{
rtl8139_io_writew(opaque, addr & 0xFF, val);
}
-static void rtl8139_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void rtl8139_mmio_writel(void *opaque, hwaddr addr, uint32_t val)
{
rtl8139_io_writel(opaque, addr & 0xFF, val);
}
-static uint32_t rtl8139_mmio_readb(void *opaque, target_phys_addr_t addr)
+static uint32_t rtl8139_mmio_readb(void *opaque, hwaddr addr)
{
return rtl8139_io_readb(opaque, addr & 0xFF);
}
-static uint32_t rtl8139_mmio_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t rtl8139_mmio_readw(void *opaque, hwaddr addr)
{
uint32_t val = rtl8139_io_readw(opaque, addr & 0xFF);
return val;
}
-static uint32_t rtl8139_mmio_readl(void *opaque, target_phys_addr_t addr)
+static uint32_t rtl8139_mmio_readl(void *opaque, hwaddr addr)
{
uint32_t val = rtl8139_io_readl(opaque, addr & 0xFF);
return val;
static ram_addr_t s390_virtio_device_num_vq(VirtIOS390Device *dev);
/* length of VirtIO device pages */
-const target_phys_addr_t virtio_size = S390_DEVICE_PAGES * TARGET_PAGE_SIZE;
+const hwaddr virtio_size = S390_DEVICE_PAGES * TARGET_PAGE_SIZE;
static void s390_virtio_bus_reset(void *opaque)
{
void s390_virtio_reset_idx(VirtIOS390Device *dev)
{
int i;
- target_phys_addr_t idx_addr;
+ hwaddr idx_addr;
uint8_t num_vq;
num_vq = s390_virtio_device_num_vq(dev);
int shift = 0;
uint8_t *storage_keys;
void *virtio_region;
- target_phys_addr_t virtio_region_len;
- target_phys_addr_t virtio_region_start;
+ hwaddr virtio_region_len;
+ hwaddr virtio_region_start;
int i;
/* s390x ram size detection needs a 16bit multiplier + an increment. So
{
}
-static uint64_t sbi_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t sbi_mem_read(void *opaque, hwaddr addr,
unsigned size)
{
SBIState *s = opaque;
return ret;
}
-static void sbi_mem_write(void *opaque, target_phys_addr_t addr,
+static void sbi_mem_write(void *opaque, hwaddr addr,
uint64_t val, unsigned dize)
{
SBIState *s = opaque;
}
/* Memory mapped interface */
-static uint64_t serial_mm_read(void *opaque, target_phys_addr_t addr,
+static uint64_t serial_mm_read(void *opaque, hwaddr addr,
unsigned size)
{
SerialState *s = opaque;
return serial_ioport_read(s, addr >> s->it_shift);
}
-static void serial_mm_write(void *opaque, target_phys_addr_t addr,
+static void serial_mm_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
SerialState *s = opaque;
};
SerialState *serial_mm_init(MemoryRegion *address_space,
- target_phys_addr_t base, int it_shift,
+ hwaddr base, int it_shift,
qemu_irq irq, int baudbase,
CharDriverState *chr, enum device_endian end)
{
SerialState *serial_init(int base, qemu_irq irq, int baudbase,
CharDriverState *chr);
SerialState *serial_mm_init(MemoryRegion *address_space,
- target_phys_addr_t base, int it_shift,
+ hwaddr base, int it_shift,
qemu_irq irq, int baudbase,
CharDriverState *chr, enum device_endian end);
#define TMU012_FEAT_TOCR (1 << 0)
#define TMU012_FEAT_3CHAN (1 << 1)
#define TMU012_FEAT_EXTCLK (1 << 2)
-void tmu012_init(struct MemoryRegion *sysmem, target_phys_addr_t base,
+void tmu012_init(struct MemoryRegion *sysmem, hwaddr base,
int feat, uint32_t freq,
qemu_irq ch0_irq, qemu_irq ch1_irq,
qemu_irq ch2_irq0, qemu_irq ch2_irq1);
/* sh_serial.c */
#define SH_SERIAL_FEAT_SCIF (1 << 0)
void sh_serial_init(MemoryRegion *sysmem,
- target_phys_addr_t base, int feat,
+ hwaddr base, int feat,
uint32_t freq, CharDriverState *chr,
qemu_irq eri_source,
qemu_irq rxi_source,
Memory
**********************************************************************/
-static void error_access(const char *kind, target_phys_addr_t addr)
+static void error_access(const char *kind, hwaddr addr)
{
fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") not supported\n",
kind, regname(addr), addr);
}
-static void ignore_access(const char *kind, target_phys_addr_t addr)
+static void ignore_access(const char *kind, hwaddr addr)
{
fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") ignored\n",
kind, regname(addr), addr);
}
-static uint32_t sh7750_mem_readb(void *opaque, target_phys_addr_t addr)
+static uint32_t sh7750_mem_readb(void *opaque, hwaddr addr)
{
switch (addr) {
default:
}
}
-static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t sh7750_mem_readw(void *opaque, hwaddr addr)
{
SH7750State *s = opaque;
}
}
-static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr)
+static uint32_t sh7750_mem_readl(void *opaque, hwaddr addr)
{
SH7750State *s = opaque;
#define is_in_sdrmx(a, x) (a >= SH7750_SDMR ## x ## _A7 \
&& a <= (SH7750_SDMR ## x ## _A7 + SH7750_SDMR ## x ## _REGNB))
-static void sh7750_mem_writeb(void *opaque, target_phys_addr_t addr,
+static void sh7750_mem_writeb(void *opaque, hwaddr addr,
uint32_t mem_value)
{
abort();
}
-static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr,
+static void sh7750_mem_writew(void *opaque, hwaddr addr,
uint32_t mem_value)
{
SH7750State *s = opaque;
}
}
-static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr,
+static void sh7750_mem_writel(void *opaque, hwaddr addr,
uint32_t mem_value)
{
SH7750State *s = opaque;
#define MM_UTLB_DATA (7)
#define MM_REGION_TYPE(addr) ((addr & MM_REGION_MASK) >> 24)
-static uint64_t invalid_read(void *opaque, target_phys_addr_t addr)
+static uint64_t invalid_read(void *opaque, hwaddr addr)
{
abort();
return 0;
}
-static uint64_t sh7750_mmct_read(void *opaque, target_phys_addr_t addr,
+static uint64_t sh7750_mmct_read(void *opaque, hwaddr addr,
unsigned size)
{
SH7750State *s = opaque;
return ret;
}
-static void invalid_write(void *opaque, target_phys_addr_t addr,
+static void invalid_write(void *opaque, hwaddr addr,
uint64_t mem_value)
{
abort();
}
-static void sh7750_mmct_write(void *opaque, target_phys_addr_t addr,
+static void sh7750_mmct_write(void *opaque, hwaddr addr,
uint64_t mem_value, unsigned size)
{
SH7750State *s = opaque;
#endif
}
-static uint64_t sh_intc_read(void *opaque, target_phys_addr_t offset,
+static uint64_t sh_intc_read(void *opaque, hwaddr offset,
unsigned size)
{
struct intc_desc *desc = opaque;
return *valuep;
}
-static void sh_intc_write(void *opaque, target_phys_addr_t offset,
+static void sh_intc_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
struct intc_desc *desc = opaque;
uint32_t iobr;
} SHPCIState;
-static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint64_t val,
+static void sh_pci_reg_write (void *p, hwaddr addr, uint64_t val,
unsigned size)
{
SHPCIState *pcic = p;
}
}
-static uint64_t sh_pci_reg_read (void *p, target_phys_addr_t addr,
+static uint64_t sh_pci_reg_read (void *p, hwaddr addr,
unsigned size)
{
SHPCIState *pcic = p;
s->rx_tail = 0;
}
-static void sh_serial_write(void *opaque, target_phys_addr_t offs,
+static void sh_serial_write(void *opaque, hwaddr offs,
uint64_t val, unsigned size)
{
sh_serial_state *s = opaque;
}
fprintf(stderr, "sh_serial: unsupported write to 0x%02"
- TARGET_PRIxPHYS "\n", offs);
+ HWADDR_PRIx "\n", offs);
abort();
}
-static uint64_t sh_serial_read(void *opaque, target_phys_addr_t offs,
+static uint64_t sh_serial_read(void *opaque, hwaddr offs,
unsigned size)
{
sh_serial_state *s = opaque;
if (ret & ~((1 << 16) - 1)) {
fprintf(stderr, "sh_serial: unsupported read from 0x%02"
- TARGET_PRIxPHYS "\n", offs);
+ HWADDR_PRIx "\n", offs);
abort();
}
};
void sh_serial_init(MemoryRegion *sysmem,
- target_phys_addr_t base, int feat,
+ hwaddr base, int feat,
uint32_t freq, CharDriverState *chr,
qemu_irq eri_source,
qemu_irq rxi_source,
s->int_level = new_level;
}
-static uint32_t sh_timer_read(void *opaque, target_phys_addr_t offset)
+static uint32_t sh_timer_read(void *opaque, hwaddr offset)
{
sh_timer_state *s = (sh_timer_state *)opaque;
}
}
-static void sh_timer_write(void *opaque, target_phys_addr_t offset,
+static void sh_timer_write(void *opaque, hwaddr offset,
uint32_t value)
{
sh_timer_state *s = (sh_timer_state *)opaque;
int feat;
} tmu012_state;
-static uint64_t tmu012_read(void *opaque, target_phys_addr_t offset,
+static uint64_t tmu012_read(void *opaque, hwaddr offset,
unsigned size)
{
tmu012_state *s = (tmu012_state *)opaque;
return 0;
}
-static void tmu012_write(void *opaque, target_phys_addr_t offset,
+static void tmu012_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
tmu012_state *s = (tmu012_state *)opaque;
.endianness = DEVICE_NATIVE_ENDIAN,
};
-void tmu012_init(MemoryRegion *sysmem, target_phys_addr_t base,
+void tmu012_init(MemoryRegion *sysmem, hwaddr base,
int feat, uint32_t freq,
qemu_irq ch0_irq, qemu_irq ch1_irq,
qemu_irq ch2_irq0, qemu_irq ch2_irq1)
/* zaurus.c */
#define SL_PXA_PARAM_BASE 0xa0000a00
-void sl_bootparam_write(target_phys_addr_t ptr);
+void sl_bootparam_write(hwaddr ptr);
#endif
return 0;
}
-static uint64_t shpc_mmio_read(void *opaque, target_phys_addr_t addr,
+static uint64_t shpc_mmio_read(void *opaque, hwaddr addr,
unsigned size)
{
return shpc_read(opaque, addr, size);
}
-static void shpc_mmio_write(void *opaque, target_phys_addr_t addr,
+static void shpc_mmio_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
shpc_write(opaque, addr, val, size);
static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs);
// per-cpu interrupt controller
-static uint64_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr,
+static uint64_t slavio_intctl_mem_readl(void *opaque, hwaddr addr,
unsigned size)
{
SLAVIO_CPUINTCTLState *s = opaque;
return ret;
}
-static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr,
+static void slavio_intctl_mem_writel(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
SLAVIO_CPUINTCTLState *s = opaque;
};
// master system interrupt controller
-static uint64_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr,
+static uint64_t slavio_intctlm_mem_readl(void *opaque, hwaddr addr,
unsigned size)
{
SLAVIO_INTCTLState *s = opaque;
return ret;
}
-static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr,
+static void slavio_intctlm_mem_writel(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
SLAVIO_INTCTLState *s = opaque;
slavio_misc_update_irq(s);
}
-static void slavio_cfg_mem_writeb(void *opaque, target_phys_addr_t addr,
+static void slavio_cfg_mem_writeb(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
MiscState *s = opaque;
slavio_misc_update_irq(s);
}
-static uint64_t slavio_cfg_mem_readb(void *opaque, target_phys_addr_t addr,
+static uint64_t slavio_cfg_mem_readb(void *opaque, hwaddr addr,
unsigned size)
{
MiscState *s = opaque;
},
};
-static void slavio_diag_mem_writeb(void *opaque, target_phys_addr_t addr,
+static void slavio_diag_mem_writeb(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
MiscState *s = opaque;
s->diag = val & 0xff;
}
-static uint64_t slavio_diag_mem_readb(void *opaque, target_phys_addr_t addr,
+static uint64_t slavio_diag_mem_readb(void *opaque, hwaddr addr,
unsigned size)
{
MiscState *s = opaque;
},
};
-static void slavio_mdm_mem_writeb(void *opaque, target_phys_addr_t addr,
+static void slavio_mdm_mem_writeb(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
MiscState *s = opaque;
s->mctrl = val & 0xff;
}
-static uint64_t slavio_mdm_mem_readb(void *opaque, target_phys_addr_t addr,
+static uint64_t slavio_mdm_mem_readb(void *opaque, hwaddr addr,
unsigned size)
{
MiscState *s = opaque;
},
};
-static void slavio_aux1_mem_writeb(void *opaque, target_phys_addr_t addr,
+static void slavio_aux1_mem_writeb(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
MiscState *s = opaque;
s->aux1 = val & 0xff;
}
-static uint64_t slavio_aux1_mem_readb(void *opaque, target_phys_addr_t addr,
+static uint64_t slavio_aux1_mem_readb(void *opaque, hwaddr addr,
unsigned size)
{
MiscState *s = opaque;
},
};
-static void slavio_aux2_mem_writeb(void *opaque, target_phys_addr_t addr,
+static void slavio_aux2_mem_writeb(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
MiscState *s = opaque;
slavio_misc_update_irq(s);
}
-static uint64_t slavio_aux2_mem_readb(void *opaque, target_phys_addr_t addr,
+static uint64_t slavio_aux2_mem_readb(void *opaque, hwaddr addr,
unsigned size)
{
MiscState *s = opaque;
},
};
-static void apc_mem_writeb(void *opaque, target_phys_addr_t addr,
+static void apc_mem_writeb(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
APCState *s = opaque;
qemu_irq_raise(s->cpu_halt);
}
-static uint64_t apc_mem_readb(void *opaque, target_phys_addr_t addr,
+static uint64_t apc_mem_readb(void *opaque, hwaddr addr,
unsigned size)
{
uint32_t ret = 0;
}
};
-static uint64_t slavio_sysctrl_mem_readl(void *opaque, target_phys_addr_t addr,
+static uint64_t slavio_sysctrl_mem_readl(void *opaque, hwaddr addr,
unsigned size)
{
MiscState *s = opaque;
return ret;
}
-static void slavio_sysctrl_mem_writel(void *opaque, target_phys_addr_t addr,
+static void slavio_sysctrl_mem_writel(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
MiscState *s = opaque;
},
};
-static uint64_t slavio_led_mem_readw(void *opaque, target_phys_addr_t addr,
+static uint64_t slavio_led_mem_readw(void *opaque, hwaddr addr,
unsigned size)
{
MiscState *s = opaque;
return ret;
}
-static void slavio_led_mem_writew(void *opaque, target_phys_addr_t addr,
+static void slavio_led_mem_writew(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
MiscState *s = opaque;
}
}
-static uint64_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr,
+static uint64_t slavio_timer_mem_readl(void *opaque, hwaddr addr,
unsigned size)
{
TimerContext *tc = opaque;
return ret;
}
-static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr,
+static void slavio_timer_mem_writel(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
TimerContext *tc = opaque;
DisplayState *ds;
/* status & internal resources */
- target_phys_addr_t base;
+ hwaddr base;
uint32_t local_mem_size_index;
uint8_t * local_mem;
MemoryRegion local_mem_region;
}
}
-static uint64_t sm501_system_config_read(void *opaque, target_phys_addr_t addr,
+static uint64_t sm501_system_config_read(void *opaque, hwaddr addr,
unsigned size)
{
SM501State * s = (SM501State *)opaque;
return ret;
}
-static void sm501_system_config_write(void *opaque, target_phys_addr_t addr,
+static void sm501_system_config_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
SM501State * s = (SM501State *)opaque;
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static uint32_t sm501_palette_read(void *opaque, target_phys_addr_t addr)
+static uint32_t sm501_palette_read(void *opaque, hwaddr addr)
{
SM501State * s = (SM501State *)opaque;
SM501_DPRINTF("sm501 palette read addr=%x\n", (int)addr);
}
static void sm501_palette_write(void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
SM501State * s = (SM501State *)opaque;
SM501_DPRINTF("sm501 palette write addr=%x, val=%x\n",
*(uint32_t*)&s->dc_palette[addr] = value;
}
-static uint64_t sm501_disp_ctrl_read(void *opaque, target_phys_addr_t addr,
+static uint64_t sm501_disp_ctrl_read(void *opaque, hwaddr addr,
unsigned size)
{
SM501State * s = (SM501State *)opaque;
return ret;
}
-static void sm501_disp_ctrl_write(void *opaque, target_phys_addr_t addr,
+static void sm501_disp_ctrl_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
SM501State * s = (SM501State *)opaque;
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static uint64_t sm501_2d_engine_read(void *opaque, target_phys_addr_t addr,
+static uint64_t sm501_2d_engine_read(void *opaque, hwaddr addr,
unsigned size)
{
SM501State * s = (SM501State *)opaque;
return ret;
}
-static void sm501_2d_engine_write(void *opaque, target_phys_addr_t addr,
+static void sm501_2d_engine_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
SM501State * s = (SM501State *)opaque;
#define SET_LOW(name, val) s->name = (s->name & 0xff00) | val
#define SET_HIGH(name, val) s->name = (s->name & 0xff) | (val << 8)
-static void smc91c111_writeb(void *opaque, target_phys_addr_t offset,
+static void smc91c111_writeb(void *opaque, hwaddr offset,
uint32_t value)
{
smc91c111_state *s = (smc91c111_state *)opaque;
hw_error("smc91c111_write: Bad reg %d:%x\n", s->bank, (int)offset);
}
-static uint32_t smc91c111_readb(void *opaque, target_phys_addr_t offset)
+static uint32_t smc91c111_readb(void *opaque, hwaddr offset)
{
smc91c111_state *s = (smc91c111_state *)opaque;
return 0;
}
-static void smc91c111_writew(void *opaque, target_phys_addr_t offset,
+static void smc91c111_writew(void *opaque, hwaddr offset,
uint32_t value)
{
smc91c111_writeb(opaque, offset, value & 0xff);
smc91c111_writeb(opaque, offset + 1, value >> 8);
}
-static void smc91c111_writel(void *opaque, target_phys_addr_t offset,
+static void smc91c111_writel(void *opaque, hwaddr offset,
uint32_t value)
{
/* 32-bit writes to offset 0xc only actually write to the bank select
smc91c111_writew(opaque, offset + 2, value >> 16);
}
-static uint32_t smc91c111_readw(void *opaque, target_phys_addr_t offset)
+static uint32_t smc91c111_readw(void *opaque, hwaddr offset)
{
uint32_t val;
val = smc91c111_readb(opaque, offset);
return val;
}
-static uint32_t smc91c111_readl(void *opaque, target_phys_addr_t offset)
+static uint32_t smc91c111_readl(void *opaque, hwaddr offset)
{
uint32_t val;
val = smc91c111_readw(opaque, offset);
struct memmap_entry_s {
enum soc_dma_port_type type;
- target_phys_addr_t addr;
+ hwaddr addr;
union {
struct {
void *opaque;
}
static inline struct memmap_entry_s *soc_dma_lookup(struct dma_s *dma,
- target_phys_addr_t addr)
+ hwaddr addr)
{
struct memmap_entry_s *lo;
int hi;
return &s->soc;
}
-void soc_dma_port_add_fifo(struct soc_dma_s *soc, target_phys_addr_t virt_base,
+void soc_dma_port_add_fifo(struct soc_dma_s *soc, hwaddr virt_base,
soc_dma_io_t fn, void *opaque, int out)
{
struct memmap_entry_s *entry;
}
void soc_dma_port_add_mem(struct soc_dma_s *soc, uint8_t *phys_base,
- target_phys_addr_t virt_base, size_t size)
+ hwaddr virt_base, size_t size)
{
struct memmap_entry_s *entry;
struct dma_s *dma = (struct dma_s *) soc;
int bytes;
/* Initialised by the DMA module, call soc_dma_ch_update after writing. */
enum soc_dma_access_type type[2];
- target_phys_addr_t vaddr[2]; /* Updated by .transfer_fn(). */
+ hwaddr vaddr[2]; /* Updated by .transfer_fn(). */
/* Private */
void *paddr[2];
soc_dma_io_t io_fn[2];
void soc_dma_reset(struct soc_dma_s *s);
struct soc_dma_s *soc_dma_init(int n);
-void soc_dma_port_add_fifo(struct soc_dma_s *dma, target_phys_addr_t virt_base,
+void soc_dma_port_add_fifo(struct soc_dma_s *dma, hwaddr virt_base,
soc_dma_io_t fn, void *opaque, int out);
void soc_dma_port_add_mem(struct soc_dma_s *dma, uint8_t *phys_base,
- target_phys_addr_t virt_base, size_t size);
+ hwaddr virt_base, size_t size);
static inline void soc_dma_port_add_fifo_in(struct soc_dma_s *dma,
- target_phys_addr_t virt_base, soc_dma_io_t fn, void *opaque)
+ hwaddr virt_base, soc_dma_io_t fn, void *opaque)
{
return soc_dma_port_add_fifo(dma, virt_base, fn, opaque, 0);
}
static inline void soc_dma_port_add_fifo_out(struct soc_dma_s *dma,
- target_phys_addr_t virt_base, soc_dma_io_t fn, void *opaque)
+ hwaddr virt_base, soc_dma_io_t fn, void *opaque)
{
return soc_dma_port_add_fifo(dma, virt_base, fn, opaque, 1);
}
static void *spapr_create_fdt_skel(const char *cpu_model,
- target_phys_addr_t initrd_base,
- target_phys_addr_t initrd_size,
- target_phys_addr_t kernel_size,
+ hwaddr initrd_base,
+ hwaddr initrd_size,
+ hwaddr kernel_size,
const char *boot_device,
const char *kernel_cmdline)
{
cpu_to_be32(0x0), cpu_to_be32(0x0),
cpu_to_be32(0x0)};
char mem_name[32];
- target_phys_addr_t node0_size, mem_start;
+ hwaddr node0_size, mem_start;
uint64_t mem_reg_property[2];
int i, off;
}
static void spapr_finalize_fdt(sPAPREnvironment *spapr,
- target_phys_addr_t fdt_addr,
- target_phys_addr_t rtas_addr,
- target_phys_addr_t rtas_size)
+ hwaddr fdt_addr,
+ hwaddr rtas_addr,
+ hwaddr rtas_size)
{
int ret;
void *fdt;
int i;
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
- target_phys_addr_t rma_alloc_size;
+ hwaddr rma_alloc_size;
uint32_t initrd_base = 0;
long kernel_size = 0, initrd_size = 0;
long load_limit, rtas_limit, fw_size;
QLIST_HEAD(, sPAPRPHBState) phbs;
struct icp_state *icp;
- target_phys_addr_t ram_limit;
+ hwaddr ram_limit;
void *htab;
long htab_shift;
- target_phys_addr_t rma_size;
+ hwaddr rma_size;
int vrma_adjust;
- target_phys_addr_t fdt_addr, rtas_addr;
+ hwaddr fdt_addr, rtas_addr;
long rtas_size;
void *fdt_skel;
target_ulong entry_point;
target_ulong spapr_rtas_call(sPAPREnvironment *spapr,
uint32_t token, uint32_t nargs, target_ulong args,
uint32_t nret, target_ulong rets);
-int spapr_rtas_device_tree_setup(void *fdt, target_phys_addr_t rtas_addr,
- target_phys_addr_t rtas_size);
+int spapr_rtas_device_tree_setup(void *fdt, hwaddr rtas_addr,
+ hwaddr rtas_size);
#define SPAPR_TCE_PAGE_SHIFT 12
#define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT)
static int spapr_tce_translate(DMAContext *dma,
dma_addr_t addr,
- target_phys_addr_t *paddr,
- target_phys_addr_t *len,
+ hwaddr *paddr,
+ hwaddr *len,
DMADirection dir)
{
sPAPRTCETable *tcet = DO_UPCAST(sPAPRTCETable, dma, dma);
if (tcet->bypass) {
*paddr = addr;
- *len = (target_phys_addr_t)-1;
+ *len = (hwaddr)-1;
return 0;
}
* This is required for msi_notify()/msix_notify() which
* will write at the addresses via spapr_msi_write().
*/
-static void spapr_msi_setmsg(PCIDevice *pdev, target_phys_addr_t addr,
+static void spapr_msi_setmsg(PCIDevice *pdev, hwaddr addr,
bool msix, unsigned req_num)
{
unsigned i;
qemu_set_irq(spapr_phb_lsi_qirq(phb, irq_num), level);
}
-static uint64_t spapr_io_read(void *opaque, target_phys_addr_t addr,
+static uint64_t spapr_io_read(void *opaque, hwaddr addr,
unsigned size)
{
switch (size) {
assert(0);
}
-static void spapr_io_write(void *opaque, target_phys_addr_t addr,
+static void spapr_io_write(void *opaque, hwaddr addr,
uint64_t data, unsigned size)
{
switch (size) {
* data is set to 0.
* For MSI, the vector number is encoded in least bits in data.
*/
-static void spapr_msi_write(void *opaque, target_phys_addr_t addr,
+static void spapr_msi_write(void *opaque, hwaddr addr,
uint64_t data, unsigned size)
{
sPAPRPHBState *phb = opaque;
char *dtbusname;
MemoryRegion memspace, iospace;
- target_phys_addr_t mem_win_addr, mem_win_size, io_win_addr, io_win_size;
- target_phys_addr_t msi_win_addr;
+ hwaddr mem_win_addr, mem_win_size, io_win_addr, io_win_size;
+ hwaddr msi_win_addr;
MemoryRegion memwindow, iowindow, msiwindow;
uint32_t dma_liobn;
rtas_next++;
}
-int spapr_rtas_device_tree_setup(void *fdt, target_phys_addr_t rtas_addr,
- target_phys_addr_t rtas_size)
+int spapr_rtas_device_tree_setup(void *fdt, hwaddr rtas_addr,
+ hwaddr rtas_size)
{
int ret;
int i;
};
/* Note: on sparc, the lance 16 bit bus is swapped */
-void ledma_memory_read(void *opaque, target_phys_addr_t addr,
+void ledma_memory_read(void *opaque, hwaddr addr,
uint8_t *buf, int len, int do_bswap)
{
DMAState *s = opaque;
}
}
-void ledma_memory_write(void *opaque, target_phys_addr_t addr,
+void ledma_memory_write(void *opaque, hwaddr addr,
uint8_t *buf, int len, int do_bswap)
{
DMAState *s = opaque;
s->dmaregs[1] += len;
}
-static uint64_t dma_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t dma_mem_read(void *opaque, hwaddr addr,
unsigned size)
{
DMAState *s = opaque;
return s->dmaregs[saddr];
}
-static void dma_mem_write(void *opaque, target_phys_addr_t addr,
+static void dma_mem_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
DMAState *s = opaque;
#define SPARC32_DMA_H
/* sparc32_dma.c */
-void ledma_memory_read(void *opaque, target_phys_addr_t addr,
+void ledma_memory_read(void *opaque, hwaddr addr,
uint8_t *buf, int len, int do_bswap);
-void ledma_memory_write(void *opaque, target_phys_addr_t addr,
+void ledma_memory_write(void *opaque, hwaddr addr,
uint8_t *buf, int len, int do_bswap);
void espdma_memory_read(void *opaque, uint8_t *buf, int len);
void espdma_memory_write(void *opaque, uint8_t *buf, int len);
ECCState ecc;
} SLNANDState;
-static uint64_t sl_read(void *opaque, target_phys_addr_t addr, unsigned size)
+static uint64_t sl_read(void *opaque, hwaddr addr, unsigned size)
{
SLNANDState *s = (SLNANDState *) opaque;
int ryby;
return 0;
}
-static void sl_write(void *opaque, target_phys_addr_t addr,
+static void sl_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
SLNANDState *s = (SLNANDState *) opaque;
gptm_update_irq(s);
}
-static uint64_t gptm_read(void *opaque, target_phys_addr_t offset,
+static uint64_t gptm_read(void *opaque, hwaddr offset,
unsigned size)
{
gptm_state *s = (gptm_state *)opaque;
}
}
-static void gptm_write(void *opaque, target_phys_addr_t offset,
+static void gptm_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
gptm_state *s = (gptm_state *)opaque;
}
}
-static uint64_t ssys_read(void *opaque, target_phys_addr_t offset,
+static uint64_t ssys_read(void *opaque, hwaddr offset,
unsigned size)
{
ssys_state *s = (ssys_state *)opaque;
}
}
-static void ssys_write(void *opaque, target_phys_addr_t offset,
+static void ssys_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
ssys_state *s = (ssys_state *)opaque;
#define STELLARIS_I2C_MCS_IDLE 0x20
#define STELLARIS_I2C_MCS_BUSBSY 0x40
-static uint64_t stellaris_i2c_read(void *opaque, target_phys_addr_t offset,
+static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset,
unsigned size)
{
stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
qemu_set_irq(s->irq, level);
}
-static void stellaris_i2c_write(void *opaque, target_phys_addr_t offset,
+static void stellaris_i2c_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
}
}
-static uint64_t stellaris_adc_read(void *opaque, target_phys_addr_t offset,
+static uint64_t stellaris_adc_read(void *opaque, hwaddr offset,
unsigned size)
{
stellaris_adc_state *s = (stellaris_adc_state *)opaque;
}
}
-static void stellaris_adc_write(void *opaque, target_phys_addr_t offset,
+static void stellaris_adc_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
stellaris_adc_state *s = (stellaris_adc_state *)opaque;
return (s->np < 31);
}
-static uint64_t stellaris_enet_read(void *opaque, target_phys_addr_t offset,
+static uint64_t stellaris_enet_read(void *opaque, hwaddr offset,
unsigned size)
{
stellaris_enet_state *s = (stellaris_enet_state *)opaque;
}
}
-static void stellaris_enet_write(void *opaque, target_phys_addr_t offset,
+static void stellaris_enet_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
stellaris_enet_state *s = (stellaris_enet_state *)opaque;
#endif
static struct {
- target_phys_addr_t io_base;
+ hwaddr io_base;
int irq;
} sa_serial[] = {
{ 0x80010000, SA_PIC_UART1 },
strongarm_pic_update(s);
}
-static uint64_t strongarm_pic_mem_read(void *opaque, target_phys_addr_t offset,
+static uint64_t strongarm_pic_mem_read(void *opaque, hwaddr offset,
unsigned size)
{
StrongARMPICState *s = opaque;
}
}
-static void strongarm_pic_mem_write(void *opaque, target_phys_addr_t offset,
+static void strongarm_pic_mem_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
StrongARMPICState *s = opaque;
strongarm_rtc_int_update(s);
}
-static uint64_t strongarm_rtc_read(void *opaque, target_phys_addr_t addr,
+static uint64_t strongarm_rtc_read(void *opaque, hwaddr addr,
unsigned size)
{
StrongARMRTCState *s = opaque;
}
}
-static void strongarm_rtc_write(void *opaque, target_phys_addr_t addr,
+static void strongarm_rtc_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
StrongARMRTCState *s = opaque;
s->prev_level = level;
}
-static uint64_t strongarm_gpio_read(void *opaque, target_phys_addr_t offset,
+static uint64_t strongarm_gpio_read(void *opaque, hwaddr offset,
unsigned size)
{
StrongARMGPIOInfo *s = opaque;
return 0;
}
-static void strongarm_gpio_write(void *opaque, target_phys_addr_t offset,
+static void strongarm_gpio_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
StrongARMGPIOInfo *s = opaque;
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static DeviceState *strongarm_gpio_init(target_phys_addr_t base,
+static DeviceState *strongarm_gpio_init(hwaddr base,
DeviceState *pic)
{
DeviceState *dev;
s->prev_level = level;
}
-static uint64_t strongarm_ppc_read(void *opaque, target_phys_addr_t offset,
+static uint64_t strongarm_ppc_read(void *opaque, hwaddr offset,
unsigned size)
{
StrongARMPPCInfo *s = opaque;
return 0;
}
-static void strongarm_ppc_write(void *opaque, target_phys_addr_t offset,
+static void strongarm_ppc_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
StrongARMPPCInfo *s = opaque;
strongarm_uart_update_int_status(s);
}
-static uint64_t strongarm_uart_read(void *opaque, target_phys_addr_t addr,
+static uint64_t strongarm_uart_read(void *opaque, hwaddr addr,
unsigned size)
{
StrongARMUARTState *s = opaque;
}
}
-static void strongarm_uart_write(void *opaque, target_phys_addr_t addr,
+static void strongarm_uart_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
StrongARMUARTState *s = opaque;
strongarm_ssp_int_update(s);
}
-static uint64_t strongarm_ssp_read(void *opaque, target_phys_addr_t addr,
+static uint64_t strongarm_ssp_read(void *opaque, hwaddr addr,
unsigned size)
{
StrongARMSSPState *s = opaque;
return 0;
}
-static void strongarm_ssp_write(void *opaque, target_phys_addr_t addr,
+static void strongarm_ssp_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
StrongARMSSPState *s = opaque;
static void sun4c_check_interrupts(void *opaque);
-static uint64_t sun4c_intctl_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t sun4c_intctl_mem_read(void *opaque, hwaddr addr,
unsigned size)
{
Sun4c_INTCTLState *s = opaque;
return ret;
}
-static void sun4c_intctl_mem_write(void *opaque, target_phys_addr_t addr,
+static void sun4c_intctl_mem_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
Sun4c_INTCTLState *s = opaque;
#define ESCC_CLOCK 4915200
struct sun4m_hwdef {
- target_phys_addr_t iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
- target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
- target_phys_addr_t serial_base, fd_base;
- target_phys_addr_t afx_base, idreg_base, dma_base, esp_base, le_base;
- target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
- target_phys_addr_t bpp_base, dbri_base, sx_base;
+ hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
+ hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
+ hwaddr serial_base, fd_base;
+ hwaddr afx_base, idreg_base, dma_base, esp_base, le_base;
+ hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base;
+ hwaddr bpp_base, dbri_base, sx_base;
struct {
- target_phys_addr_t reg_base, vram_base;
+ hwaddr reg_base, vram_base;
} vsimm[MAX_VSIMMS];
- target_phys_addr_t ecc_base;
+ hwaddr ecc_base;
uint64_t max_mem;
const char * const default_cpu_model;
uint32_t ecc_version;
#define MAX_IOUNITS 5
struct sun4d_hwdef {
- target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
- target_phys_addr_t counter_base, nvram_base, ms_kb_base;
- target_phys_addr_t serial_base;
- target_phys_addr_t espdma_base, esp_base;
- target_phys_addr_t ledma_base, le_base;
- target_phys_addr_t tcx_base;
- target_phys_addr_t sbi_base;
+ hwaddr iounit_bases[MAX_IOUNITS], slavio_base;
+ hwaddr counter_base, nvram_base, ms_kb_base;
+ hwaddr serial_base;
+ hwaddr espdma_base, esp_base;
+ hwaddr ledma_base, le_base;
+ hwaddr tcx_base;
+ hwaddr sbi_base;
uint64_t max_mem;
const char * const default_cpu_model;
uint32_t iounit_version;
};
struct sun4c_hwdef {
- target_phys_addr_t iommu_base, slavio_base;
- target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
- target_phys_addr_t serial_base, fd_base;
- target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
- target_phys_addr_t tcx_base, aux1_base;
+ hwaddr iommu_base, slavio_base;
+ hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
+ hwaddr serial_base, fd_base;
+ hwaddr idreg_base, dma_base, esp_base, le_base;
+ hwaddr tcx_base, aux1_base;
uint64_t max_mem;
const char * const default_cpu_model;
uint32_t iommu_version;
return kernel_size;
}
-static void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq)
+static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq)
{
DeviceState *dev;
SysBusDevice *s;
return s;
}
-static void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
+static void *sparc32_dma_init(hwaddr daddr, qemu_irq parent_irq,
void *iommu, qemu_irq *dev_irq, int is_ledma)
{
DeviceState *dev;
return s;
}
-static void lance_init(NICInfo *nd, target_phys_addr_t leaddr,
+static void lance_init(NICInfo *nd, hwaddr leaddr,
void *dma_opaque, qemu_irq irq)
{
DeviceState *dev;
qdev_connect_gpio_out(dma_opaque, 0, reset);
}
-static DeviceState *slavio_intctl_init(target_phys_addr_t addr,
- target_phys_addr_t addrg,
+static DeviceState *slavio_intctl_init(hwaddr addr,
+ hwaddr addrg,
qemu_irq **parent_irq)
{
DeviceState *dev;
#define SYS_TIMER_OFFSET 0x10000ULL
#define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
-static void slavio_timer_init_all(target_phys_addr_t addr, qemu_irq master_irq,
+static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq,
qemu_irq *cpu_irqs, unsigned int num_cpus)
{
DeviceState *dev;
sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
for (i = 0; i < MAX_CPUS; i++) {
- sysbus_mmio_map(s, i + 1, addr + (target_phys_addr_t)CPU_TIMER_OFFSET(i));
+ sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i));
sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
}
}
#define MISC_MDM 0x01b00000
#define MISC_SYS 0x01f00000
-static void slavio_misc_init(target_phys_addr_t base,
- target_phys_addr_t aux1_base,
- target_phys_addr_t aux2_base, qemu_irq irq,
+static void slavio_misc_init(hwaddr base,
+ hwaddr aux1_base,
+ hwaddr aux2_base, qemu_irq irq,
qemu_irq fdc_tc)
{
DeviceState *dev;
qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier);
}
-static void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version)
+static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version)
{
DeviceState *dev;
SysBusDevice *s;
}
}
-static void apc_init(target_phys_addr_t power_base, qemu_irq cpu_halt)
+static void apc_init(hwaddr power_base, qemu_irq cpu_halt)
{
DeviceState *dev;
SysBusDevice *s;
sysbus_connect_irq(s, 0, cpu_halt);
}
-static void tcx_init(target_phys_addr_t addr, int vram_size, int width,
+static void tcx_init(hwaddr addr, int vram_size, int width,
int height, int depth)
{
DeviceState *dev;
/* NCR89C100/MACIO Internal ID register */
static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
-static void idreg_init(target_phys_addr_t addr)
+static void idreg_init(hwaddr addr)
{
DeviceState *dev;
SysBusDevice *s;
} AFXState;
/* SS-5 TCX AFX register */
-static void afx_init(target_phys_addr_t addr)
+static void afx_init(hwaddr addr)
{
DeviceState *dev;
SysBusDevice *s;
/* Boot PROM (OpenBIOS) */
static uint64_t translate_prom_address(void *opaque, uint64_t addr)
{
- target_phys_addr_t *base_addr = (target_phys_addr_t *)opaque;
+ hwaddr *base_addr = (hwaddr *)opaque;
return addr + *base_addr - PROM_VADDR;
}
-static void prom_init(target_phys_addr_t addr, const char *bios_name)
+static void prom_init(hwaddr addr, const char *bios_name)
{
DeviceState *dev;
SysBusDevice *s;
return 0;
}
-static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size,
+static void ram_init(hwaddr addr, ram_addr_t RAM_size,
uint64_t max_mem)
{
DeviceState *dev;
},
};
-static DeviceState *sbi_init(target_phys_addr_t addr, qemu_irq **parent_irq)
+static DeviceState *sbi_init(hwaddr addr, qemu_irq **parent_irq)
{
DeviceState *dev;
SysBusDevice *s;
}
for (i = 0; i < MAX_IOUNITS; i++)
- if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
+ if (hwdef->iounit_bases[i] != (hwaddr)-1)
iounits[i] = iommu_init(hwdef->iounit_bases[i],
hwdef->iounit_version,
sbi_irq[0]);
},
};
-static DeviceState *sun4c_intctl_init(target_phys_addr_t addr,
+static DeviceState *sun4c_intctl_init(hwaddr addr,
qemu_irq *parent_irq)
{
DeviceState *dev;
slavio_irq[1], serial_hds[0], serial_hds[1],
ESCC_CLOCK, 1);
- if (hwdef->fd_base != (target_phys_addr_t)-1) {
+ if (hwdef->fd_base != (hwaddr)-1) {
/* there is zero or one floppy drive */
memset(fd, 0, sizeof(fd));
fd[0] = drive_get(IF_FLOPPY, 0, 0);
/* Devices used by sparc32 system. */
/* iommu.c */
-void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
+void sparc_iommu_memory_rw(void *opaque, hwaddr addr,
uint8_t *buf, int len, int is_write);
static inline void sparc_iommu_memory_read(void *opaque,
- target_phys_addr_t addr,
+ hwaddr addr,
uint8_t *buf, int len)
{
sparc_iommu_memory_rw(opaque, addr, buf, len, 0);
}
static inline void sparc_iommu_memory_write(void *opaque,
- target_phys_addr_t addr,
+ hwaddr addr,
uint8_t *buf, int len)
{
sparc_iommu_memory_rw(opaque, addr, buf, len, 1);
SysBusDevice busdev;
MemoryRegion iomem;
uint32_t regs[IOMMU_NREGS];
- target_phys_addr_t iostart;
+ hwaddr iostart;
qemu_irq irq;
uint32_t version;
} IOMMUState;
-static uint64_t iommu_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t iommu_mem_read(void *opaque, hwaddr addr,
unsigned size)
{
IOMMUState *s = opaque;
- target_phys_addr_t saddr;
+ hwaddr saddr;
uint32_t ret;
saddr = addr >> 2;
return ret;
}
-static void iommu_mem_write(void *opaque, target_phys_addr_t addr,
+static void iommu_mem_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
IOMMUState *s = opaque;
- target_phys_addr_t saddr;
+ hwaddr saddr;
saddr = addr >> 2;
trace_sun4m_iommu_mem_writel(saddr, val);
},
};
-static uint32_t iommu_page_get_flags(IOMMUState *s, target_phys_addr_t addr)
+static uint32_t iommu_page_get_flags(IOMMUState *s, hwaddr addr)
{
uint32_t ret;
- target_phys_addr_t iopte;
- target_phys_addr_t pa = addr;
+ hwaddr iopte;
+ hwaddr pa = addr;
iopte = s->regs[IOMMU_BASE] << 4;
addr &= ~s->iostart;
return ret;
}
-static target_phys_addr_t iommu_translate_pa(target_phys_addr_t addr,
+static hwaddr iommu_translate_pa(hwaddr addr,
uint32_t pte)
{
- target_phys_addr_t pa;
+ hwaddr pa;
pa = ((pte & IOPTE_PAGE) << 4) + (addr & ~IOMMU_PAGE_MASK);
trace_sun4m_iommu_translate_pa(addr, pa, pte);
return pa;
}
-static void iommu_bad_addr(IOMMUState *s, target_phys_addr_t addr,
+static void iommu_bad_addr(IOMMUState *s, hwaddr addr,
int is_write)
{
trace_sun4m_iommu_bad_addr(addr);
qemu_irq_raise(s->irq);
}
-void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
+void sparc_iommu_memory_rw(void *opaque, hwaddr addr,
uint8_t *buf, int len, int is_write)
{
int l;
uint32_t flags;
- target_phys_addr_t page, phys_addr;
+ hwaddr page, phys_addr;
while (len > 0) {
page = addr & IOMMU_PAGE_MASK;
static uint64_t translate_prom_address(void *opaque, uint64_t addr)
{
- target_phys_addr_t *base_addr = (target_phys_addr_t *)opaque;
+ hwaddr *base_addr = (hwaddr *)opaque;
return addr + *base_addr - PROM_VADDR;
}
/* Boot PROM (OpenBIOS) */
-static void prom_init(target_phys_addr_t addr, const char *bios_name)
+static void prom_init(hwaddr addr, const char *bios_name)
{
DeviceState *dev;
SysBusDevice *s;
return 0;
}
-static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size)
+static void ram_init(hwaddr addr, ram_addr_t RAM_size)
{
DeviceState *dev;
SysBusDevice *s;
}
}
-void sysbus_mmio_map(SysBusDevice *dev, int n, target_phys_addr_t addr)
+void sysbus_mmio_map(SysBusDevice *dev, int n, hwaddr addr)
{
assert(n >= 0 && n < dev->num_mmio);
/* ??? region already mapped here. */
return;
}
- if (dev->mmio[n].addr != (target_phys_addr_t)-1) {
+ if (dev->mmio[n].addr != (hwaddr)-1) {
/* Unregister previous mapping. */
memory_region_del_subregion(get_system_memory(), dev->mmio[n].memory);
}
}
DeviceState *sysbus_create_varargs(const char *name,
- target_phys_addr_t addr, ...)
+ hwaddr addr, ...)
{
DeviceState *dev;
SysBusDevice *s;
dev = qdev_create(NULL, name);
s = sysbus_from_qdev(dev);
qdev_init_nofail(dev);
- if (addr != (target_phys_addr_t)-1) {
+ if (addr != (hwaddr)-1) {
sysbus_mmio_map(s, 0, addr);
}
va_start(va, addr);
}
DeviceState *sysbus_try_create_varargs(const char *name,
- target_phys_addr_t addr, ...)
+ hwaddr addr, ...)
{
DeviceState *dev;
SysBusDevice *s;
}
s = sysbus_from_qdev(dev);
qdev_init_nofail(dev);
- if (addr != (target_phys_addr_t)-1) {
+ if (addr != (hwaddr)-1) {
sysbus_mmio_map(s, 0, addr);
}
va_start(va, addr);
static void sysbus_dev_print(Monitor *mon, DeviceState *dev, int indent)
{
SysBusDevice *s = sysbus_from_qdev(dev);
- target_phys_addr_t size;
+ hwaddr size;
int i;
monitor_printf(mon, "%*sirq %d\n", indent, "", s->num_irq);
return g_strdup(path);
}
-void sysbus_add_memory(SysBusDevice *dev, target_phys_addr_t addr,
+void sysbus_add_memory(SysBusDevice *dev, hwaddr addr,
MemoryRegion *mem)
{
memory_region_add_subregion(get_system_memory(), addr, mem);
}
-void sysbus_add_memory_overlap(SysBusDevice *dev, target_phys_addr_t addr,
+void sysbus_add_memory_overlap(SysBusDevice *dev, hwaddr addr,
MemoryRegion *mem, unsigned priority)
{
memory_region_add_subregion_overlap(get_system_memory(), addr, mem,
memory_region_del_subregion(get_system_memory(), mem);
}
-void sysbus_add_io(SysBusDevice *dev, target_phys_addr_t addr,
+void sysbus_add_io(SysBusDevice *dev, hwaddr addr,
MemoryRegion *mem)
{
memory_region_add_subregion(get_system_io(), addr, mem);
qemu_irq *irqp[QDEV_MAX_IRQ];
int num_mmio;
struct {
- target_phys_addr_t addr;
+ hwaddr addr;
MemoryRegion *memory;
} mmio[QDEV_MAX_MMIO];
int num_pio;
void sysbus_connect_irq(SysBusDevice *dev, int n, qemu_irq irq);
-void sysbus_mmio_map(SysBusDevice *dev, int n, target_phys_addr_t addr);
-void sysbus_add_memory(SysBusDevice *dev, target_phys_addr_t addr,
+void sysbus_mmio_map(SysBusDevice *dev, int n, hwaddr addr);
+void sysbus_add_memory(SysBusDevice *dev, hwaddr addr,
MemoryRegion *mem);
-void sysbus_add_memory_overlap(SysBusDevice *dev, target_phys_addr_t addr,
+void sysbus_add_memory_overlap(SysBusDevice *dev, hwaddr addr,
MemoryRegion *mem, unsigned priority);
void sysbus_del_memory(SysBusDevice *dev, MemoryRegion *mem);
-void sysbus_add_io(SysBusDevice *dev, target_phys_addr_t addr,
+void sysbus_add_io(SysBusDevice *dev, hwaddr addr,
MemoryRegion *mem);
void sysbus_del_io(SysBusDevice *dev, MemoryRegion *mem);
MemoryRegion *sysbus_address_space(SysBusDevice *dev);
/* Legacy helper function for creating devices. */
DeviceState *sysbus_create_varargs(const char *name,
- target_phys_addr_t addr, ...);
+ hwaddr addr, ...);
DeviceState *sysbus_try_create_varargs(const char *name,
- target_phys_addr_t addr, ...);
+ hwaddr addr, ...);
static inline DeviceState *sysbus_create_simple(const char *name,
- target_phys_addr_t addr,
+ hwaddr addr,
qemu_irq irq)
{
return sysbus_create_varargs(name, addr, irq, NULL);
}
static inline DeviceState *sysbus_try_create_simple(const char *name,
- target_phys_addr_t addr,
+ hwaddr addr,
qemu_irq irq)
{
return sysbus_try_create_varargs(name, addr, irq, NULL);
case SCR_ ##N(1): return s->scr.N[1]; \
case SCR_ ##N(2): return s->scr.N[2]
-static uint32_t tc6393xb_scr_readb(TC6393xbState *s, target_phys_addr_t addr)
+static uint32_t tc6393xb_scr_readb(TC6393xbState *s, hwaddr addr)
{
switch (addr) {
case SCR_REVID:
case SCR_ ##N(1): s->scr.N[1] = value; return; \
case SCR_ ##N(2): s->scr.N[2] = value; return
-static void tc6393xb_scr_writeb(TC6393xbState *s, target_phys_addr_t addr, uint32_t value)
+static void tc6393xb_scr_writeb(TC6393xbState *s, hwaddr addr, uint32_t value)
{
switch (addr) {
SCR_REG_B(ISR);
(s->nand.imr & 0x80) && (s->nand.imr & s->nand.isr));
}
-static uint32_t tc6393xb_nand_cfg_readb(TC6393xbState *s, target_phys_addr_t addr) {
+static uint32_t tc6393xb_nand_cfg_readb(TC6393xbState *s, hwaddr addr) {
switch (addr) {
case NAND_CFG_COMMAND:
return s->nand_enable ? 2 : 0;
fprintf(stderr, "tc6393xb_nand_cfg: unhandled read at %08x\n", (uint32_t) addr);
return 0;
}
-static void tc6393xb_nand_cfg_writeb(TC6393xbState *s, target_phys_addr_t addr, uint32_t value) {
+static void tc6393xb_nand_cfg_writeb(TC6393xbState *s, hwaddr addr, uint32_t value) {
switch (addr) {
case NAND_CFG_COMMAND:
s->nand_enable = (value & 0x2);
(uint32_t) addr, value & 0xff);
}
-static uint32_t tc6393xb_nand_readb(TC6393xbState *s, target_phys_addr_t addr) {
+static uint32_t tc6393xb_nand_readb(TC6393xbState *s, hwaddr addr) {
switch (addr) {
case NAND_DATA + 0:
case NAND_DATA + 1:
fprintf(stderr, "tc6393xb_nand: unhandled read at %08x\n", (uint32_t) addr);
return 0;
}
-static void tc6393xb_nand_writeb(TC6393xbState *s, target_phys_addr_t addr, uint32_t value) {
+static void tc6393xb_nand_writeb(TC6393xbState *s, hwaddr addr, uint32_t value) {
// fprintf(stderr, "tc6393xb_nand: write at %08x: %02x\n",
// (uint32_t) addr, value & 0xff);
switch (addr) {
}
-static uint64_t tc6393xb_readb(void *opaque, target_phys_addr_t addr,
+static uint64_t tc6393xb_readb(void *opaque, hwaddr addr,
unsigned size)
{
TC6393xbState *s = opaque;
return 0;
}
-static void tc6393xb_writeb(void *opaque, target_phys_addr_t addr,
+static void tc6393xb_writeb(void *opaque, hwaddr addr,
uint64_t value, unsigned size) {
TC6393xbState *s = opaque;
typedef struct TCXState {
SysBusDevice busdev;
- target_phys_addr_t addr;
+ hwaddr addr;
DisplayState *ds;
uint8_t *vram;
uint32_t *vram24, *cplane;
s->dac_state = 0;
}
-static uint64_t tcx_dac_readl(void *opaque, target_phys_addr_t addr,
+static uint64_t tcx_dac_readl(void *opaque, hwaddr addr,
unsigned size)
{
return 0;
}
-static void tcx_dac_writel(void *opaque, target_phys_addr_t addr, uint64_t val,
+static void tcx_dac_writel(void *opaque, hwaddr addr, uint64_t val,
unsigned size)
{
TCXState *s = opaque;
},
};
-static uint64_t dummy_readl(void *opaque, target_phys_addr_t addr,
+static uint64_t dummy_readl(void *opaque, hwaddr addr,
unsigned size)
{
return 0;
}
-static void dummy_writel(void *opaque, target_phys_addr_t addr,
+static void dummy_writel(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
}
extern CPUReadMemoryFunc * const musb_read[];
extern CPUWriteMemoryFunc * const musb_write[];
-static uint32_t tusb_async_readb(void *opaque, target_phys_addr_t addr)
+static uint32_t tusb_async_readb(void *opaque, hwaddr addr)
{
TUSBState *s = (TUSBState *) opaque;
return 0;
}
-static uint32_t tusb_async_readh(void *opaque, target_phys_addr_t addr)
+static uint32_t tusb_async_readh(void *opaque, hwaddr addr)
{
TUSBState *s = (TUSBState *) opaque;
return 0;
}
-static uint32_t tusb_async_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t tusb_async_readw(void *opaque, hwaddr addr)
{
TUSBState *s = (TUSBState *) opaque;
int offset = addr & 0xfff;
return 0;
}
-static void tusb_async_writeb(void *opaque, target_phys_addr_t addr,
+static void tusb_async_writeb(void *opaque, hwaddr addr,
uint32_t value)
{
TUSBState *s = (TUSBState *) opaque;
}
}
-static void tusb_async_writeh(void *opaque, target_phys_addr_t addr,
+static void tusb_async_writeh(void *opaque, hwaddr addr,
uint32_t value)
{
TUSBState *s = (TUSBState *) opaque;
}
}
-static void tusb_async_writew(void *opaque, target_phys_addr_t addr,
+static void tusb_async_writew(void *opaque, hwaddr addr,
uint32_t value)
{
TUSBState *s = (TUSBState *) opaque;
return retval;
}
-static void unin_data_write(void *opaque, target_phys_addr_t addr,
+static void unin_data_write(void *opaque, hwaddr addr,
uint64_t val, unsigned len)
{
UNINState *s = opaque;
val, len);
}
-static uint64_t unin_data_read(void *opaque, target_phys_addr_t addr,
+static uint64_t unin_data_read(void *opaque, hwaddr addr,
unsigned len)
{
UNINState *s = opaque;
return nr2str(ehci_state_names, ARRAY_SIZE(ehci_state_names), state);
}
-static const char *addr2str(target_phys_addr_t addr)
+static const char *addr2str(hwaddr addr)
{
return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names),
addr + OPREGBASE);
return async ? s->a_fetch_addr : s->p_fetch_addr;
}
-static void ehci_trace_qh(EHCIQueue *q, target_phys_addr_t addr, EHCIqh *qh)
+static void ehci_trace_qh(EHCIQueue *q, hwaddr addr, EHCIqh *qh)
{
/* need three here due to argument count limits */
trace_usb_ehci_qh_ptrs(q, addr, qh->next,
(bool)(qh->epchar & QH_EPCHAR_I));
}
-static void ehci_trace_qtd(EHCIQueue *q, target_phys_addr_t addr, EHCIqtd *qtd)
+static void ehci_trace_qtd(EHCIQueue *q, hwaddr addr, EHCIqtd *qtd)
{
/* need three here due to argument count limits */
trace_usb_ehci_qtd_ptrs(q, addr, qtd->next, qtd->altnext);
(bool)(qtd->token & QTD_TOKEN_XACTERR));
}
-static void ehci_trace_itd(EHCIState *s, target_phys_addr_t addr, EHCIitd *itd)
+static void ehci_trace_itd(EHCIState *s, hwaddr addr, EHCIitd *itd)
{
trace_usb_ehci_itd(addr, itd->next,
get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT),
get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR));
}
-static void ehci_trace_sitd(EHCIState *s, target_phys_addr_t addr,
+static void ehci_trace_sitd(EHCIState *s, hwaddr addr,
EHCIsitd *sitd)
{
trace_usb_ehci_sitd(addr, sitd->next,
qemu_bh_cancel(s->async_bh);
}
-static uint64_t ehci_caps_read(void *ptr, target_phys_addr_t addr,
+static uint64_t ehci_caps_read(void *ptr, hwaddr addr,
unsigned size)
{
EHCIState *s = ptr;
return s->caps[addr];
}
-static uint64_t ehci_opreg_read(void *ptr, target_phys_addr_t addr,
+static uint64_t ehci_opreg_read(void *ptr, hwaddr addr,
unsigned size)
{
EHCIState *s = ptr;
return val;
}
-static uint64_t ehci_port_read(void *ptr, target_phys_addr_t addr,
+static uint64_t ehci_port_read(void *ptr, hwaddr addr,
unsigned size)
{
EHCIState *s = ptr;
}
}
-static void ehci_port_write(void *ptr, target_phys_addr_t addr,
+static void ehci_port_write(void *ptr, hwaddr addr,
uint64_t val, unsigned size)
{
EHCIState *s = ptr;
trace_usb_ehci_portsc_change(addr + PORTSC_BEGIN, addr >> 2, *portsc, old);
}
-static void ehci_opreg_write(void *ptr, target_phys_addr_t addr,
+static void ehci_opreg_write(void *ptr, hwaddr addr,
uint64_t val, unsigned size)
{
EHCIState *s = ptr;
}
/* Generic control */
-static uint32_t musb_readb(void *opaque, target_phys_addr_t addr)
+static uint32_t musb_readb(void *opaque, hwaddr addr)
{
MUSBState *s = (MUSBState *) opaque;
int ep, i;
};
}
-static void musb_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
+static void musb_writeb(void *opaque, hwaddr addr, uint32_t value)
{
MUSBState *s = (MUSBState *) opaque;
int ep;
};
}
-static uint32_t musb_readh(void *opaque, target_phys_addr_t addr)
+static uint32_t musb_readh(void *opaque, hwaddr addr)
{
MUSBState *s = (MUSBState *) opaque;
int ep, i;
};
}
-static void musb_writeh(void *opaque, target_phys_addr_t addr, uint32_t value)
+static void musb_writeh(void *opaque, hwaddr addr, uint32_t value)
{
MUSBState *s = (MUSBState *) opaque;
int ep;
};
}
-static uint32_t musb_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t musb_readw(void *opaque, hwaddr addr)
{
MUSBState *s = (MUSBState *) opaque;
int ep;
};
}
-static void musb_writew(void *opaque, target_phys_addr_t addr, uint32_t value)
+static void musb_writew(void *opaque, hwaddr addr, uint32_t value)
{
MUSBState *s = (MUSBState *) opaque;
int ep;
}
static uint64_t ohci_mem_read(void *opaque,
- target_phys_addr_t addr,
+ hwaddr addr,
unsigned size)
{
OHCIState *ohci = opaque;
}
static void ohci_mem_write(void *opaque,
- target_phys_addr_t addr,
+ hwaddr addr,
uint64_t val,
unsigned size)
{
xhci_mfwrap_update(xhci);
}
-static uint64_t xhci_cap_read(void *ptr, target_phys_addr_t reg, unsigned size)
+static uint64_t xhci_cap_read(void *ptr, hwaddr reg, unsigned size)
{
XHCIState *xhci = ptr;
uint32_t ret;
return ret;
}
-static uint64_t xhci_port_read(void *ptr, target_phys_addr_t reg, unsigned size)
+static uint64_t xhci_port_read(void *ptr, hwaddr reg, unsigned size)
{
XHCIPort *port = ptr;
uint32_t ret;
return ret;
}
-static void xhci_port_write(void *ptr, target_phys_addr_t reg,
+static void xhci_port_write(void *ptr, hwaddr reg,
uint64_t val, unsigned size)
{
XHCIPort *port = ptr;
}
}
-static uint64_t xhci_oper_read(void *ptr, target_phys_addr_t reg, unsigned size)
+static uint64_t xhci_oper_read(void *ptr, hwaddr reg, unsigned size)
{
XHCIState *xhci = ptr;
uint32_t ret;
return ret;
}
-static void xhci_oper_write(void *ptr, target_phys_addr_t reg,
+static void xhci_oper_write(void *ptr, hwaddr reg,
uint64_t val, unsigned size)
{
XHCIState *xhci = ptr;
}
}
-static uint64_t xhci_runtime_read(void *ptr, target_phys_addr_t reg,
+static uint64_t xhci_runtime_read(void *ptr, hwaddr reg,
unsigned size)
{
XHCIState *xhci = ptr;
return ret;
}
-static void xhci_runtime_write(void *ptr, target_phys_addr_t reg,
+static void xhci_runtime_write(void *ptr, hwaddr reg,
uint64_t val, unsigned size)
{
XHCIState *xhci = ptr;
}
}
-static uint64_t xhci_doorbell_read(void *ptr, target_phys_addr_t reg,
+static uint64_t xhci_doorbell_read(void *ptr, hwaddr reg,
unsigned size)
{
/* doorbells always read as 0 */
return 0;
}
-static void xhci_doorbell_write(void *ptr, target_phys_addr_t reg,
+static void xhci_doorbell_write(void *ptr, hwaddr reg,
uint64_t val, unsigned size)
{
XHCIState *xhci = ptr;
int in;
} VersatileI2CState;
-static uint64_t versatile_i2c_read(void *opaque, target_phys_addr_t offset,
+static uint64_t versatile_i2c_read(void *opaque, hwaddr offset,
unsigned size)
{
VersatileI2CState *s = (VersatileI2CState *)opaque;
}
}
-static void versatile_i2c_write(void *opaque, target_phys_addr_t offset,
+static void versatile_i2c_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
VersatileI2CState *s = (VersatileI2CState *)opaque;
MemoryRegion isa;
} PCIVPBState;
-static inline uint32_t vpb_pci_config_addr(target_phys_addr_t addr)
+static inline uint32_t vpb_pci_config_addr(hwaddr addr)
{
return addr & 0xffffff;
}
-static void pci_vpb_config_write(void *opaque, target_phys_addr_t addr,
+static void pci_vpb_config_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
pci_data_write(opaque, vpb_pci_config_addr(addr), val, size);
}
-static uint64_t pci_vpb_config_read(void *opaque, target_phys_addr_t addr,
+static uint64_t pci_vpb_config_read(void *opaque, hwaddr addr,
unsigned size)
{
uint32_t val;
vpb_sic_update(s);
}
-static uint64_t vpb_sic_read(void *opaque, target_phys_addr_t offset,
+static uint64_t vpb_sic_read(void *opaque, hwaddr offset,
unsigned size)
{
vpb_sic_state *s = (vpb_sic_state *)opaque;
}
}
-static void vpb_sic_write(void *opaque, target_phys_addr_t offset,
+static void vpb_sic_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
vpb_sic_state *s = (vpb_sic_state *)opaque;
VE_DAPROM,
};
-static target_phys_addr_t motherboard_legacy_map[] = {
+static hwaddr motherboard_legacy_map[] = {
/* CS7: 0x10000000 .. 0x10020000 */
[VE_SYSREGS] = 0x10000000,
[VE_SP810] = 0x10001000,
[VE_USB] = 0x4f000000,
};
-static target_phys_addr_t motherboard_aseries_map[] = {
+static hwaddr motherboard_aseries_map[] = {
/* CS0: 0x08000000 .. 0x0c000000 */
[VE_NORFLASH0] = 0x08000000,
/* CS4: 0x0c000000 .. 0x10000000 */
qemu_irq *pic, uint32_t *proc_id);
struct VEDBoardInfo {
- const target_phys_addr_t *motherboard_map;
- target_phys_addr_t loader_start;
- const target_phys_addr_t gic_cpu_if_addr;
+ const hwaddr *motherboard_map;
+ hwaddr loader_start;
+ const hwaddr gic_cpu_if_addr;
DBoardInitFn *init;
};
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *vram = g_new(MemoryRegion, 1);
MemoryRegion *sram = g_new(MemoryRegion, 1);
- const target_phys_addr_t *map = daughterboard->motherboard_map;
+ const hwaddr *map = daughterboard->motherboard_map;
daughterboard->init(daughterboard, ram_size, cpu_model, pic, &proc_id);
/*
* IO Port/MMIO - Beware of the endians, VFIO is always little endian
*/
-static void vfio_bar_write(void *opaque, target_phys_addr_t addr,
+static void vfio_bar_write(void *opaque, hwaddr addr,
uint64_t data, unsigned size)
{
VFIOBAR *bar = opaque;
}
if (pwrite(bar->fd, &buf, size, bar->fd_offset + addr) != size) {
- error_report("%s(,0x%"TARGET_PRIxPHYS", 0x%"PRIx64", %d) failed: %m\n",
+ error_report("%s(,0x%"HWADDR_PRIx", 0x%"PRIx64", %d) failed: %m\n",
__func__, addr, data, size);
}
- DPRINTF("%s(BAR%d+0x%"TARGET_PRIxPHYS", 0x%"PRIx64", %d)\n",
+ DPRINTF("%s(BAR%d+0x%"HWADDR_PRIx", 0x%"PRIx64", %d)\n",
__func__, bar->nr, addr, data, size);
/*
}
static uint64_t vfio_bar_read(void *opaque,
- target_phys_addr_t addr, unsigned size)
+ hwaddr addr, unsigned size)
{
VFIOBAR *bar = opaque;
union {
uint64_t data = 0;
if (pread(bar->fd, &buf, size, bar->fd_offset + addr) != size) {
- error_report("%s(,0x%"TARGET_PRIxPHYS", %d) failed: %m\n",
+ error_report("%s(,0x%"HWADDR_PRIx", %d) failed: %m\n",
__func__, addr, size);
return (uint64_t)-1;
}
break;
}
- DPRINTF("%s(BAR%d+0x%"TARGET_PRIxPHYS", %d) = 0x%"PRIx64"\n",
+ DPRINTF("%s(BAR%d+0x%"HWADDR_PRIx", %d) = 0x%"PRIx64"\n",
__func__, bar->nr, addr, size, data);
/* Same as write above */
* DMA - Mapping and unmapping for the "type1" IOMMU interface used on x86
*/
static int vfio_dma_unmap(VFIOContainer *container,
- target_phys_addr_t iova, ram_addr_t size)
+ hwaddr iova, ram_addr_t size)
{
struct vfio_iommu_type1_dma_unmap unmap = {
.argsz = sizeof(unmap),
return 0;
}
-static int vfio_dma_map(VFIOContainer *container, target_phys_addr_t iova,
+static int vfio_dma_map(VFIOContainer *container, hwaddr iova,
ram_addr_t size, void *vaddr, bool readonly)
{
struct vfio_iommu_type1_dma_map map = {
{
VFIOContainer *container = container_of(listener, VFIOContainer,
iommu_data.listener);
- target_phys_addr_t iova, end;
+ hwaddr iova, end;
void *vaddr;
int ret;
if (vfio_listener_skipped_section(section)) {
- DPRINTF("vfio: SKIPPING region_add %"TARGET_PRIxPHYS" - %"PRIx64"\n",
+ DPRINTF("vfio: SKIPPING region_add %"HWADDR_PRIx" - %"PRIx64"\n",
section->offset_within_address_space,
section->offset_within_address_space + section->size - 1);
return;
section->offset_within_region +
(iova - section->offset_within_address_space);
- DPRINTF("vfio: region_add %"TARGET_PRIxPHYS" - %"TARGET_PRIxPHYS" [%p]\n",
+ DPRINTF("vfio: region_add %"HWADDR_PRIx" - %"HWADDR_PRIx" [%p]\n",
iova, end - 1, vaddr);
ret = vfio_dma_map(container, iova, end - iova, vaddr, section->readonly);
if (ret) {
- error_report("vfio_dma_map(%p, 0x%"TARGET_PRIxPHYS", "
- "0x%"TARGET_PRIxPHYS", %p) = %d (%m)\n",
+ error_report("vfio_dma_map(%p, 0x%"HWADDR_PRIx", "
+ "0x%"HWADDR_PRIx", %p) = %d (%m)\n",
container, iova, end - iova, vaddr, ret);
}
}
{
VFIOContainer *container = container_of(listener, VFIOContainer,
iommu_data.listener);
- target_phys_addr_t iova, end;
+ hwaddr iova, end;
int ret;
if (vfio_listener_skipped_section(section)) {
- DPRINTF("vfio: SKIPPING region_del %"TARGET_PRIxPHYS" - %"PRIx64"\n",
+ DPRINTF("vfio: SKIPPING region_del %"HWADDR_PRIx" - %"PRIx64"\n",
section->offset_within_address_space,
section->offset_within_address_space + section->size - 1);
return;
return;
}
- DPRINTF("vfio: region_del %"TARGET_PRIxPHYS" - %"TARGET_PRIxPHYS"\n",
+ DPRINTF("vfio: region_del %"HWADDR_PRIx" - %"HWADDR_PRIx"\n",
iova, end - 1);
ret = vfio_dma_unmap(container, iova, end - iova);
if (ret) {
- error_report("vfio_dma_unmap(%p, 0x%"TARGET_PRIxPHYS", "
- "0x%"TARGET_PRIxPHYS") = %d (%m)\n",
+ error_report("vfio_dma_unmap(%p, 0x%"HWADDR_PRIx", "
+ "0x%"HWADDR_PRIx") = %d (%m)\n",
container, iova, end - iova, ret);
}
}
} ISAVGAMMState;
/* Memory mapped interface */
-static uint32_t vga_mm_readb (void *opaque, target_phys_addr_t addr)
+static uint32_t vga_mm_readb (void *opaque, hwaddr addr)
{
ISAVGAMMState *s = opaque;
}
static void vga_mm_writeb (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
ISAVGAMMState *s = opaque;
vga_ioport_write(&s->vga, addr >> s->it_shift, value & 0xff);
}
-static uint32_t vga_mm_readw (void *opaque, target_phys_addr_t addr)
+static uint32_t vga_mm_readw (void *opaque, hwaddr addr)
{
ISAVGAMMState *s = opaque;
}
static void vga_mm_writew (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
ISAVGAMMState *s = opaque;
vga_ioport_write(&s->vga, addr >> s->it_shift, value & 0xffff);
}
-static uint32_t vga_mm_readl (void *opaque, target_phys_addr_t addr)
+static uint32_t vga_mm_readl (void *opaque, hwaddr addr)
{
ISAVGAMMState *s = opaque;
}
static void vga_mm_writel (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
ISAVGAMMState *s = opaque;
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static void vga_mm_init(ISAVGAMMState *s, target_phys_addr_t vram_base,
- target_phys_addr_t ctrl_base, int it_shift,
+static void vga_mm_init(ISAVGAMMState *s, hwaddr vram_base,
+ hwaddr ctrl_base, int it_shift,
MemoryRegion *address_space)
{
MemoryRegion *s_ioport_ctrl, *vga_io_memory;
memory_region_set_coalescing(vga_io_memory);
}
-int isa_vga_mm_init(target_phys_addr_t vram_base,
- target_phys_addr_t ctrl_base, int it_shift,
+int isa_vga_mm_init(hwaddr vram_base,
+ hwaddr ctrl_base, int it_shift,
MemoryRegion *address_space)
{
ISAVGAMMState *s;
}
};
-static uint64_t pci_vga_ioport_read(void *ptr, target_phys_addr_t addr,
+static uint64_t pci_vga_ioport_read(void *ptr, hwaddr addr,
unsigned size)
{
PCIVGAState *d = ptr;
return ret;
}
-static void pci_vga_ioport_write(void *ptr, target_phys_addr_t addr,
+static void pci_vga_ioport_write(void *ptr, hwaddr addr,
uint64_t val, unsigned size)
{
PCIVGAState *d = ptr;
.endianness = DEVICE_LITTLE_ENDIAN,
};
-static uint64_t pci_vga_bochs_read(void *ptr, target_phys_addr_t addr,
+static uint64_t pci_vga_bochs_read(void *ptr, hwaddr addr,
unsigned size)
{
PCIVGAState *d = ptr;
return vbe_ioport_read_data(&d->vga, 0);
}
-static void pci_vga_bochs_write(void *ptr, target_phys_addr_t addr,
+static void pci_vga_bochs_write(void *ptr, hwaddr addr,
uint64_t val, unsigned size)
{
PCIVGAState *d = ptr;
static void vga_update_memory_access(VGACommonState *s)
{
MemoryRegion *region, *old_region = s->chain4_alias;
- target_phys_addr_t base, offset, size;
+ hwaddr base, offset, size;
s->chain4_alias = NULL;
}
/* called for accesses between 0xa0000 and 0xc0000 */
-uint32_t vga_mem_readb(VGACommonState *s, target_phys_addr_t addr)
+uint32_t vga_mem_readb(VGACommonState *s, hwaddr addr)
{
int memory_map_mode, plane;
uint32_t ret;
}
/* called for accesses between 0xa0000 and 0xc0000 */
-void vga_mem_writeb(VGACommonState *s, target_phys_addr_t addr, uint32_t val)
+void vga_mem_writeb(VGACommonState *s, hwaddr addr, uint32_t val)
{
int memory_map_mode, plane, write_mode, b, func_select, mask;
uint32_t write_mask, bit_mask, set_mask;
dpy_update(s->ds, 0, 0, s->last_width, height);
}
-static uint64_t vga_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t vga_mem_read(void *opaque, hwaddr addr,
unsigned size)
{
VGACommonState *s = opaque;
return vga_mem_readb(s, addr);
}
-static void vga_mem_write(void *opaque, target_phys_addr_t addr,
+static void vga_mem_write(void *opaque, hwaddr addr,
uint64_t data, unsigned size)
{
VGACommonState *s = opaque;
extern const VMStateDescription vmstate_vga_common;
uint32_t vga_ioport_read(void *opaque, uint32_t addr);
void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val);
-uint32_t vga_mem_readb(VGACommonState *s, target_phys_addr_t addr);
-void vga_mem_writeb(VGACommonState *s, target_phys_addr_t addr, uint32_t val);
+uint32_t vga_mem_readb(VGACommonState *s, hwaddr addr);
+void vga_mem_writeb(VGACommonState *s, hwaddr addr, uint32_t val);
void vga_invalidate_scanlines(VGACommonState *s, int y1, int y2);
void ppm_save(const char *filename, struct DisplaySurface *ds, Error **errp);
static int vhost_sync_dirty_bitmap(struct vhost_dev *dev,
MemoryRegionSection *section,
- target_phys_addr_t start_addr,
- target_phys_addr_t end_addr)
+ hwaddr start_addr,
+ hwaddr end_addr)
{
int i;
{
struct vhost_dev *dev = container_of(listener, struct vhost_dev,
memory_listener);
- target_phys_addr_t start_addr = section->offset_within_address_space;
- target_phys_addr_t end_addr = start_addr + section->size;
+ hwaddr start_addr = section->offset_within_address_space;
+ hwaddr end_addr = start_addr + section->size;
vhost_sync_dirty_bitmap(dev, section, start_addr, end_addr);
}
int i;
for (i = 0; i < dev->nvqs; ++i) {
struct vhost_virtqueue *vq = dev->vqs + i;
- target_phys_addr_t l;
+ hwaddr l;
void *p;
if (!ranges_overlap(start_addr, size, vq->ring_phys, vq->ring_size)) {
{
struct vhost_dev *dev = container_of(listener, struct vhost_dev,
memory_listener);
- target_phys_addr_t start_addr = section->offset_within_address_space;
+ hwaddr start_addr = section->offset_within_address_space;
ram_addr_t size = section->size;
bool log_dirty = memory_region_is_logging(section->mr);
int s = offsetof(struct vhost_memory, regions) +
struct vhost_virtqueue *vq,
unsigned idx)
{
- target_phys_addr_t s, l, a;
+ hwaddr s, l, a;
int r;
struct vhost_vring_file file = {
.index = idx,
}
for (i = 0; i < hdev->n_mem_sections; ++i) {
vhost_sync_dirty_bitmap(hdev, &hdev->mem_sections[i],
- 0, (target_phys_addr_t)~0x0ull);
+ 0, (hwaddr)~0x0ull);
}
r = vdev->binding->set_guest_notifiers(vdev->binding_opaque, false);
if (r < 0) {
/* Create reset TLB entries for BookE, spanning the 32bit addr space. */
static void mmubooke_create_initial_mapping(CPUPPCState *env,
target_ulong va,
- target_phys_addr_t pa)
+ hwaddr pa)
{
ppcemb_tlb_t *tlb = &env->tlb.tlbe[0];
}
#define BINARY_DEVICE_TREE_FILE "virtex-ml507.dtb"
-static int xilinx_load_device_tree(target_phys_addr_t addr,
+static int xilinx_load_device_tree(hwaddr addr,
uint32_t ramsize,
- target_phys_addr_t initrd_base,
- target_phys_addr_t initrd_size,
+ hwaddr initrd_base,
+ hwaddr initrd_size,
const char *kernel_cmdline)
{
char *path;
DeviceState *dev;
PowerPCCPU *cpu;
CPUPPCState *env;
- target_phys_addr_t ram_base = 0;
+ hwaddr ram_base = 0;
DriveInfo *dinfo;
MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
qemu_irq irq[32], *cpu_irq;
if (kernel_filename) {
uint64_t entry, low, high;
- target_phys_addr_t boot_offset;
+ hwaddr boot_offset;
/* Boots a kernel elf binary. */
kernel_size = load_elf(kernel_filename, NULL, NULL,
{
VirtIOPCIProxy *proxy = opaque;
VirtIODevice *vdev = proxy->vdev;
- target_phys_addr_t pa;
+ hwaddr pa;
switch (addr) {
case VIRTIO_PCI_GUEST_FEATURES:
virtio_set_features(vdev, val);
break;
case VIRTIO_PCI_QUEUE_PFN:
- pa = (target_phys_addr_t)val << VIRTIO_PCI_QUEUE_ADDR_SHIFT;
+ pa = (hwaddr)val << VIRTIO_PCI_QUEUE_ADDR_SHIFT;
if (pa == 0) {
virtio_pci_stop_ioeventfd(proxy);
virtio_reset(proxy->vdev);
}
static void qemu_sgl_init_external(QEMUSGList *qsgl, struct iovec *sg,
- target_phys_addr_t *addr, int num)
+ hwaddr *addr, int num)
{
memset(qsgl, 0, sizeof(*qsgl));
while (num--) {
typedef struct VRing
{
unsigned int num;
- target_phys_addr_t desc;
- target_phys_addr_t avail;
- target_phys_addr_t used;
+ hwaddr desc;
+ hwaddr avail;
+ hwaddr used;
} VRing;
struct VirtQueue
{
VRing vring;
- target_phys_addr_t pa;
+ hwaddr pa;
uint16_t last_avail_idx;
/* Last used index value we have signalled on */
uint16_t signalled_used;
/* virt queue functions */
static void virtqueue_init(VirtQueue *vq)
{
- target_phys_addr_t pa = vq->pa;
+ hwaddr pa = vq->pa;
vq->vring.desc = pa;
vq->vring.avail = pa + vq->vring.num * sizeof(VRingDesc);
VIRTIO_PCI_VRING_ALIGN);
}
-static inline uint64_t vring_desc_addr(target_phys_addr_t desc_pa, int i)
+static inline uint64_t vring_desc_addr(hwaddr desc_pa, int i)
{
- target_phys_addr_t pa;
+ hwaddr pa;
pa = desc_pa + sizeof(VRingDesc) * i + offsetof(VRingDesc, addr);
return ldq_phys(pa);
}
-static inline uint32_t vring_desc_len(target_phys_addr_t desc_pa, int i)
+static inline uint32_t vring_desc_len(hwaddr desc_pa, int i)
{
- target_phys_addr_t pa;
+ hwaddr pa;
pa = desc_pa + sizeof(VRingDesc) * i + offsetof(VRingDesc, len);
return ldl_phys(pa);
}
-static inline uint16_t vring_desc_flags(target_phys_addr_t desc_pa, int i)
+static inline uint16_t vring_desc_flags(hwaddr desc_pa, int i)
{
- target_phys_addr_t pa;
+ hwaddr pa;
pa = desc_pa + sizeof(VRingDesc) * i + offsetof(VRingDesc, flags);
return lduw_phys(pa);
}
-static inline uint16_t vring_desc_next(target_phys_addr_t desc_pa, int i)
+static inline uint16_t vring_desc_next(hwaddr desc_pa, int i)
{
- target_phys_addr_t pa;
+ hwaddr pa;
pa = desc_pa + sizeof(VRingDesc) * i + offsetof(VRingDesc, next);
return lduw_phys(pa);
}
static inline uint16_t vring_avail_flags(VirtQueue *vq)
{
- target_phys_addr_t pa;
+ hwaddr pa;
pa = vq->vring.avail + offsetof(VRingAvail, flags);
return lduw_phys(pa);
}
static inline uint16_t vring_avail_idx(VirtQueue *vq)
{
- target_phys_addr_t pa;
+ hwaddr pa;
pa = vq->vring.avail + offsetof(VRingAvail, idx);
return lduw_phys(pa);
}
static inline uint16_t vring_avail_ring(VirtQueue *vq, int i)
{
- target_phys_addr_t pa;
+ hwaddr pa;
pa = vq->vring.avail + offsetof(VRingAvail, ring[i]);
return lduw_phys(pa);
}
static inline void vring_used_ring_id(VirtQueue *vq, int i, uint32_t val)
{
- target_phys_addr_t pa;
+ hwaddr pa;
pa = vq->vring.used + offsetof(VRingUsed, ring[i].id);
stl_phys(pa, val);
}
static inline void vring_used_ring_len(VirtQueue *vq, int i, uint32_t val)
{
- target_phys_addr_t pa;
+ hwaddr pa;
pa = vq->vring.used + offsetof(VRingUsed, ring[i].len);
stl_phys(pa, val);
}
static uint16_t vring_used_idx(VirtQueue *vq)
{
- target_phys_addr_t pa;
+ hwaddr pa;
pa = vq->vring.used + offsetof(VRingUsed, idx);
return lduw_phys(pa);
}
static inline void vring_used_idx_set(VirtQueue *vq, uint16_t val)
{
- target_phys_addr_t pa;
+ hwaddr pa;
pa = vq->vring.used + offsetof(VRingUsed, idx);
stw_phys(pa, val);
}
static inline void vring_used_flags_set_bit(VirtQueue *vq, int mask)
{
- target_phys_addr_t pa;
+ hwaddr pa;
pa = vq->vring.used + offsetof(VRingUsed, flags);
stw_phys(pa, lduw_phys(pa) | mask);
}
static inline void vring_used_flags_unset_bit(VirtQueue *vq, int mask)
{
- target_phys_addr_t pa;
+ hwaddr pa;
pa = vq->vring.used + offsetof(VRingUsed, flags);
stw_phys(pa, lduw_phys(pa) & ~mask);
}
static inline void vring_avail_event(VirtQueue *vq, uint16_t val)
{
- target_phys_addr_t pa;
+ hwaddr pa;
if (!vq->notification) {
return;
}
return head;
}
-static unsigned virtqueue_next_desc(target_phys_addr_t desc_pa,
+static unsigned virtqueue_next_desc(hwaddr desc_pa,
unsigned int i, unsigned int max)
{
unsigned int next;
total_bufs = in_total = out_total = 0;
while (virtqueue_num_heads(vq, idx)) {
unsigned int max, num_bufs, indirect = 0;
- target_phys_addr_t desc_pa;
+ hwaddr desc_pa;
int i;
max = vq->vring.num;
return 0;
}
-void virtqueue_map_sg(struct iovec *sg, target_phys_addr_t *addr,
+void virtqueue_map_sg(struct iovec *sg, hwaddr *addr,
size_t num_sg, int is_write)
{
unsigned int i;
- target_phys_addr_t len;
+ hwaddr len;
for (i = 0; i < num_sg; i++) {
len = sg[i].iov_len;
int virtqueue_pop(VirtQueue *vq, VirtQueueElement *elem)
{
unsigned int i, head, max;
- target_phys_addr_t desc_pa = vq->vring.desc;
+ hwaddr desc_pa = vq->vring.desc;
if (!virtqueue_num_heads(vq, vq->last_avail_idx))
return 0;
vdev->set_config(vdev, vdev->config);
}
-void virtio_queue_set_addr(VirtIODevice *vdev, int n, target_phys_addr_t addr)
+void virtio_queue_set_addr(VirtIODevice *vdev, int n, hwaddr addr)
{
vdev->vq[n].pa = addr;
virtqueue_init(&vdev->vq[n]);
}
-target_phys_addr_t virtio_queue_get_addr(VirtIODevice *vdev, int n)
+hwaddr virtio_queue_get_addr(VirtIODevice *vdev, int n)
{
return vdev->vq[n].pa;
}
vdev->binding_opaque = opaque;
}
-target_phys_addr_t virtio_queue_get_desc_addr(VirtIODevice *vdev, int n)
+hwaddr virtio_queue_get_desc_addr(VirtIODevice *vdev, int n)
{
return vdev->vq[n].vring.desc;
}
-target_phys_addr_t virtio_queue_get_avail_addr(VirtIODevice *vdev, int n)
+hwaddr virtio_queue_get_avail_addr(VirtIODevice *vdev, int n)
{
return vdev->vq[n].vring.avail;
}
-target_phys_addr_t virtio_queue_get_used_addr(VirtIODevice *vdev, int n)
+hwaddr virtio_queue_get_used_addr(VirtIODevice *vdev, int n)
{
return vdev->vq[n].vring.used;
}
-target_phys_addr_t virtio_queue_get_ring_addr(VirtIODevice *vdev, int n)
+hwaddr virtio_queue_get_ring_addr(VirtIODevice *vdev, int n)
{
return vdev->vq[n].vring.desc;
}
-target_phys_addr_t virtio_queue_get_desc_size(VirtIODevice *vdev, int n)
+hwaddr virtio_queue_get_desc_size(VirtIODevice *vdev, int n)
{
return sizeof(VRingDesc) * vdev->vq[n].vring.num;
}
-target_phys_addr_t virtio_queue_get_avail_size(VirtIODevice *vdev, int n)
+hwaddr virtio_queue_get_avail_size(VirtIODevice *vdev, int n)
{
return offsetof(VRingAvail, ring) +
sizeof(uint64_t) * vdev->vq[n].vring.num;
}
-target_phys_addr_t virtio_queue_get_used_size(VirtIODevice *vdev, int n)
+hwaddr virtio_queue_get_used_size(VirtIODevice *vdev, int n)
{
return offsetof(VRingUsed, ring) +
sizeof(VRingUsedElem) * vdev->vq[n].vring.num;
}
-target_phys_addr_t virtio_queue_get_ring_size(VirtIODevice *vdev, int n)
+hwaddr virtio_queue_get_ring_size(VirtIODevice *vdev, int n)
{
return vdev->vq[n].vring.used - vdev->vq[n].vring.desc +
virtio_queue_get_used_size(vdev, n);
struct VirtQueue;
-static inline target_phys_addr_t vring_align(target_phys_addr_t addr,
+static inline hwaddr vring_align(hwaddr addr,
unsigned long align)
{
return (addr + align - 1) & ~(align - 1);
unsigned int index;
unsigned int out_num;
unsigned int in_num;
- target_phys_addr_t in_addr[VIRTQUEUE_MAX_SIZE];
- target_phys_addr_t out_addr[VIRTQUEUE_MAX_SIZE];
+ hwaddr in_addr[VIRTQUEUE_MAX_SIZE];
+ hwaddr out_addr[VIRTQUEUE_MAX_SIZE];
struct iovec in_sg[VIRTQUEUE_MAX_SIZE];
struct iovec out_sg[VIRTQUEUE_MAX_SIZE];
} VirtQueueElement;
void virtqueue_fill(VirtQueue *vq, const VirtQueueElement *elem,
unsigned int len, unsigned int idx);
-void virtqueue_map_sg(struct iovec *sg, target_phys_addr_t *addr,
+void virtqueue_map_sg(struct iovec *sg, hwaddr *addr,
size_t num_sg, int is_write);
int virtqueue_pop(VirtQueue *vq, VirtQueueElement *elem);
int virtqueue_avail_bytes(VirtQueue *vq, unsigned int in_bytes,
void virtio_config_writeb(VirtIODevice *vdev, uint32_t addr, uint32_t data);
void virtio_config_writew(VirtIODevice *vdev, uint32_t addr, uint32_t data);
void virtio_config_writel(VirtIODevice *vdev, uint32_t addr, uint32_t data);
-void virtio_queue_set_addr(VirtIODevice *vdev, int n, target_phys_addr_t addr);
-target_phys_addr_t virtio_queue_get_addr(VirtIODevice *vdev, int n);
+void virtio_queue_set_addr(VirtIODevice *vdev, int n, hwaddr addr);
+hwaddr virtio_queue_get_addr(VirtIODevice *vdev, int n);
int virtio_queue_get_num(VirtIODevice *vdev, int n);
void virtio_queue_notify(VirtIODevice *vdev, int n);
uint16_t virtio_queue_vector(VirtIODevice *vdev, int n);
DEFINE_PROP_BIT("event_idx", _state, _field, \
VIRTIO_RING_F_EVENT_IDX, true)
-target_phys_addr_t virtio_queue_get_desc_addr(VirtIODevice *vdev, int n);
-target_phys_addr_t virtio_queue_get_avail_addr(VirtIODevice *vdev, int n);
-target_phys_addr_t virtio_queue_get_used_addr(VirtIODevice *vdev, int n);
-target_phys_addr_t virtio_queue_get_ring_addr(VirtIODevice *vdev, int n);
-target_phys_addr_t virtio_queue_get_desc_size(VirtIODevice *vdev, int n);
-target_phys_addr_t virtio_queue_get_avail_size(VirtIODevice *vdev, int n);
-target_phys_addr_t virtio_queue_get_used_size(VirtIODevice *vdev, int n);
-target_phys_addr_t virtio_queue_get_ring_size(VirtIODevice *vdev, int n);
+hwaddr virtio_queue_get_desc_addr(VirtIODevice *vdev, int n);
+hwaddr virtio_queue_get_avail_addr(VirtIODevice *vdev, int n);
+hwaddr virtio_queue_get_used_addr(VirtIODevice *vdev, int n);
+hwaddr virtio_queue_get_ring_addr(VirtIODevice *vdev, int n);
+hwaddr virtio_queue_get_desc_size(VirtIODevice *vdev, int n);
+hwaddr virtio_queue_get_avail_size(VirtIODevice *vdev, int n);
+hwaddr virtio_queue_get_used_size(VirtIODevice *vdev, int n);
+hwaddr virtio_queue_get_ring_size(VirtIODevice *vdev, int n);
uint16_t virtio_queue_get_last_avail_idx(VirtIODevice *vdev, int n);
void virtio_queue_set_last_avail_idx(VirtIODevice *vdev, int n, uint16_t idx);
VirtQueue *virtio_get_queue(VirtIODevice *vdev, int n);
}
}
-static uint64_t vmsvga_io_read(void *opaque, target_phys_addr_t addr,
+static uint64_t vmsvga_io_read(void *opaque, hwaddr addr,
unsigned size)
{
struct vmsvga_state_s *s = opaque;
}
}
-static void vmsvga_io_write(void *opaque, target_phys_addr_t addr,
+static void vmsvga_io_write(void *opaque, hwaddr addr,
uint64_t data, unsigned size)
{
struct vmsvga_state_s *s = opaque;
}
}
-static uint32_t i6300esb_mem_readb(void *vp, target_phys_addr_t addr)
+static uint32_t i6300esb_mem_readb(void *vp, hwaddr addr)
{
i6300esb_debug ("addr = %x\n", (int) addr);
return 0;
}
-static uint32_t i6300esb_mem_readw(void *vp, target_phys_addr_t addr)
+static uint32_t i6300esb_mem_readw(void *vp, hwaddr addr)
{
uint32_t data = 0;
I6300State *d = vp;
return data;
}
-static uint32_t i6300esb_mem_readl(void *vp, target_phys_addr_t addr)
+static uint32_t i6300esb_mem_readl(void *vp, hwaddr addr)
{
i6300esb_debug("addr = %x\n", (int) addr);
return 0;
}
-static void i6300esb_mem_writeb(void *vp, target_phys_addr_t addr, uint32_t val)
+static void i6300esb_mem_writeb(void *vp, hwaddr addr, uint32_t val)
{
I6300State *d = vp;
d->unlock_state = 2;
}
-static void i6300esb_mem_writew(void *vp, target_phys_addr_t addr, uint32_t val)
+static void i6300esb_mem_writew(void *vp, hwaddr addr, uint32_t val)
{
I6300State *d = vp;
}
}
-static void i6300esb_mem_writel(void *vp, target_phys_addr_t addr, uint32_t val)
+static void i6300esb_mem_writel(void *vp, hwaddr addr, uint32_t val)
{
I6300State *d = vp;
#include "hw/msi.h"
#include "xen.h"
-static uint64_t xen_apic_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t xen_apic_mem_read(void *opaque, hwaddr addr,
unsigned size)
{
return ~(uint64_t)0;
}
-static void xen_apic_mem_write(void *opaque, target_phys_addr_t addr,
+static void xen_apic_mem_write(void *opaque, hwaddr addr,
uint64_t data, unsigned size)
{
if (size != sizeof(uint32_t)) {
memory_region_init_io(&d->bar, &xen_pci_io_ops, d, "xen-pci", 0x100);
}
-static uint64_t platform_mmio_read(void *opaque, target_phys_addr_t addr,
+static uint64_t platform_mmio_read(void *opaque, hwaddr addr,
unsigned size)
{
DPRINTF("Warning: attempted read from physical address "
return 0;
}
-static void platform_mmio_write(void *opaque, target_phys_addr_t addr,
+static void platform_mmio_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
DPRINTF("Warning: attempted write of 0x%"PRIx64" to physical "
/* register regions */
-static uint64_t xen_pt_bar_read(void *o, target_phys_addr_t addr,
+static uint64_t xen_pt_bar_read(void *o, hwaddr addr,
unsigned size)
{
PCIDevice *d = o;
addr);
return 0;
}
-static void xen_pt_bar_write(void *o, target_phys_addr_t addr, uint64_t val,
+static void xen_pt_bar_write(void *o, hwaddr addr, uint64_t val,
unsigned size)
{
PCIDevice *d = o;
}
}
-static void pci_msix_write(void *opaque, target_phys_addr_t addr,
+static void pci_msix_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
XenPCIPassthroughState *s = opaque;
}
}
-static uint64_t pci_msix_read(void *opaque, target_phys_addr_t addr,
+static uint64_t pci_msix_read(void *opaque, hwaddr addr,
unsigned size)
{
XenPCIPassthroughState *s = opaque;
qemu_set_irq(s->sbd_irq, !!stat);
}
-static uint64_t enet_read(void *opaque, target_phys_addr_t addr, unsigned size)
+static uint64_t enet_read(void *opaque, hwaddr addr, unsigned size)
{
struct XgmacState *s = opaque;
uint64_t r = 0;
return r;
}
-static void enet_write(void *opaque, target_phys_addr_t addr,
+static void enet_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct XgmacState *s = opaque;
#include "net.h"
static inline DeviceState *
-xilinx_intc_create(target_phys_addr_t base, qemu_irq irq, int kind_of_intr)
+xilinx_intc_create(hwaddr base, qemu_irq irq, int kind_of_intr)
{
DeviceState *dev;
/* OPB Timer/Counter. */
static inline DeviceState *
-xilinx_timer_create(target_phys_addr_t base, qemu_irq irq, int oto, int freq)
+xilinx_timer_create(hwaddr base, qemu_irq irq, int oto, int freq)
{
DeviceState *dev;
/* XPS Ethernet Lite MAC. */
static inline DeviceState *
-xilinx_ethlite_create(NICInfo *nd, target_phys_addr_t base, qemu_irq irq,
+xilinx_ethlite_create(NICInfo *nd, hwaddr base, qemu_irq irq,
int txpingpong, int rxpingpong)
{
DeviceState *dev;
static inline DeviceState *
xilinx_axiethernet_create(NICInfo *nd, StreamSlave *peer,
- target_phys_addr_t base, qemu_irq irq,
+ hwaddr base, qemu_irq irq,
int txmem, int rxmem)
{
DeviceState *dev;
static inline void
xilinx_axiethernetdma_init(DeviceState *dev, StreamSlave *peer,
- target_phys_addr_t base, qemu_irq irq,
+ hwaddr base, qemu_irq irq,
qemu_irq irq2, int freqhz)
{
Error *errp = NULL;
}
/* Map an offset addr into a channel index. */
-static inline int streamid_from_addr(target_phys_addr_t addr)
+static inline int streamid_from_addr(hwaddr addr)
{
int sid;
}
#endif
-static void stream_desc_load(struct Stream *s, target_phys_addr_t addr)
+static void stream_desc_load(struct Stream *s, hwaddr addr)
{
struct SDesc *d = &s->desc;
int i;
}
}
-static void stream_desc_store(struct Stream *s, target_phys_addr_t addr)
+static void stream_desc_store(struct Stream *s, hwaddr addr)
{
struct SDesc *d = &s->desc;
int i;
stream_update_irq(s);
}
-static uint64_t axidma_read(void *opaque, target_phys_addr_t addr,
+static uint64_t axidma_read(void *opaque, hwaddr addr,
unsigned size)
{
struct XilinxAXIDMA *d = opaque;
}
-static void axidma_write(void *opaque, target_phys_addr_t addr,
+static void axidma_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct XilinxAXIDMA *d = opaque;
qemu_set_irq(s->irq, !!s->regs[R_IP]);
}
-static uint64_t enet_read(void *opaque, target_phys_addr_t addr, unsigned size)
+static uint64_t enet_read(void *opaque, hwaddr addr, unsigned size)
{
struct XilinxAXIEnet *s = opaque;
uint32_t r = 0;
return r;
}
-static void enet_write(void *opaque, target_phys_addr_t addr,
+static void enet_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct XilinxAXIEnet *s = opaque;
}
static uint64_t
-eth_read(void *opaque, target_phys_addr_t addr, unsigned int size)
+eth_read(void *opaque, hwaddr addr, unsigned int size)
{
struct xlx_ethlite *s = opaque;
uint32_t r = 0;
}
static void
-eth_write(void *opaque, target_phys_addr_t addr,
+eth_write(void *opaque, hwaddr addr,
uint64_t val64, unsigned int size)
{
struct xlx_ethlite *s = opaque;
}
static uint64_t
-pic_read(void *opaque, target_phys_addr_t addr, unsigned int size)
+pic_read(void *opaque, hwaddr addr, unsigned int size)
{
struct xlx_pic *p = opaque;
uint32_t r = 0;
}
static void
-pic_write(void *opaque, target_phys_addr_t addr,
+pic_write(void *opaque, hwaddr addr,
uint64_t val64, unsigned int size)
{
struct xlx_pic *p = opaque;
}
static uint64_t
-spi_read(void *opaque, target_phys_addr_t addr, unsigned int size)
+spi_read(void *opaque, hwaddr addr, unsigned int size)
{
XilinxSPI *s = opaque;
uint32_t r = 0;
}
static void
-spi_write(void *opaque, target_phys_addr_t addr,
+spi_write(void *opaque, hwaddr addr,
uint64_t val64, unsigned int size)
{
XilinxSPI *s = opaque;
xilinx_spips_update_ixr(s);
}
-static uint64_t xilinx_spips_read(void *opaque, target_phys_addr_t addr,
+static uint64_t xilinx_spips_read(void *opaque, hwaddr addr,
unsigned size)
{
XilinxSPIPS *s = opaque;
}
-static void xilinx_spips_write(void *opaque, target_phys_addr_t addr,
+static void xilinx_spips_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
int mask = ~0;
return 2 - t->one_timer_only;
}
-static inline unsigned int timer_from_addr(target_phys_addr_t addr)
+static inline unsigned int timer_from_addr(hwaddr addr)
{
/* Timers get a 4x32bit control reg area each. */
return addr >> 2;
}
static uint64_t
-timer_read(void *opaque, target_phys_addr_t addr, unsigned int size)
+timer_read(void *opaque, hwaddr addr, unsigned int size)
{
struct timerblock *t = opaque;
struct xlx_timer *xt;
}
static void
-timer_write(void *opaque, target_phys_addr_t addr,
+timer_write(void *opaque, hwaddr addr,
uint64_t val64, unsigned int size)
{
struct timerblock *t = opaque;
}
static uint64_t
-uart_read(void *opaque, target_phys_addr_t addr, unsigned int size)
+uart_read(void *opaque, hwaddr addr, unsigned int size)
{
struct xlx_uartlite *s = opaque;
uint32_t r = 0;
}
static void
-uart_write(void *opaque, target_phys_addr_t addr,
+uart_write(void *opaque, hwaddr addr,
uint64_t val64, unsigned int size)
{
struct xlx_uartlite *s = opaque;
s->switches = 0;
}
-static uint64_t lx60_fpga_read(void *opaque, target_phys_addr_t addr,
+static uint64_t lx60_fpga_read(void *opaque, hwaddr addr,
unsigned size)
{
Lx60FpgaState *s = opaque;
return 0;
}
-static void lx60_fpga_write(void *opaque, target_phys_addr_t addr,
+static void lx60_fpga_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
Lx60FpgaState *s = opaque;
};
static Lx60FpgaState *lx60_fpga_init(MemoryRegion *address_space,
- target_phys_addr_t base)
+ hwaddr base)
{
Lx60FpgaState *s = g_malloc(sizeof(Lx60FpgaState));
}
static void lx60_net_init(MemoryRegion *address_space,
- target_phys_addr_t base,
- target_phys_addr_t descriptors,
- target_phys_addr_t buffers,
+ hwaddr base,
+ hwaddr descriptors,
+ hwaddr buffers,
qemu_irq irq, NICInfo *nd)
{
DeviceState *dev;
s->prev_level = level;
}
-static uint64_t scoop_read(void *opaque, target_phys_addr_t addr,
+static uint64_t scoop_read(void *opaque, hwaddr addr,
unsigned size)
{
ScoopInfo *s = (ScoopInfo *) opaque;
return 0;
}
-static void scoop_write(void *opaque, target_phys_addr_t addr,
+static void scoop_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
ScoopInfo *s = (ScoopInfo *) opaque;
.phadadj = 0x01,
};
-void sl_bootparam_write(target_phys_addr_t ptr)
+void sl_bootparam_write(hwaddr ptr)
{
cpu_physical_memory_write(ptr, (void *)&zaurus_bootparam,
sizeof(struct sl_param_info));
}
static inline uint32_t zynq_slcr_read_imp(void *opaque,
- target_phys_addr_t offset)
+ hwaddr offset)
{
ZynqSLCRState *s = (ZynqSLCRState *)opaque;
}
}
-static uint64_t zynq_slcr_read(void *opaque, target_phys_addr_t offset,
+static uint64_t zynq_slcr_read(void *opaque, hwaddr offset,
unsigned size)
{
uint32_t ret = zynq_slcr_read_imp(opaque, offset);
return ret;
}
-static void zynq_slcr_write(void *opaque, target_phys_addr_t offset,
+static void zynq_slcr_write(void *opaque, hwaddr offset,
uint64_t val, unsigned size)
{
ZynqSLCRState *s = (ZynqSLCRState *)opaque;
--- /dev/null
+/* Define hwaddr if it exists. */
+
+#ifndef HWADDR_H
+#define HWADDR_H
+
+#ifndef CONFIG_USER_ONLY
+
+#define HWADDR_BITS 64
+/* hwaddr is the type of a physical address (its size can
+ be different from 'target_ulong'). */
+
+typedef uint64_t hwaddr;
+#define HWADDR_MAX UINT64_MAX
+#define TARGET_FMT_plx "%016" PRIx64
+#define HWADDR_PRId PRId64
+#define HWADDR_PRIi PRIi64
+#define HWADDR_PRIo PRIo64
+#define HWADDR_PRIu PRIu64
+#define HWADDR_PRIx PRIx64
+#define HWADDR_PRIX PRIX64
+
+#endif
+
+#endif
typedef struct KVMSlot
{
- target_phys_addr_t start_addr;
+ hwaddr start_addr;
ram_addr_t memory_size;
void *ram;
int slot;
}
static KVMSlot *kvm_lookup_matching_slot(KVMState *s,
- target_phys_addr_t start_addr,
- target_phys_addr_t end_addr)
+ hwaddr start_addr,
+ hwaddr end_addr)
{
int i;
* Find overlapping slot with lowest start address
*/
static KVMSlot *kvm_lookup_overlapping_slot(KVMState *s,
- target_phys_addr_t start_addr,
- target_phys_addr_t end_addr)
+ hwaddr start_addr,
+ hwaddr end_addr)
{
KVMSlot *found = NULL;
int i;
}
int kvm_physical_memory_addr_from_host(KVMState *s, void *ram,
- target_phys_addr_t *phys_addr)
+ hwaddr *phys_addr)
{
int i;
return kvm_set_user_memory_region(s, mem);
}
-static int kvm_dirty_pages_log_change(target_phys_addr_t phys_addr,
+static int kvm_dirty_pages_log_change(hwaddr phys_addr,
ram_addr_t size, bool log_dirty)
{
KVMState *s = kvm_state;
if (mem == NULL) {
fprintf(stderr, "BUG: %s: invalid parameters " TARGET_FMT_plx "-"
TARGET_FMT_plx "\n", __func__, phys_addr,
- (target_phys_addr_t)(phys_addr + size - 1));
+ (hwaddr)(phys_addr + size - 1));
return -EINVAL;
}
return kvm_slot_dirty_pages_log_change(mem, log_dirty);
{
unsigned int i, j;
unsigned long page_number, c;
- target_phys_addr_t addr, addr1;
+ hwaddr addr, addr1;
unsigned int len = ((section->size / TARGET_PAGE_SIZE) + HOST_LONG_BITS - 1) / HOST_LONG_BITS;
unsigned long hpratio = getpagesize() / TARGET_PAGE_SIZE;
KVMDirtyLog d;
KVMSlot *mem;
int ret = 0;
- target_phys_addr_t start_addr = section->offset_within_address_space;
- target_phys_addr_t end_addr = start_addr + section->size;
+ hwaddr start_addr = section->offset_within_address_space;
+ hwaddr end_addr = start_addr + section->size;
d.dirty_bitmap = NULL;
while (start_addr < end_addr) {
static void kvm_coalesce_mmio_region(MemoryListener *listener,
MemoryRegionSection *secion,
- target_phys_addr_t start, target_phys_addr_t size)
+ hwaddr start, hwaddr size)
{
KVMState *s = kvm_state;
static void kvm_uncoalesce_mmio_region(MemoryListener *listener,
MemoryRegionSection *secion,
- target_phys_addr_t start, target_phys_addr_t size)
+ hwaddr start, hwaddr size)
{
KVMState *s = kvm_state;
int err;
MemoryRegion *mr = section->mr;
bool log_dirty = memory_region_is_logging(mr);
- target_phys_addr_t start_addr = section->offset_within_address_space;
+ hwaddr start_addr = section->offset_within_address_space;
ram_addr_t size = section->size;
void *ram = NULL;
unsigned delta;
#if !defined(CONFIG_USER_ONLY)
int kvm_physical_memory_addr_from_host(KVMState *s, void *ram_addr,
- target_phys_addr_t *phys_addr);
+ hwaddr *phys_addr);
#endif
#endif
struct MemoryRegion;
struct MemoryRegionSection;
-void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size);
-void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size);
+void qemu_register_coalesced_mmio(hwaddr addr, ram_addr_t size);
+void qemu_unregister_coalesced_mmio(hwaddr addr, ram_addr_t size);
int cpu_physical_memory_set_dirty_tracking(int enable);
/* Range of memory in the global map. Addresses are absolute. */
struct FlatRange {
MemoryRegion *mr;
- target_phys_addr_t offset_in_region;
+ hwaddr offset_in_region;
AddrRange addr;
uint8_t dirty_log_mask;
bool readable;
}
static void memory_region_read_accessor(void *opaque,
- target_phys_addr_t addr,
+ hwaddr addr,
uint64_t *value,
unsigned size,
unsigned shift,
}
static void memory_region_write_accessor(void *opaque,
- target_phys_addr_t addr,
+ hwaddr addr,
uint64_t *value,
unsigned size,
unsigned shift,
mr->ops->write(mr->opaque, addr, tmp, size);
}
-static void access_with_adjusted_size(target_phys_addr_t addr,
+static void access_with_adjusted_size(hwaddr addr,
uint64_t *value,
unsigned size,
unsigned access_size_min,
unsigned access_size_max,
void (*access)(void *opaque,
- target_phys_addr_t addr,
+ hwaddr addr,
uint64_t *value,
unsigned size,
unsigned shift,
{
MemoryRegion *subregion;
unsigned i;
- target_phys_addr_t offset_in_region;
+ hwaddr offset_in_region;
Int128 remain;
Int128 now;
FlatRange fr;
}
static bool memory_region_access_valid(MemoryRegion *mr,
- target_phys_addr_t addr,
+ hwaddr addr,
unsigned size,
bool is_write)
{
}
static uint64_t memory_region_dispatch_read1(MemoryRegion *mr,
- target_phys_addr_t addr,
+ hwaddr addr,
unsigned size)
{
uint64_t data = 0;
}
static uint64_t memory_region_dispatch_read(MemoryRegion *mr,
- target_phys_addr_t addr,
+ hwaddr addr,
unsigned size)
{
uint64_t ret;
}
static void memory_region_dispatch_write(MemoryRegion *mr,
- target_phys_addr_t addr,
+ hwaddr addr,
uint64_t data,
unsigned size)
{
void memory_region_init_alias(MemoryRegion *mr,
const char *name,
MemoryRegion *orig,
- target_phys_addr_t offset,
+ hwaddr offset,
uint64_t size)
{
memory_region_init(mr, name, size);
mr->ram_addr = qemu_ram_alloc(size, mr);
}
-static uint64_t invalid_read(void *opaque, target_phys_addr_t addr,
+static uint64_t invalid_read(void *opaque, hwaddr addr,
unsigned size)
{
MemoryRegion *mr = opaque;
return -1U;
}
-static void invalid_write(void *opaque, target_phys_addr_t addr, uint64_t data,
+static void invalid_write(void *opaque, hwaddr addr, uint64_t data,
unsigned size)
{
MemoryRegion *mr = opaque;
memory_region_transaction_commit();
}
-bool memory_region_get_dirty(MemoryRegion *mr, target_phys_addr_t addr,
- target_phys_addr_t size, unsigned client)
+bool memory_region_get_dirty(MemoryRegion *mr, hwaddr addr,
+ hwaddr size, unsigned client)
{
assert(mr->terminates);
return cpu_physical_memory_get_dirty(mr->ram_addr + addr, size,
1 << client);
}
-void memory_region_set_dirty(MemoryRegion *mr, target_phys_addr_t addr,
- target_phys_addr_t size)
+void memory_region_set_dirty(MemoryRegion *mr, hwaddr addr,
+ hwaddr size)
{
assert(mr->terminates);
return cpu_physical_memory_set_dirty_range(mr->ram_addr + addr, size, -1);
}
}
-void memory_region_reset_dirty(MemoryRegion *mr, target_phys_addr_t addr,
- target_phys_addr_t size, unsigned client)
+void memory_region_reset_dirty(MemoryRegion *mr, hwaddr addr,
+ hwaddr size, unsigned client)
{
assert(mr->terminates);
cpu_physical_memory_reset_dirty(mr->ram_addr + addr,
}
void memory_region_add_coalescing(MemoryRegion *mr,
- target_phys_addr_t offset,
+ hwaddr offset,
uint64_t size)
{
CoalescedMemoryRange *cmr = g_malloc(sizeof(*cmr));
}
void memory_region_add_eventfd(MemoryRegion *mr,
- target_phys_addr_t addr,
+ hwaddr addr,
unsigned size,
bool match_data,
uint64_t data,
}
void memory_region_del_eventfd(MemoryRegion *mr,
- target_phys_addr_t addr,
+ hwaddr addr,
unsigned size,
bool match_data,
uint64_t data,
}
static void memory_region_add_subregion_common(MemoryRegion *mr,
- target_phys_addr_t offset,
+ hwaddr offset,
MemoryRegion *subregion)
{
MemoryRegion *other;
void memory_region_add_subregion(MemoryRegion *mr,
- target_phys_addr_t offset,
+ hwaddr offset,
MemoryRegion *subregion)
{
subregion->may_overlap = false;
}
void memory_region_add_subregion_overlap(MemoryRegion *mr,
- target_phys_addr_t offset,
+ hwaddr offset,
MemoryRegion *subregion,
unsigned priority)
{
memory_region_transaction_commit();
}
-void memory_region_set_address(MemoryRegion *mr, target_phys_addr_t addr)
+void memory_region_set_address(MemoryRegion *mr, hwaddr addr)
{
MemoryRegion *parent = mr->parent;
unsigned priority = mr->priority;
memory_region_transaction_commit();
}
-void memory_region_set_alias_offset(MemoryRegion *mr, target_phys_addr_t offset)
+void memory_region_set_alias_offset(MemoryRegion *mr, hwaddr offset)
{
assert(mr->alias);
}
MemoryRegionSection memory_region_find(MemoryRegion *address_space,
- target_phys_addr_t addr, uint64_t size)
+ hwaddr addr, uint64_t size)
{
AddressSpace *as = memory_region_to_address_space(address_space);
AddrRange range = addrrange_make(int128_make64(addr),
g_free(as->current_map);
}
-uint64_t io_mem_read(MemoryRegion *mr, target_phys_addr_t addr, unsigned size)
+uint64_t io_mem_read(MemoryRegion *mr, hwaddr addr, unsigned size)
{
return memory_region_dispatch_read(mr, addr, size);
}
-void io_mem_write(MemoryRegion *mr, target_phys_addr_t addr,
+void io_mem_write(MemoryRegion *mr, hwaddr addr,
uint64_t val, unsigned size)
{
memory_region_dispatch_write(mr, addr, val, size);
static void mtree_print_mr(fprintf_function mon_printf, void *f,
const MemoryRegion *mr, unsigned int level,
- target_phys_addr_t base,
+ hwaddr base,
MemoryRegionListHead *alias_print_queue)
{
MemoryRegionList *new_ml, *ml, *next_ml;
"-" TARGET_FMT_plx "\n",
base + mr->addr,
base + mr->addr
- + (target_phys_addr_t)int128_get64(mr->size) - 1,
+ + (hwaddr)int128_get64(mr->size) - 1,
mr->priority,
mr->readable ? 'R' : '-',
!mr->readonly && !(mr->rom_device && mr->readable) ? 'W'
mr->alias->name,
mr->alias_offset,
mr->alias_offset
- + (target_phys_addr_t)int128_get64(mr->size) - 1);
+ + (hwaddr)int128_get64(mr->size) - 1);
} else {
mon_printf(f,
TARGET_FMT_plx "-" TARGET_FMT_plx " (prio %d, %c%c): %s\n",
base + mr->addr,
base + mr->addr
- + (target_phys_addr_t)int128_get64(mr->size) - 1,
+ + (hwaddr)int128_get64(mr->size) - 1,
mr->priority,
mr->readable ? 'R' : '-',
!mr->readonly && !(mr->rom_device && mr->readable) ? 'W'
#include <stdbool.h>
#include "qemu-common.h"
#include "cpu-common.h"
-#include "targphys.h"
+#include "hwaddr.h"
#include "qemu-queue.h"
#include "iorange.h"
#include "ioport.h"
struct MemoryRegionIORange {
IORange iorange;
MemoryRegion *mr;
- target_phys_addr_t offset;
+ hwaddr offset;
};
/*
/* Read from the memory region. @addr is relative to @mr; @size is
* in bytes. */
uint64_t (*read)(void *opaque,
- target_phys_addr_t addr,
+ hwaddr addr,
unsigned size);
/* Write to the memory region. @addr is relative to @mr; @size is
* in bytes. */
void (*write)(void *opaque,
- target_phys_addr_t addr,
+ hwaddr addr,
uint64_t data,
unsigned size);
* by the device (and results in machine dependent behaviour such
* as a machine check exception).
*/
- bool (*accepts)(void *opaque, target_phys_addr_t addr,
+ bool (*accepts)(void *opaque, hwaddr addr,
unsigned size, bool is_write);
} valid;
/* Internal implementation constraints: */
void *opaque;
MemoryRegion *parent;
Int128 size;
- target_phys_addr_t addr;
+ hwaddr addr;
void (*destructor)(MemoryRegion *mr);
ram_addr_t ram_addr;
bool subpage;
bool warning_printed; /* For reservations */
bool flush_coalesced_mmio;
MemoryRegion *alias;
- target_phys_addr_t alias_offset;
+ hwaddr alias_offset;
unsigned priority;
bool may_overlap;
QTAILQ_HEAD(subregions, MemoryRegion) subregions;
struct MemoryRegionSection {
MemoryRegion *mr;
AddressSpace *address_space;
- target_phys_addr_t offset_within_region;
+ hwaddr offset_within_region;
uint64_t size;
- target_phys_addr_t offset_within_address_space;
+ hwaddr offset_within_address_space;
bool readonly;
};
void (*eventfd_del)(MemoryListener *listener, MemoryRegionSection *section,
bool match_data, uint64_t data, EventNotifier *e);
void (*coalesced_mmio_add)(MemoryListener *listener, MemoryRegionSection *section,
- target_phys_addr_t addr, target_phys_addr_t len);
+ hwaddr addr, hwaddr len);
void (*coalesced_mmio_del)(MemoryListener *listener, MemoryRegionSection *section,
- target_phys_addr_t addr, target_phys_addr_t len);
+ hwaddr addr, hwaddr len);
/* Lower = earlier (during add), later (during del) */
unsigned priority;
AddressSpace *address_space_filter;
void memory_region_init_alias(MemoryRegion *mr,
const char *name,
MemoryRegion *orig,
- target_phys_addr_t offset,
+ hwaddr offset,
uint64_t size);
/**
* @client: the user of the logging information; %DIRTY_MEMORY_MIGRATION or
* %DIRTY_MEMORY_VGA.
*/
-bool memory_region_get_dirty(MemoryRegion *mr, target_phys_addr_t addr,
- target_phys_addr_t size, unsigned client);
+bool memory_region_get_dirty(MemoryRegion *mr, hwaddr addr,
+ hwaddr size, unsigned client);
/**
* memory_region_set_dirty: Mark a range of bytes as dirty in a memory region.
* @addr: the address (relative to the start of the region) being dirtied.
* @size: size of the range being dirtied.
*/
-void memory_region_set_dirty(MemoryRegion *mr, target_phys_addr_t addr,
- target_phys_addr_t size);
+void memory_region_set_dirty(MemoryRegion *mr, hwaddr addr,
+ hwaddr size);
/**
* memory_region_sync_dirty_bitmap: Synchronize a region's dirty bitmap with
* @client: the user of the logging information; %DIRTY_MEMORY_MIGRATION or
* %DIRTY_MEMORY_VGA.
*/
-void memory_region_reset_dirty(MemoryRegion *mr, target_phys_addr_t addr,
- target_phys_addr_t size, unsigned client);
+void memory_region_reset_dirty(MemoryRegion *mr, hwaddr addr,
+ hwaddr size, unsigned client);
/**
* memory_region_set_readonly: Turn a memory region read-only (or read-write)
* @size: the size of the subrange to be coalesced.
*/
void memory_region_add_coalescing(MemoryRegion *mr,
- target_phys_addr_t offset,
+ hwaddr offset,
uint64_t size);
/**
* @fd: the eventfd to be triggered when @addr, @size, and @data all match.
**/
void memory_region_add_eventfd(MemoryRegion *mr,
- target_phys_addr_t addr,
+ hwaddr addr,
unsigned size,
bool match_data,
uint64_t data,
* @fd: the eventfd to be triggered when @addr, @size, and @data all match.
*/
void memory_region_del_eventfd(MemoryRegion *mr,
- target_phys_addr_t addr,
+ hwaddr addr,
unsigned size,
bool match_data,
uint64_t data,
* @subregion: the subregion to be added.
*/
void memory_region_add_subregion(MemoryRegion *mr,
- target_phys_addr_t offset,
+ hwaddr offset,
MemoryRegion *subregion);
/**
* memory_region_add_subregion_overlap: Add a subregion to a container
* @priority: used for resolving overlaps; highest priority wins.
*/
void memory_region_add_subregion_overlap(MemoryRegion *mr,
- target_phys_addr_t offset,
+ hwaddr offset,
MemoryRegion *subregion,
unsigned priority);
* @mr: the region to be updated
* @addr: new address, relative to parent region
*/
-void memory_region_set_address(MemoryRegion *mr, target_phys_addr_t addr);
+void memory_region_set_address(MemoryRegion *mr, hwaddr addr);
/*
* memory_region_set_alias_offset: dynamically update a memory alias's offset
* @offset: the new offset into the target memory region
*/
void memory_region_set_alias_offset(MemoryRegion *mr,
- target_phys_addr_t offset);
+ hwaddr offset);
/**
* memory_region_find: locate a MemoryRegion in an address space
* @size: size of the area to be searched
*/
MemoryRegionSection memory_region_find(MemoryRegion *address_space,
- target_phys_addr_t addr, uint64_t size);
+ hwaddr addr, uint64_t size);
/**
* memory_region_section_addr: get offset within MemoryRegionSection
* @section: the memory region section being queried
* @addr: address in address space
*/
-static inline target_phys_addr_t
+static inline hwaddr
memory_region_section_addr(MemoryRegionSection *section,
- target_phys_addr_t addr)
+ hwaddr addr)
{
addr -= section->offset_within_address_space;
addr += section->offset_within_region;
* @buf: buffer with the data transferred
* @is_write: indicates the transfer direction
*/
-void address_space_rw(AddressSpace *as, target_phys_addr_t addr, uint8_t *buf,
+void address_space_rw(AddressSpace *as, hwaddr addr, uint8_t *buf,
int len, bool is_write);
/**
* @addr: address within that address space
* @buf: buffer with the data transferred
*/
-void address_space_write(AddressSpace *as, target_phys_addr_t addr,
+void address_space_write(AddressSpace *as, hwaddr addr,
const uint8_t *buf, int len);
/**
* @addr: address within that address space
* @buf: buffer with the data transferred
*/
-void address_space_read(AddressSpace *as, target_phys_addr_t addr, uint8_t *buf, int len);
+void address_space_read(AddressSpace *as, hwaddr addr, uint8_t *buf, int len);
/* address_space_map: map a physical memory region into a host virtual address
*
* @plen: pointer to length of buffer; updated on return
* @is_write: indicates the transfer direction
*/
-void *address_space_map(AddressSpace *as, target_phys_addr_t addr,
- target_phys_addr_t *plen, bool is_write);
+void *address_space_map(AddressSpace *as, hwaddr addr,
+ hwaddr *plen, bool is_write);
/* address_space_unmap: Unmaps a memory region previously mapped by address_space_map()
*
* @access_len: amount of data actually transferred
* @is_write: indicates the transfer direction
*/
-void address_space_unmap(AddressSpace *as, void *buffer, target_phys_addr_t len,
- int is_write, target_phys_addr_t access_len);
+void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len,
+ int is_write, hwaddr access_len);
#endif
}
static void create_new_memory_mapping(MemoryMappingList *list,
- target_phys_addr_t phys_addr,
- target_phys_addr_t virt_addr,
+ hwaddr phys_addr,
+ hwaddr virt_addr,
ram_addr_t length)
{
MemoryMapping *memory_mapping;
}
static inline bool mapping_contiguous(MemoryMapping *map,
- target_phys_addr_t phys_addr,
- target_phys_addr_t virt_addr)
+ hwaddr phys_addr,
+ hwaddr virt_addr)
{
return phys_addr == map->phys_addr + map->length &&
virt_addr == map->virt_addr + map->length;
* [phys_addr, phys_addr + length) have intersection?
*/
static inline bool mapping_have_same_region(MemoryMapping *map,
- target_phys_addr_t phys_addr,
+ hwaddr phys_addr,
ram_addr_t length)
{
return !(phys_addr + length < map->phys_addr ||
* intersection are the same?
*/
static inline bool mapping_conflict(MemoryMapping *map,
- target_phys_addr_t phys_addr,
- target_phys_addr_t virt_addr)
+ hwaddr phys_addr,
+ hwaddr virt_addr)
{
return virt_addr - map->virt_addr != phys_addr - map->phys_addr;
}
* in the intersection are the same.
*/
static inline void mapping_merge(MemoryMapping *map,
- target_phys_addr_t virt_addr,
+ hwaddr virt_addr,
ram_addr_t length)
{
if (virt_addr < map->virt_addr) {
}
void memory_mapping_list_add_merge_sorted(MemoryMappingList *list,
- target_phys_addr_t phys_addr,
- target_phys_addr_t virt_addr,
+ hwaddr phys_addr,
+ hwaddr virt_addr,
ram_addr_t length)
{
MemoryMapping *memory_mapping, *last_mapping;
/* The physical and virtual address in the memory mapping are contiguous. */
typedef struct MemoryMapping {
- target_phys_addr_t phys_addr;
+ hwaddr phys_addr;
target_ulong virt_addr;
ram_addr_t length;
QTAILQ_ENTRY(MemoryMapping) next;
* and is contiguous. The list is sorted by phys_addr.
*/
void memory_mapping_list_add_merge_sorted(MemoryMappingList *list,
- target_phys_addr_t phys_addr,
- target_phys_addr_t virt_addr,
+ hwaddr phys_addr,
+ hwaddr virt_addr,
ram_addr_t length);
void memory_mapping_list_free(MemoryMappingList *list);
}
static void memory_dump(Monitor *mon, int count, int format, int wsize,
- target_phys_addr_t addr, int is_physical)
+ hwaddr addr, int is_physical)
{
CPUArchState *env;
int l, line_size, i, max_digits, len;
int count = qdict_get_int(qdict, "count");
int format = qdict_get_int(qdict, "format");
int size = qdict_get_int(qdict, "size");
- target_phys_addr_t addr = qdict_get_int(qdict, "addr");
+ hwaddr addr = qdict_get_int(qdict, "addr");
memory_dump(mon, count, format, size, addr, 1);
}
static void do_print(Monitor *mon, const QDict *qdict)
{
int format = qdict_get_int(qdict, "format");
- target_phys_addr_t val = qdict_get_int(qdict, "val");
+ hwaddr val = qdict_get_int(qdict, "val");
switch(format) {
case 'o':
- monitor_printf(mon, "%#" TARGET_PRIoPHYS, val);
+ monitor_printf(mon, "%#" HWADDR_PRIo, val);
break;
case 'x':
- monitor_printf(mon, "%#" TARGET_PRIxPHYS, val);
+ monitor_printf(mon, "%#" HWADDR_PRIx, val);
break;
case 'u':
- monitor_printf(mon, "%" TARGET_PRIuPHYS, val);
+ monitor_printf(mon, "%" HWADDR_PRIu, val);
break;
default:
case 'd':
- monitor_printf(mon, "%" TARGET_PRIdPHYS, val);
+ monitor_printf(mon, "%" HWADDR_PRId, val);
break;
case 'c':
monitor_printc(mon, val);
}
#if defined(TARGET_I386)
-static void print_pte(Monitor *mon, target_phys_addr_t addr,
- target_phys_addr_t pte,
- target_phys_addr_t mask)
+static void print_pte(Monitor *mon, hwaddr addr,
+ hwaddr pte,
+ hwaddr mask)
{
#ifdef TARGET_X86_64
if (addr & (1ULL << 47)) {
if (pde & PG_PSE_MASK) {
/* 2M pages with PAE, CR4.PSE is ignored */
print_pte(mon, (l1 << 30 ) + (l2 << 21), pde,
- ~((target_phys_addr_t)(1 << 20) - 1));
+ ~((hwaddr)(1 << 20) - 1));
} else {
pt_addr = pde & 0x3fffffffff000ULL;
for (l3 = 0; l3 < 512; l3++) {
print_pte(mon, (l1 << 30 ) + (l2 << 21)
+ (l3 << 12),
pte & ~PG_PSE_MASK,
- ~(target_phys_addr_t)0xfff);
+ ~(hwaddr)0xfff);
}
}
}
}
}
-static void mem_print(Monitor *mon, target_phys_addr_t *pstart,
+static void mem_print(Monitor *mon, hwaddr *pstart,
int *plast_prot,
- target_phys_addr_t end, int prot)
+ hwaddr end, int prot)
{
int prot1;
prot1 = *plast_prot;
unsigned int l1, l2;
int prot, last_prot;
uint32_t pgd, pde, pte;
- target_phys_addr_t start, end;
+ hwaddr start, end;
pgd = env->cr[3] & ~0xfff;
last_prot = 0;
}
}
/* Flush last range */
- mem_print(mon, &start, &last_prot, (target_phys_addr_t)1 << 32, 0);
+ mem_print(mon, &start, &last_prot, (hwaddr)1 << 32, 0);
}
static void mem_info_pae32(Monitor *mon, CPUArchState *env)
int prot, last_prot;
uint64_t pdpe, pde, pte;
uint64_t pdp_addr, pd_addr, pt_addr;
- target_phys_addr_t start, end;
+ hwaddr start, end;
pdp_addr = env->cr[3] & ~0x1f;
last_prot = 0;
}
}
/* Flush last range */
- mem_print(mon, &start, &last_prot, (target_phys_addr_t)1 << 32, 0);
+ mem_print(mon, &start, &last_prot, (hwaddr)1 << 32, 0);
}
}
}
/* Flush last range */
- mem_print(mon, &start, &last_prot, (target_phys_addr_t)1 << 48, 0);
+ mem_print(mon, &start, &last_prot, (hwaddr)1 << 48, 0);
}
#endif
int mmu_idx,
uintptr_t retaddr);
static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env,
- target_phys_addr_t physaddr,
+ hwaddr physaddr,
target_ulong addr,
uintptr_t retaddr)
{
DATA_TYPE res;
int index;
target_ulong tlb_addr;
- target_phys_addr_t ioaddr;
+ hwaddr ioaddr;
uintptr_t retaddr;
/* test if there is match for unaligned or IO access */
{
DATA_TYPE res, res1, res2;
int index, shift;
- target_phys_addr_t ioaddr;
+ hwaddr ioaddr;
target_ulong tlb_addr, addr1, addr2;
index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
uintptr_t retaddr);
static inline void glue(io_write, SUFFIX)(CPUArchState *env,
- target_phys_addr_t physaddr,
+ hwaddr physaddr,
DATA_TYPE val,
target_ulong addr,
uintptr_t retaddr)
target_ulong addr, DATA_TYPE val,
int mmu_idx)
{
- target_phys_addr_t ioaddr;
+ hwaddr ioaddr;
target_ulong tlb_addr;
uintptr_t retaddr;
int index;
int mmu_idx,
uintptr_t retaddr)
{
- target_phys_addr_t ioaddr;
+ hwaddr ioaddr;
target_ulong tlb_addr;
int index, i;
#ifndef CONFIG_USER_ONLY
void swap_shadow_regs(CPUAlphaState *env);
QEMU_NORETURN void cpu_unassigned_access(CPUAlphaState *env1,
- target_phys_addr_t addr, int is_write,
+ hwaddr addr, int is_write,
int is_exec, int unused, int size);
#endif
return ret;
}
-target_phys_addr_t cpu_get_phys_page_debug(CPUAlphaState *env, target_ulong addr)
+hwaddr cpu_get_phys_page_debug(CPUAlphaState *env, target_ulong addr)
{
target_ulong phys;
int prot, fail;
cpu_loop_exit(env);
}
-void cpu_unassigned_access(CPUAlphaState *env, target_phys_addr_t addr,
+void cpu_unassigned_access(CPUAlphaState *env, hwaddr addr,
int is_write, int is_exec, int unused, int size)
{
env->trap_arg0 = addr;
#ifndef CONFIG_USER_ONLY
static inline int get_phys_addr(CPUARMState *env, uint32_t address,
int access_type, int is_user,
- target_phys_addr_t *phys_ptr, int *prot,
+ hwaddr *phys_ptr, int *prot,
target_ulong *page_size);
#endif
static int ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
{
- target_phys_addr_t phys_addr;
+ hwaddr phys_addr;
target_ulong page_size;
int prot;
int ret, is_user = ri->opc2 & 2;
}
static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type,
- int is_user, target_phys_addr_t *phys_ptr,
+ int is_user, hwaddr *phys_ptr,
int *prot, target_ulong *page_size)
{
int code;
int ap;
int domain;
int domain_prot;
- target_phys_addr_t phys_addr;
+ hwaddr phys_addr;
/* Pagetable walk. */
/* Lookup l1 descriptor. */
}
static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type,
- int is_user, target_phys_addr_t *phys_ptr,
+ int is_user, hwaddr *phys_ptr,
int *prot, target_ulong *page_size)
{
int code;
int ap;
int domain = 0;
int domain_prot;
- target_phys_addr_t phys_addr;
+ hwaddr phys_addr;
/* Pagetable walk. */
/* Lookup l1 descriptor. */
static int get_phys_addr_lpae(CPUARMState *env, uint32_t address,
int access_type, int is_user,
- target_phys_addr_t *phys_ptr, int *prot,
+ hwaddr *phys_ptr, int *prot,
target_ulong *page_size_ptr)
{
/* Read an LPAE long-descriptor translation table. */
uint64_t ttbr;
int ttbr_select;
int n;
- target_phys_addr_t descaddr;
+ hwaddr descaddr;
uint32_t tableattrs;
target_ulong page_size;
uint32_t attrs;
static int get_phys_addr_mpu(CPUARMState *env, uint32_t address,
int access_type, int is_user,
- target_phys_addr_t *phys_ptr, int *prot)
+ hwaddr *phys_ptr, int *prot)
{
int n;
uint32_t mask;
*/
static inline int get_phys_addr(CPUARMState *env, uint32_t address,
int access_type, int is_user,
- target_phys_addr_t *phys_ptr, int *prot,
+ hwaddr *phys_ptr, int *prot,
target_ulong *page_size)
{
/* Fast Context Switch Extension. */
int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address,
int access_type, int mmu_idx)
{
- target_phys_addr_t phys_addr;
+ hwaddr phys_addr;
target_ulong page_size;
int prot;
int ret, is_user;
&page_size);
if (ret == 0) {
/* Map a single [sub]page. */
- phys_addr &= ~(target_phys_addr_t)0x3ff;
+ phys_addr &= ~(hwaddr)0x3ff;
address &= ~(uint32_t)0x3ff;
tlb_set_page (env, address, phys_addr, prot, mmu_idx, page_size);
return 0;
return 1;
}
-target_phys_addr_t cpu_get_phys_page_debug(CPUARMState *env, target_ulong addr)
+hwaddr cpu_get_phys_page_debug(CPUARMState *env, target_ulong addr)
{
- target_phys_addr_t phys_addr;
+ hwaddr phys_addr;
target_ulong page_size;
int prot;
int ret;
env->pregs[PR_ERP]);
}
-target_phys_addr_t cpu_get_phys_page_debug(CPUCRISState * env, target_ulong addr)
+hwaddr cpu_get_phys_page_debug(CPUCRISState * env, target_ulong addr)
{
uint32_t phy = addr;
struct cris_mmu_result res;
#include "memory_mapping.h"
/* PAE Paging or IA-32e Paging */
-static void walk_pte(MemoryMappingList *list, target_phys_addr_t pte_start_addr,
+static void walk_pte(MemoryMappingList *list, hwaddr pte_start_addr,
int32_t a20_mask, target_ulong start_line_addr)
{
- target_phys_addr_t pte_addr, start_paddr;
+ hwaddr pte_addr, start_paddr;
uint64_t pte;
target_ulong start_vaddr;
int i;
/* 32-bit Paging */
static void walk_pte2(MemoryMappingList *list,
- target_phys_addr_t pte_start_addr, int32_t a20_mask,
+ hwaddr pte_start_addr, int32_t a20_mask,
target_ulong start_line_addr)
{
- target_phys_addr_t pte_addr, start_paddr;
+ hwaddr pte_addr, start_paddr;
uint32_t pte;
target_ulong start_vaddr;
int i;
}
/* PAE Paging or IA-32e Paging */
-static void walk_pde(MemoryMappingList *list, target_phys_addr_t pde_start_addr,
+static void walk_pde(MemoryMappingList *list, hwaddr pde_start_addr,
int32_t a20_mask, target_ulong start_line_addr)
{
- target_phys_addr_t pde_addr, pte_start_addr, start_paddr;
+ hwaddr pde_addr, pte_start_addr, start_paddr;
uint64_t pde;
target_ulong line_addr, start_vaddr;
int i;
/* 32-bit Paging */
static void walk_pde2(MemoryMappingList *list,
- target_phys_addr_t pde_start_addr, int32_t a20_mask,
+ hwaddr pde_start_addr, int32_t a20_mask,
bool pse)
{
- target_phys_addr_t pde_addr, pte_start_addr, start_paddr;
+ hwaddr pde_addr, pte_start_addr, start_paddr;
uint32_t pde;
target_ulong line_addr, start_vaddr;
int i;
/* PAE Paging */
static void walk_pdpe2(MemoryMappingList *list,
- target_phys_addr_t pdpe_start_addr, int32_t a20_mask)
+ hwaddr pdpe_start_addr, int32_t a20_mask)
{
- target_phys_addr_t pdpe_addr, pde_start_addr;
+ hwaddr pdpe_addr, pde_start_addr;
uint64_t pdpe;
target_ulong line_addr;
int i;
#ifdef TARGET_X86_64
/* IA-32e Paging */
static void walk_pdpe(MemoryMappingList *list,
- target_phys_addr_t pdpe_start_addr, int32_t a20_mask,
+ hwaddr pdpe_start_addr, int32_t a20_mask,
target_ulong start_line_addr)
{
- target_phys_addr_t pdpe_addr, pde_start_addr, start_paddr;
+ hwaddr pdpe_addr, pde_start_addr, start_paddr;
uint64_t pdpe;
target_ulong line_addr, start_vaddr;
int i;
/* IA-32e Paging */
static void walk_pml4e(MemoryMappingList *list,
- target_phys_addr_t pml4e_start_addr, int32_t a20_mask)
+ hwaddr pml4e_start_addr, int32_t a20_mask)
{
- target_phys_addr_t pml4e_addr, pdpe_start_addr;
+ hwaddr pml4e_addr, pdpe_start_addr;
uint64_t pml4e;
target_ulong line_addr;
int i;
if (env->cr[4] & CR4_PAE_MASK) {
#ifdef TARGET_X86_64
if (env->hflags & HF_LMA_MASK) {
- target_phys_addr_t pml4e_addr;
+ hwaddr pml4e_addr;
pml4e_addr = (env->cr[3] & ~0xfff) & env->a20_mask;
walk_pml4e(list, pml4e_addr, env->a20_mask);
} else
#endif
{
- target_phys_addr_t pdpe_addr;
+ hwaddr pdpe_addr;
pdpe_addr = (env->cr[3] & ~0x1f) & env->a20_mask;
walk_pdpe2(list, pdpe_addr, env->a20_mask);
}
} else {
- target_phys_addr_t pde_addr;
+ hwaddr pde_addr;
bool pse;
pde_addr = (env->cr[3] & ~0xfff) & env->a20_mask;
uint64_t ptep, pte;
target_ulong pde_addr, pte_addr;
int error_code, is_dirty, prot, page_size, is_write, is_user;
- target_phys_addr_t paddr;
+ hwaddr paddr;
uint32_t page_offset;
target_ulong vaddr, virt_addr;
return 1;
}
-target_phys_addr_t cpu_get_phys_page_debug(CPUX86State *env, target_ulong addr)
+hwaddr cpu_get_phys_page_debug(CPUX86State *env, target_ulong addr)
{
target_ulong pde_addr, pte_addr;
uint64_t pte;
- target_phys_addr_t paddr;
+ hwaddr paddr;
uint32_t page_offset;
int page_size;
return -ENOSYS;
}
-static void kvm_mce_inject(CPUX86State *env, target_phys_addr_t paddr, int code)
+static void kvm_mce_inject(CPUX86State *env, hwaddr paddr, int code)
{
uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
int kvm_arch_on_sigbus_vcpu(CPUX86State *env, int code, void *addr)
{
ram_addr_t ram_addr;
- target_phys_addr_t paddr;
+ hwaddr paddr;
if ((env->mcg_cap & MCG_SER_P) && addr
&& (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
{
if ((first_cpu->mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
ram_addr_t ram_addr;
- target_phys_addr_t paddr;
+ hwaddr paddr;
/* Hope we are lucky for AO MCE */
if (qemu_ram_addr_from_host(addr, &ram_addr) ||
}
#else
-static inline void svm_save_seg(CPUX86State *env, target_phys_addr_t addr,
+static inline void svm_save_seg(CPUX86State *env, hwaddr addr,
const SegmentCache *sc)
{
stw_phys(addr + offsetof(struct vmcb_seg, selector),
((sc->flags >> 8) & 0xff) | ((sc->flags >> 12) & 0x0f00));
}
-static inline void svm_load_seg(CPUX86State *env, target_phys_addr_t addr,
+static inline void svm_load_seg(CPUX86State *env, hwaddr addr,
SegmentCache *sc)
{
unsigned int flags;
sc->flags = ((flags & 0xff) << 8) | ((flags & 0x0f00) << 12);
}
-static inline void svm_load_seg_cache(CPUX86State *env, target_phys_addr_t addr,
+static inline void svm_load_seg_cache(CPUX86State *env, hwaddr addr,
int seg_reg)
{
SegmentCache sc1, *sc = &sc1;
return 0;
}
-target_phys_addr_t cpu_get_phys_page_debug(CPULM32State *env, target_ulong addr)
+hwaddr cpu_get_phys_page_debug(CPULM32State *env, target_ulong addr)
{
return addr & TARGET_PAGE_MASK;
}
/* MMU */
/* TODO: This will need fixing once the MMU is implemented. */
-target_phys_addr_t cpu_get_phys_page_debug(CPUM68KState *env, target_ulong addr)
+hwaddr cpu_get_phys_page_debug(CPUM68KState *env, target_ulong addr)
{
return addr;
}
}
#if !defined(CONFIG_USER_ONLY)
-void cpu_unassigned_access(CPUMBState *env1, target_phys_addr_t addr,
+void cpu_unassigned_access(CPUMBState *env1, hwaddr addr,
int is_write, int is_exec, int is_asi, int size);
#endif
}
}
-target_phys_addr_t cpu_get_phys_page_debug(CPUMBState * env, target_ulong addr)
+hwaddr cpu_get_phys_page_debug(CPUMBState * env, target_ulong addr)
{
target_ulong vaddr, paddr = 0;
struct microblaze_mmu_lookup lu;
mmu_write(env, rn, v);
}
-void cpu_unassigned_access(CPUMBState *env, target_phys_addr_t addr,
+void cpu_unassigned_access(CPUMBState *env, hwaddr addr,
int is_write, int is_exec, int is_asi, int size)
{
qemu_log_mask(CPU_LOG_INT, "Unassigned " TARGET_FMT_plx " wr=%d exe=%d\n",
struct CPUMIPSTLBContext {
uint32_t nb_tlb;
uint32_t tlb_in_use;
- int (*map_address) (struct CPUMIPSState *env, target_phys_addr_t *physical, int *prot, target_ulong address, int rw, int access_type);
+ int (*map_address) (struct CPUMIPSState *env, hwaddr *physical, int *prot, target_ulong address, int rw, int access_type);
void (*helper_tlbwi)(struct CPUMIPSState *env);
void (*helper_tlbwr)(struct CPUMIPSState *env);
void (*helper_tlbp)(struct CPUMIPSState *env);
#include "cpu-qom.h"
#if !defined(CONFIG_USER_ONLY)
-int no_mmu_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot,
+int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
target_ulong address, int rw, int access_type);
-int fixed_mmu_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot,
+int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
target_ulong address, int rw, int access_type);
-int r4k_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot,
+int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
target_ulong address, int rw, int access_type);
void r4k_helper_tlbwi(CPUMIPSState *env);
void r4k_helper_tlbwr(CPUMIPSState *env);
void r4k_helper_tlbp(CPUMIPSState *env);
void r4k_helper_tlbr(CPUMIPSState *env);
-void cpu_unassigned_access(CPUMIPSState *env, target_phys_addr_t addr,
+void cpu_unassigned_access(CPUMIPSState *env, hwaddr addr,
int is_write, int is_exec, int unused, int size);
#endif
void do_interrupt (CPUMIPSState *env);
#if !defined(CONFIG_USER_ONLY)
void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra);
-target_phys_addr_t cpu_mips_translate_address (CPUMIPSState *env, target_ulong address,
+hwaddr cpu_mips_translate_address (CPUMIPSState *env, target_ulong address,
int rw);
#endif
#if !defined(CONFIG_USER_ONLY)
/* no MMU emulation */
-int no_mmu_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot,
+int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
target_ulong address, int rw, int access_type)
{
*physical = address;
}
/* fixed mapping MMU emulation */
-int fixed_mmu_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot,
+int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
target_ulong address, int rw, int access_type)
{
if (address <= (int32_t)0x7FFFFFFFUL) {
}
/* MIPS32/MIPS64 R4000-style MMU emulation */
-int r4k_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot,
+int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
target_ulong address, int rw, int access_type)
{
uint8_t ASID = env->CP0_EntryHi & 0xFF;
return TLBRET_NOMATCH;
}
-static int get_physical_address (CPUMIPSState *env, target_phys_addr_t *physical,
+static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
int *prot, target_ulong address,
int rw, int access_type)
{
}
#if !defined(CONFIG_USER_ONLY)
-target_phys_addr_t cpu_get_phys_page_debug(CPUMIPSState *env, target_ulong addr)
+hwaddr cpu_get_phys_page_debug(CPUMIPSState *env, target_ulong addr)
{
- target_phys_addr_t phys_addr;
+ hwaddr phys_addr;
int prot;
if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
int mmu_idx)
{
#if !defined(CONFIG_USER_ONLY)
- target_phys_addr_t physical;
+ hwaddr physical;
int prot;
int access_type;
#endif
}
#if !defined(CONFIG_USER_ONLY)
-target_phys_addr_t cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int rw)
+hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int rw)
{
- target_phys_addr_t physical;
+ hwaddr physical;
int prot;
int access_type;
int ret = 0;
#ifndef CONFIG_USER_ONLY
-static inline target_phys_addr_t do_translate_address(CPUMIPSState *env,
+static inline hwaddr do_translate_address(CPUMIPSState *env,
target_ulong address,
int rw)
{
- target_phys_addr_t lladdr;
+ hwaddr lladdr;
lladdr = cpu_mips_translate_address(env, address, rw);
}
}
-void cpu_unassigned_access(CPUMIPSState *env, target_phys_addr_t addr,
+void cpu_unassigned_access(CPUMIPSState *env, hwaddr addr,
int is_write, int is_exec, int unused, int size)
{
if (is_exec)
OpenRISCTLBEntry dtlb[DTLB_WAYS][DTLB_SIZE];
int (*cpu_openrisc_map_address_code)(struct OpenRISCCPU *cpu,
- target_phys_addr_t *physical,
+ hwaddr *physical,
int *prot,
target_ulong address, int rw);
int (*cpu_openrisc_map_address_data)(struct OpenRISCCPU *cpu,
- target_phys_addr_t *physical,
+ hwaddr *physical,
int *prot,
target_ulong address, int rw);
} CPUOpenRISCTLBContext;
void cpu_openrisc_mmu_init(OpenRISCCPU *cpu);
int cpu_openrisc_get_phys_nommu(OpenRISCCPU *cpu,
- target_phys_addr_t *physical,
+ hwaddr *physical,
int *prot, target_ulong address, int rw);
int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu,
- target_phys_addr_t *physical,
+ hwaddr *physical,
int *prot, target_ulong address, int rw);
int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu,
- target_phys_addr_t *physical,
+ hwaddr *physical,
int *prot, target_ulong address, int rw);
#endif
#ifndef CONFIG_USER_ONLY
int cpu_openrisc_get_phys_nommu(OpenRISCCPU *cpu,
- target_phys_addr_t *physical,
+ hwaddr *physical,
int *prot, target_ulong address, int rw)
{
*physical = address;
}
int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu,
- target_phys_addr_t *physical,
+ hwaddr *physical,
int *prot, target_ulong address, int rw)
{
int vpn = address >> TARGET_PAGE_BITS;
}
int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu,
- target_phys_addr_t *physical,
+ hwaddr *physical,
int *prot, target_ulong address, int rw)
{
int vpn = address >> TARGET_PAGE_BITS;
}
static int cpu_openrisc_get_phys_addr(OpenRISCCPU *cpu,
- target_phys_addr_t *physical,
+ hwaddr *physical,
int *prot, target_ulong address,
int rw)
{
target_ulong address, int rw, int mmu_idx)
{
int ret = 0;
- target_phys_addr_t physical = 0;
+ hwaddr physical = 0;
int prot = 0;
OpenRISCCPU *cpu = OPENRISC_CPU(ENV_GET_CPU(env));
#endif
#ifndef CONFIG_USER_ONLY
-target_phys_addr_t cpu_get_phys_page_debug(CPUOpenRISCState *env,
+hwaddr cpu_get_phys_page_debug(CPUOpenRISCState *env,
target_ulong addr)
{
- target_phys_addr_t phys_addr;
+ hwaddr phys_addr;
int prot;
OpenRISCCPU *cpu = OPENRISC_CPU(ENV_GET_CPU(env));
typedef struct ppcemb_tlb_t ppcemb_tlb_t;
struct ppcemb_tlb_t {
- target_phys_addr_t RPN;
+ hwaddr RPN;
target_ulong EPN;
target_ulong PID;
target_ulong size;
int slb_nr;
#endif
/* segment registers */
- target_phys_addr_t htab_base;
- target_phys_addr_t htab_mask;
+ hwaddr htab_base;
+ hwaddr htab_mask;
target_ulong sr[32];
/* externally stored hash table */
uint8_t *external_htab;
#endif
#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
- target_phys_addr_t vpa;
- target_phys_addr_t slb_shadow;
- target_phys_addr_t dispatch_trace_log;
+ hwaddr vpa;
+ hwaddr slb_shadow;
+ hwaddr dispatch_trace_log;
uint32_t dtl_size;
#endif /* TARGET_PPC64 */
target_ulong ivor_mask;
target_ulong ivpr_mask;
target_ulong hreset_vector;
- target_phys_addr_t mpic_cpu_base;
+ hwaddr mpic_cpu_base;
#endif
/* Those resources are used only during code translation */
/* Context used internally during MMU translations */
typedef struct mmu_ctx_t mmu_ctx_t;
struct mmu_ctx_t {
- target_phys_addr_t raddr; /* Real address */
- target_phys_addr_t eaddr; /* Effective address */
+ hwaddr raddr; /* Real address */
+ hwaddr eaddr; /* Effective address */
int prot; /* Protection bits */
- target_phys_addr_t hash[2]; /* Pagetable hash values */
+ hwaddr hash[2]; /* Pagetable hash values */
target_ulong ptem; /* Virtual segment ID | API */
int key; /* Access key */
int nx; /* Non-execute area */
void store_booke_tcr (CPUPPCState *env, target_ulong val);
void store_booke_tsr (CPUPPCState *env, target_ulong val);
void booke206_flush_tlb(CPUPPCState *env, int flags, const int check_iprot);
-target_phys_addr_t booke206_tlb_to_page_size(CPUPPCState *env, ppcmas_tlb_t *tlb);
+hwaddr booke206_tlb_to_page_size(CPUPPCState *env, ppcmas_tlb_t *tlb);
int ppcmas_tlb_check(CPUPPCState *env, ppcmas_tlb_t *tlb,
- target_phys_addr_t *raddrp, target_ulong address,
+ hwaddr *raddrp, target_ulong address,
uint32_t pid);
void ppc_tlb_invalidate_all (CPUPPCState *env);
void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
pp = pte1 & 0x00000003;
}
if (ptem == ctx->ptem) {
- if (ctx->raddr != (target_phys_addr_t)-1ULL) {
+ if (ctx->raddr != (hwaddr)-1ULL) {
/* all matches should have equal RPN, WIMG & PP */
if ((ctx->raddr & mmask) != (pte1 & mmask)) {
qemu_log("Bad RPN/WIMG/PP\n");
return ret;
}
-static inline target_phys_addr_t get_pteg_offset(CPUPPCState *env,
- target_phys_addr_t hash,
+static inline hwaddr get_pteg_offset(CPUPPCState *env,
+ hwaddr hash,
int pte_size)
{
return (hash * pte_size * 8) & env->htab_mask;
static inline int find_pte2(CPUPPCState *env, mmu_ctx_t *ctx, int is_64b, int h,
int rw, int type, int target_page_bits)
{
- target_phys_addr_t pteg_off;
+ hwaddr pteg_off;
target_ulong pte0, pte1;
int i, good = -1;
int ret, r;
static inline int get_segment(CPUPPCState *env, mmu_ctx_t *ctx,
target_ulong eaddr, int rw, int type)
{
- target_phys_addr_t hash;
+ hwaddr hash;
target_ulong vsid;
int ds, pr, target_page_bits;
int ret, ret2;
ctx->hash[1] = ~hash;
/* Initialize real address with an invalid value */
- ctx->raddr = (target_phys_addr_t)-1ULL;
+ ctx->raddr = (hwaddr)-1ULL;
if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_6xx ||
env->mmu_model == POWERPC_MMU_SOFT_74xx)) {
/* Software TLB search */
}
#if defined(DUMP_PAGE_TABLES)
if (qemu_log_enabled()) {
- target_phys_addr_t curaddr;
+ hwaddr curaddr;
uint32_t a0, a1, a2, a3;
qemu_log("Page table: " TARGET_FMT_plx " len " TARGET_FMT_plx
/* Generic TLB check function for embedded PowerPC implementations */
static int ppcemb_tlb_check(CPUPPCState *env, ppcemb_tlb_t *tlb,
- target_phys_addr_t *raddrp,
+ hwaddr *raddrp,
target_ulong address, uint32_t pid, int ext,
int i)
{
uint32_t pid)
{
ppcemb_tlb_t *tlb;
- target_phys_addr_t raddr;
+ hwaddr raddr;
int i, ret;
/* Default return value is no match */
{
#if !defined(FLUSH_ALL_TLBS)
ppcemb_tlb_t *tlb;
- target_phys_addr_t raddr;
+ hwaddr raddr;
target_ulong page, end;
int i;
int access_type)
{
ppcemb_tlb_t *tlb;
- target_phys_addr_t raddr;
+ hwaddr raddr;
int i, ret, zsel, zpr, pr;
ret = -1;
- raddr = (target_phys_addr_t)-1ULL;
+ raddr = (hwaddr)-1ULL;
pr = msr_pr;
for (i = 0; i < env->nb_tlb; i++) {
tlb = &env->tlb.tlbe[i];
}
static inline int mmubooke_check_tlb(CPUPPCState *env, ppcemb_tlb_t *tlb,
- target_phys_addr_t *raddr, int *prot,
+ hwaddr *raddr, int *prot,
target_ulong address, int rw,
int access_type, int i)
{
int access_type)
{
ppcemb_tlb_t *tlb;
- target_phys_addr_t raddr;
+ hwaddr raddr;
int i, ret;
ret = -1;
- raddr = (target_phys_addr_t)-1ULL;
+ raddr = (hwaddr)-1ULL;
for (i = 0; i < env->nb_tlb; i++) {
tlb = &env->tlb.tlbe[i];
ret = mmubooke_check_tlb(env, tlb, &raddr, &ctx->prot, address, rw,
tlb_flush(env, 1);
}
-target_phys_addr_t booke206_tlb_to_page_size(CPUPPCState *env,
+hwaddr booke206_tlb_to_page_size(CPUPPCState *env,
ppcmas_tlb_t *tlb)
{
int tlbm_size;
/* TLB check function for MAS based SoftTLBs */
int ppcmas_tlb_check(CPUPPCState *env, ppcmas_tlb_t *tlb,
- target_phys_addr_t *raddrp,
+ hwaddr *raddrp,
target_ulong address, uint32_t pid)
{
target_ulong mask;
}
static int mmubooke206_check_tlb(CPUPPCState *env, ppcmas_tlb_t *tlb,
- target_phys_addr_t *raddr, int *prot,
+ hwaddr *raddr, int *prot,
target_ulong address, int rw,
int access_type)
{
int access_type)
{
ppcmas_tlb_t *tlb;
- target_phys_addr_t raddr;
+ hwaddr raddr;
int i, j, ret;
ret = -1;
- raddr = (target_phys_addr_t)-1ULL;
+ raddr = (hwaddr)-1ULL;
for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
int ways = booke206_tlb_ways(env, i);
entry = &env->tlb.tlbe[0];
for (i = 0; i < env->nb_tlb; i++, entry++) {
- target_phys_addr_t ea, pa;
+ hwaddr ea, pa;
target_ulong mask;
uint64_t size = (uint64_t)entry->size;
char size_buf[20];
mask = ~(entry->size - 1);
ea = entry->EPN & mask;
pa = entry->RPN & mask;
-#if (TARGET_PHYS_ADDR_BITS >= 36)
+#if (TARGET_PHYS_ADDR_SPACE_BITS >= 36)
/* Extend the physical address to 36 bits */
- pa |= (target_phys_addr_t)(entry->RPN & 0xF) << 32;
+ pa |= (hwaddr)(entry->RPN & 0xF) << 32;
#endif
size /= 1024;
if (size >= 1024) {
entry = &env->tlb.tlbm[offset];
for (i = 0; i < tlbsize; i++, entry++) {
- target_phys_addr_t ea, pa, size;
+ hwaddr ea, pa, size;
int tsize;
if (!(entry->mas1 & MAS1_VALID)) {
return ret;
}
-target_phys_addr_t cpu_get_phys_page_debug(CPUPPCState *env, target_ulong addr)
+hwaddr cpu_get_phys_page_debug(CPUPPCState *env, target_ulong addr)
{
mmu_ctx_t ctx;
{
ppcmas_tlb_t *tlb = NULL;
int i, j;
- target_phys_addr_t raddr;
+ hwaddr raddr;
uint32_t spid, sas;
spid = (env->spr[SPR_BOOKE_MAS6] & MAS6_SPID_MASK) >> MAS6_SPID_SHIFT;
void s390_sclp_extint(uint32_t parm);
/* from s390-virtio-bus */
-extern const target_phys_addr_t virtio_size;
+extern const hwaddr virtio_size;
#else
static inline void s390_add_running_cpu(CPUS390XState *env)
return 0;
}
-target_phys_addr_t cpu_get_phys_page_debug(CPUS390XState *env,
+hwaddr cpu_get_phys_page_debug(CPUS390XState *env,
target_ulong vaddr)
{
target_ulong raddr;
{
uint64_t mask, addr;
LowCore *lowcore;
- target_phys_addr_t len = TARGET_PAGE_SIZE;
+ hwaddr len = TARGET_PAGE_SIZE;
lowcore = cpu_physical_memory_map(env->psa, &len, 1);
{
uint64_t mask, addr;
LowCore *lowcore;
- target_phys_addr_t len = TARGET_PAGE_SIZE;
+ hwaddr len = TARGET_PAGE_SIZE;
int ilc = env->int_pgm_ilc;
switch (ilc) {
{
uint64_t mask, addr;
LowCore *lowcore;
- target_phys_addr_t len = TARGET_PAGE_SIZE;
+ hwaddr len = TARGET_PAGE_SIZE;
ExtQueue *q;
if (!(env->psw.mask & PSW_MASK_EXT)) {
static void mvc_fast_memset(CPUS390XState *env, uint32_t l, uint64_t dest,
uint8_t byte)
{
- target_phys_addr_t dest_phys;
- target_phys_addr_t len = l;
+ hwaddr dest_phys;
+ hwaddr len = l;
void *dest_p;
uint64_t asc = env->psw.mask & PSW_MASK_ASC;
int flags;
static void mvc_fast_memmove(CPUS390XState *env, uint32_t l, uint64_t dest,
uint64_t src)
{
- target_phys_addr_t dest_phys;
- target_phys_addr_t src_phys;
- target_phys_addr_t len = l;
+ hwaddr dest_phys;
+ hwaddr src_phys;
+ hwaddr len = l;
void *dest_p;
void *src_p;
uint64_t asc = env->psw.mask & PSW_MASK_ASC;
#if !defined(CONFIG_USER_ONLY)
void cpu_sh4_invalidate_tlb(CPUSH4State *s);
uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
- target_phys_addr_t addr);
-void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, target_phys_addr_t addr,
+ hwaddr addr);
+void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr,
uint32_t mem_value);
uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State *s,
- target_phys_addr_t addr);
-void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, target_phys_addr_t addr,
+ hwaddr addr);
+void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr addr,
uint32_t mem_value);
uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s,
- target_phys_addr_t addr);
-void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
+ hwaddr addr);
+void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr,
uint32_t mem_value);
uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s,
- target_phys_addr_t addr);
-void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, target_phys_addr_t addr,
+ hwaddr addr);
+void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr,
uint32_t mem_value);
#endif
return 0;
}
-target_phys_addr_t cpu_get_phys_page_debug(CPUSH4State * env, target_ulong addr)
+hwaddr cpu_get_phys_page_debug(CPUSH4State * env, target_ulong addr)
{
target_ulong physical;
int prot;
}
uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
- target_phys_addr_t addr)
+ hwaddr addr)
{
int index = (addr & 0x00000300) >> 8;
tlb_t * entry = &s->itlb[index];
(entry->asid);
}
-void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, target_phys_addr_t addr,
+void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr,
uint32_t mem_value)
{
uint32_t vpn = (mem_value & 0xfffffc00) >> 10;
}
uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State *s,
- target_phys_addr_t addr)
+ hwaddr addr)
{
int array = (addr & 0x00800000) >> 23;
int index = (addr & 0x00000300) >> 8;
}
}
-void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, target_phys_addr_t addr,
+void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr addr,
uint32_t mem_value)
{
int array = (addr & 0x00800000) >> 23;
}
uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s,
- target_phys_addr_t addr)
+ hwaddr addr)
{
int index = (addr & 0x00003f00) >> 8;
tlb_t * entry = &s->utlb[index];
(entry->asid);
}
-void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
+void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr,
uint32_t mem_value)
{
int associate = addr & 0x0000080;
}
uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s,
- target_phys_addr_t addr)
+ hwaddr addr)
{
int array = (addr & 0x00800000) >> 23;
int index = (addr & 0x00003f00) >> 8;
}
}
-void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, target_phys_addr_t addr,
+void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr,
uint32_t mem_value)
{
int array = (addr & 0x00800000) >> 23;
/* cpu-exec.c */
#if !defined(CONFIG_USER_ONLY)
-void cpu_unassigned_access(CPUSPARCState *env1, target_phys_addr_t addr,
+void cpu_unassigned_access(CPUSPARCState *env1, hwaddr addr,
int is_write, int is_exec, int is_asi, int size);
#if defined(TARGET_SPARC64)
-target_phys_addr_t cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr,
+hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr,
int mmu_idx);
#endif
#endif
case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
switch (size) {
case 1:
- ret = ldub_phys((target_phys_addr_t)addr
- | ((target_phys_addr_t)(asi & 0xf) << 32));
+ ret = ldub_phys((hwaddr)addr
+ | ((hwaddr)(asi & 0xf) << 32));
break;
case 2:
- ret = lduw_phys((target_phys_addr_t)addr
- | ((target_phys_addr_t)(asi & 0xf) << 32));
+ ret = lduw_phys((hwaddr)addr
+ | ((hwaddr)(asi & 0xf) << 32));
break;
default:
case 4:
- ret = ldl_phys((target_phys_addr_t)addr
- | ((target_phys_addr_t)(asi & 0xf) << 32));
+ ret = ldl_phys((hwaddr)addr
+ | ((hwaddr)(asi & 0xf) << 32));
break;
case 8:
- ret = ldq_phys((target_phys_addr_t)addr
- | ((target_phys_addr_t)(asi & 0xf) << 32));
+ ret = ldq_phys((hwaddr)addr
+ | ((hwaddr)(asi & 0xf) << 32));
break;
}
break;
{
switch (size) {
case 1:
- stb_phys((target_phys_addr_t)addr
- | ((target_phys_addr_t)(asi & 0xf) << 32), val);
+ stb_phys((hwaddr)addr
+ | ((hwaddr)(asi & 0xf) << 32), val);
break;
case 2:
- stw_phys((target_phys_addr_t)addr
- | ((target_phys_addr_t)(asi & 0xf) << 32), val);
+ stw_phys((hwaddr)addr
+ | ((hwaddr)(asi & 0xf) << 32), val);
break;
case 4:
default:
- stl_phys((target_phys_addr_t)addr
- | ((target_phys_addr_t)(asi & 0xf) << 32), val);
+ stl_phys((hwaddr)addr
+ | ((hwaddr)(asi & 0xf) << 32), val);
break;
case 8:
- stq_phys((target_phys_addr_t)addr
- | ((target_phys_addr_t)(asi & 0xf) << 32), val);
+ stq_phys((hwaddr)addr
+ | ((hwaddr)(asi & 0xf) << 32), val);
break;
}
}
#if !defined(CONFIG_USER_ONLY)
#ifndef TARGET_SPARC64
-void cpu_unassigned_access(CPUSPARCState *env, target_phys_addr_t addr,
+void cpu_unassigned_access(CPUSPARCState *env, hwaddr addr,
int is_write, int is_exec, int is_asi, int size)
{
int fault_type;
}
}
#else
-void cpu_unassigned_access(CPUSPARCState *env, target_phys_addr_t addr,
+void cpu_unassigned_access(CPUSPARCState *env, hwaddr addr,
int is_write, int is_exec, int is_asi, int size)
{
#ifdef DEBUG_UNASSIGNED
}
};
-static int get_physical_address(CPUSPARCState *env, target_phys_addr_t *physical,
+static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
int *prot, int *access_index,
target_ulong address, int rw, int mmu_idx,
target_ulong *page_size)
{
int access_perms = 0;
- target_phys_addr_t pde_ptr;
+ hwaddr pde_ptr;
uint32_t pde;
int error_code = 0, is_dirty, is_user;
unsigned long page_offset;
/* Even if large ptes, we map only one 4KB page in the cache to
avoid filling it too fast */
- *physical = ((target_phys_addr_t)(pde & PTE_ADDR_MASK) << 4) + page_offset;
+ *physical = ((hwaddr)(pde & PTE_ADDR_MASK) << 4) + page_offset;
return error_code;
}
int cpu_sparc_handle_mmu_fault(CPUSPARCState *env, target_ulong address, int rw,
int mmu_idx)
{
- target_phys_addr_t paddr;
+ hwaddr paddr;
target_ulong vaddr;
target_ulong page_size;
int error_code = 0, prot, access_index;
target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev)
{
- target_phys_addr_t pde_ptr;
+ hwaddr pde_ptr;
uint32_t pde;
/* Context base + context number */
- pde_ptr = (target_phys_addr_t)(env->mmuregs[1] << 4) +
+ pde_ptr = (hwaddr)(env->mmuregs[1] << 4) +
(env->mmuregs[2] << 2);
pde = ldl_phys(pde_ptr);
{
target_ulong va, va1, va2;
unsigned int n, m, o;
- target_phys_addr_t pde_ptr, pa;
+ hwaddr pde_ptr, pa;
uint32_t pde;
pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
pde = ldl_phys(pde_ptr);
(*cpu_fprintf)(f, "Root ptr: " TARGET_FMT_plx ", ctx: %d\n",
- (target_phys_addr_t)env->mmuregs[1] << 4, env->mmuregs[2]);
+ (hwaddr)env->mmuregs[1] << 4, env->mmuregs[2]);
for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {
pde = mmu_probe(env, va, 2);
if (pde) {
#else /* !TARGET_SPARC64 */
/* 41 bit physical address space */
-static inline target_phys_addr_t ultrasparc_truncate_physical(uint64_t x)
+static inline hwaddr ultrasparc_truncate_physical(uint64_t x)
{
return x & 0x1ffffffffffULL;
}
entry size */
static inline int ultrasparc_tag_match(SparcTLBEntry *tlb,
uint64_t address, uint64_t context,
- target_phys_addr_t *physical)
+ hwaddr *physical)
{
uint64_t mask;
}
static int get_physical_address_data(CPUSPARCState *env,
- target_phys_addr_t *physical, int *prot,
+ hwaddr *physical, int *prot,
target_ulong address, int rw, int mmu_idx)
{
unsigned int i;
}
static int get_physical_address_code(CPUSPARCState *env,
- target_phys_addr_t *physical, int *prot,
+ hwaddr *physical, int *prot,
target_ulong address, int mmu_idx)
{
unsigned int i;
return 1;
}
-static int get_physical_address(CPUSPARCState *env, target_phys_addr_t *physical,
+static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
int *prot, int *access_index,
target_ulong address, int rw, int mmu_idx,
target_ulong *page_size)
int mmu_idx)
{
target_ulong vaddr;
- target_phys_addr_t paddr;
+ hwaddr paddr;
target_ulong page_size;
int error_code = 0, prot, access_index;
#endif /* TARGET_SPARC64 */
-static int cpu_sparc_get_phys_page(CPUSPARCState *env, target_phys_addr_t *phys,
+static int cpu_sparc_get_phys_page(CPUSPARCState *env, hwaddr *phys,
target_ulong addr, int rw, int mmu_idx)
{
target_ulong page_size;
}
#if defined(TARGET_SPARC64)
-target_phys_addr_t cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr,
+hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr,
int mmu_idx)
{
- target_phys_addr_t phys_addr;
+ hwaddr phys_addr;
if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 4, mmu_idx) != 0) {
return -1;
}
#endif
-target_phys_addr_t cpu_get_phys_page_debug(CPUSPARCState *env, target_ulong addr)
+hwaddr cpu_get_phys_page_debug(CPUSPARCState *env, target_ulong addr)
{
- target_phys_addr_t phys_addr;
+ hwaddr phys_addr;
int mmu_idx = cpu_mmu_index(env);
MemoryRegionSection section;
return ret;
}
-target_phys_addr_t cpu_get_phys_page_debug(CPUUniCore32State *env,
+hwaddr cpu_get_phys_page_debug(CPUUniCore32State *env,
target_ulong addr)
{
cpu_abort(env, "%s not supported yet\n", __func__);
}
}
-target_phys_addr_t cpu_get_phys_page_debug(CPUXtensaState *env, target_ulong addr)
+hwaddr cpu_get_phys_page_debug(CPUXtensaState *env, target_ulong addr)
{
uint32_t paddr;
uint32_t page_size;
uint32_t len = regs[5];
while (len > 0) {
- target_phys_addr_t paddr =
+ hwaddr paddr =
cpu_get_phys_page_debug(env, vaddr);
uint32_t page_left =
TARGET_PAGE_SIZE - (vaddr & (TARGET_PAGE_SIZE - 1));
uint32_t io_sz = page_left < len ? page_left : len;
- target_phys_addr_t sz = io_sz;
+ hwaddr sz = io_sz;
void *buf = cpu_physical_memory_map(paddr, &sz, is_write);
if (buf) {
uint32_t sz = regs[5];
while (sz) {
- target_phys_addr_t len = sz;
+ hwaddr len = sz;
void *buf = cpu_physical_memory_map(base, &len, 1);
if (buf && len) {
+++ /dev/null
-/* Define target_phys_addr_t if it exists. */
-
-#ifndef TARGPHYS_H
-#define TARGPHYS_H
-
-#ifndef CONFIG_USER_ONLY
-
-#define TARGET_PHYS_ADDR_BITS 64
-/* target_phys_addr_t is the type of a physical address (its size can
- be different from 'target_ulong'). */
-
-typedef uint64_t target_phys_addr_t;
-#define TARGET_PHYS_ADDR_MAX UINT64_MAX
-#define TARGET_FMT_plx "%016" PRIx64
-#define TARGET_PRIdPHYS PRId64
-#define TARGET_PRIiPHYS PRIi64
-#define TARGET_PRIoPHYS PRIo64
-#define TARGET_PRIuPHYS PRIu64
-#define TARGET_PRIxPHYS PRIx64
-#define TARGET_PRIXPHYS PRIX64
-
-#endif
-
-#endif
#define BUFFER_IO_MAX_DELAY 100
typedef struct XenPhysmap {
- target_phys_addr_t start_addr;
+ hwaddr start_addr;
ram_addr_t size;
char *name;
- target_phys_addr_t phys_offset;
+ hwaddr phys_offset;
QLIST_ENTRY(XenPhysmap) list;
} XenPhysmap;
struct xs_handle *xenstore;
MemoryListener memory_listener;
QLIST_HEAD(, XenPhysmap) physmap;
- target_phys_addr_t free_phys_offset;
+ hwaddr free_phys_offset;
const XenPhysmap *log_for_dirtybit;
Notifier exit;
}
static XenPhysmap *get_physmapping(XenIOState *state,
- target_phys_addr_t start_addr, ram_addr_t size)
+ hwaddr start_addr, ram_addr_t size)
{
XenPhysmap *physmap = NULL;
return NULL;
}
-static target_phys_addr_t xen_phys_offset_to_gaddr(target_phys_addr_t start_addr,
+static hwaddr xen_phys_offset_to_gaddr(hwaddr start_addr,
ram_addr_t size, void *opaque)
{
- target_phys_addr_t addr = start_addr & TARGET_PAGE_MASK;
+ hwaddr addr = start_addr & TARGET_PAGE_MASK;
XenIOState *xen_io_state = opaque;
XenPhysmap *physmap = NULL;
#if CONFIG_XEN_CTRL_INTERFACE_VERSION >= 340
static int xen_add_to_physmap(XenIOState *state,
- target_phys_addr_t start_addr,
+ hwaddr start_addr,
ram_addr_t size,
MemoryRegion *mr,
- target_phys_addr_t offset_within_region)
+ hwaddr offset_within_region)
{
unsigned long i = 0;
int rc = 0;
XenPhysmap *physmap = NULL;
- target_phys_addr_t pfn, start_gpfn;
- target_phys_addr_t phys_offset = memory_region_get_ram_addr(mr);
+ hwaddr pfn, start_gpfn;
+ hwaddr phys_offset = memory_region_get_ram_addr(mr);
char path[80], value[17];
if (get_physmapping(state, start_addr, size)) {
}
static int xen_remove_from_physmap(XenIOState *state,
- target_phys_addr_t start_addr,
+ hwaddr start_addr,
ram_addr_t size)
{
unsigned long i = 0;
int rc = 0;
XenPhysmap *physmap = NULL;
- target_phys_addr_t phys_offset = 0;
+ hwaddr phys_offset = 0;
physmap = get_physmapping(state, start_addr, size);
if (physmap == NULL) {
#else
static int xen_add_to_physmap(XenIOState *state,
- target_phys_addr_t start_addr,
+ hwaddr start_addr,
ram_addr_t size,
MemoryRegion *mr,
- target_phys_addr_t offset_within_region)
+ hwaddr offset_within_region)
{
return -ENOSYS;
}
static int xen_remove_from_physmap(XenIOState *state,
- target_phys_addr_t start_addr,
+ hwaddr start_addr,
ram_addr_t size)
{
return -ENOSYS;
bool add)
{
XenIOState *state = container_of(listener, XenIOState, memory_listener);
- target_phys_addr_t start_addr = section->offset_within_address_space;
+ hwaddr start_addr = section->offset_within_address_space;
ram_addr_t size = section->size;
bool log_dirty = memory_region_is_logging(section->mr);
hvmmem_type_t mem_type;
}
static void xen_sync_dirty_bitmap(XenIOState *state,
- target_phys_addr_t start_addr,
+ hwaddr start_addr,
ram_addr_t size)
{
- target_phys_addr_t npages = size >> TARGET_PAGE_BITS;
+ hwaddr npages = size >> TARGET_PAGE_BITS;
const int width = sizeof(unsigned long) * 8;
unsigned long bitmap[(npages + width - 1) / width];
int rc, i, j;
#define mapcache_unlock() ((void)0)
typedef struct MapCacheEntry {
- target_phys_addr_t paddr_index;
+ hwaddr paddr_index;
uint8_t *vaddr_base;
unsigned long *valid_mapping;
uint8_t lock;
- target_phys_addr_t size;
+ hwaddr size;
struct MapCacheEntry *next;
} MapCacheEntry;
typedef struct MapCacheRev {
uint8_t *vaddr_req;
- target_phys_addr_t paddr_index;
- target_phys_addr_t size;
+ hwaddr paddr_index;
+ hwaddr size;
QTAILQ_ENTRY(MapCacheRev) next;
} MapCacheRev;
QTAILQ_HEAD(map_cache_head, MapCacheRev) locked_entries;
/* For most cases (>99.9%), the page address is the same. */
- target_phys_addr_t last_address_index;
+ hwaddr last_address_index;
uint8_t *last_address_vaddr;
unsigned long max_mcache_size;
unsigned int mcache_bucket_shift;
}
static void xen_remap_bucket(MapCacheEntry *entry,
- target_phys_addr_t size,
- target_phys_addr_t address_index)
+ hwaddr size,
+ hwaddr address_index)
{
uint8_t *vaddr_base;
xen_pfn_t *pfns;
int *err;
unsigned int i;
- target_phys_addr_t nb_pfn = size >> XC_PAGE_SHIFT;
+ hwaddr nb_pfn = size >> XC_PAGE_SHIFT;
trace_xen_remap_bucket(address_index);
g_free(err);
}
-uint8_t *xen_map_cache(target_phys_addr_t phys_addr, target_phys_addr_t size,
+uint8_t *xen_map_cache(hwaddr phys_addr, hwaddr size,
uint8_t lock)
{
MapCacheEntry *entry, *pentry = NULL;
- target_phys_addr_t address_index;
- target_phys_addr_t address_offset;
- target_phys_addr_t __size = size;
+ hwaddr address_index;
+ hwaddr address_offset;
+ hwaddr __size = size;
bool translated = false;
tryagain:
{
MapCacheEntry *entry = NULL;
MapCacheRev *reventry;
- target_phys_addr_t paddr_index;
- target_phys_addr_t size;
+ hwaddr paddr_index;
+ hwaddr size;
int found = 0;
QTAILQ_FOREACH(reventry, &mapcache->locked_entries, next) {
{
MapCacheEntry *entry = NULL, *pentry = NULL;
MapCacheRev *reventry;
- target_phys_addr_t paddr_index;
- target_phys_addr_t size;
+ hwaddr paddr_index;
+ hwaddr size;
int found = 0;
QTAILQ_FOREACH(reventry, &mapcache->locked_entries, next) {
#include <stdlib.h>
-typedef target_phys_addr_t (*phys_offset_to_gaddr_t)(target_phys_addr_t start_addr,
+typedef hwaddr (*phys_offset_to_gaddr_t)(hwaddr start_addr,
ram_addr_t size,
void *opaque);
#ifdef CONFIG_XEN
void xen_map_cache_init(phys_offset_to_gaddr_t f,
void *opaque);
-uint8_t *xen_map_cache(target_phys_addr_t phys_addr, target_phys_addr_t size,
+uint8_t *xen_map_cache(hwaddr phys_addr, hwaddr size,
uint8_t lock);
ram_addr_t xen_ram_addr_from_mapcache(void *ptr);
void xen_invalidate_map_cache_entry(uint8_t *buffer);
{
}
-static inline uint8_t *xen_map_cache(target_phys_addr_t phys_addr,
- target_phys_addr_t size,
+static inline uint8_t *xen_map_cache(hwaddr phys_addr,
+ hwaddr size,
uint8_t lock)
{
abort();
projects / sdk / emulator / qemu.git / commitdiff