2014-05-23 Yvan Roux <yvan.roux@linaro.org>

       Backport from trunk r209711.
       2014-04-23  Richard Earnshaw  <rearnsha@arm.com>

       * aarch64.md (<optab>_rol<mode>3): New pattern.
       (<optab>_rolsi3_uxtw): Likewise.
       * aarch64.c (aarch64_strip_shift): Handle ROTATE and ROTATERT.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211524 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog.linaro b/gcc/ChangeLog.linaro
index 74c730d..db6e29b 100644 (file)
--- a/gcc/ChangeLog.linaro
+++ b/gcc/ChangeLog.linaro
@@ -1,5 +1,14 @@
 2014-05-23  Yvan Roux  <yvan.roux@linaro.org>
 
+       Backport from trunk r209711.
+       2014-04-23  Richard Earnshaw  <rearnsha@arm.com>
+
+       * aarch64.md (<optab>_rol<mode>3): New pattern.
+       (<optab>_rolsi3_uxtw): Likewise.
+       * aarch64.c (aarch64_strip_shift): Handle ROTATE and ROTATERT.
+
+2014-05-23  Yvan Roux  <yvan.roux@linaro.org>
+
        Backport from trunk r209710.
        2014-04-23  James Greenhalgh  <james.greenhalgh@arm.com>
 

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 277c087..496d1b8 100644 (file)
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -4471,9 +4471,13 @@ aarch64_strip_shift (rtx x)
 {
   rtx op = x;
 
+  /* We accept both ROTATERT and ROTATE: since the RHS must be a constant
+     we can convert both to ROR during final output.  */
   if ((GET_CODE (op) == ASHIFT
        || GET_CODE (op) == ASHIFTRT
-       || GET_CODE (op) == LSHIFTRT)
+       || GET_CODE (op) == LSHIFTRT
+       || GET_CODE (op) == ROTATERT
+       || GET_CODE (op) == ROTATE)
       && CONST_INT_P (XEXP (op, 1)))
     return XEXP (op, 0);
 

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index f81959d..073d3ad 100644 (file)
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -2584,7 +2584,18 @@
   [(set_attr "type" "logic_shift_imm")]
 )
 
-;; zero_extend version of above
+(define_insn "*<optab>_rol<mode>3"
+  [(set (match_operand:GPI 0 "register_operand" "=r")
+       (LOGICAL:GPI (rotate:GPI
+                     (match_operand:GPI 1 "register_operand" "r")
+                     (match_operand:QI 2 "aarch64_shift_imm_<mode>" "n"))
+                    (match_operand:GPI 3 "register_operand" "r")))]
+  ""
+  "<logical>\\t%<w>0, %<w>3, %<w>1, ror (<sizen> - %2)"
+  [(set_attr "type" "logic_shift_imm")]
+)
+
+;; zero_extend versions of above
 (define_insn "*<LOGICAL:optab>_<SHIFT:optab>si3_uxtw"
   [(set (match_operand:DI 0 "register_operand" "=r")
        (zero_extend:DI
@@ -2597,6 +2608,18 @@
   [(set_attr "type" "logic_shift_imm")]
 )
 
+(define_insn "*<optab>_rolsi3_uxtw"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+       (zero_extend:DI
+        (LOGICAL:SI (rotate:SI
+                     (match_operand:SI 1 "register_operand" "r")
+                     (match_operand:QI 2 "aarch64_shift_imm_si" "n"))
+                    (match_operand:SI 3 "register_operand" "r"))))]
+  ""
+  "<logical>\\t%w0, %w3, %w1, ror (32 - %2)"
+  [(set_attr "type" "logic_shift_imm")]
+)
+
 (define_insn "one_cmpl<mode>2"
   [(set (match_operand:GPI 0 "register_operand" "=r")
        (not:GPI (match_operand:GPI 1 "register_operand" "r")))]