drm/amd/display: Reset inbox rptr/wptr when resetting DMCUB

[Why]
These logically make sense more to be set after the DMCUB has been
reset rather than when we setup the inbox.

[How]
Move them into the reset callback.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
index 9229012..b2ca8e0 100644 (file)
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
@@ -80,6 +80,8 @@ void dmub_dcn20_reset(struct dmub_srv *dmub)
        REG_UPDATE(DMCUB_CNTL, DMCUB_SOFT_RESET, 1);
        REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);
        REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1);
+       REG_WRITE(DMCUB_INBOX1_RPTR, 0);
+       REG_WRITE(DMCUB_INBOX1_WPTR, 0);
 }
 
 void dmub_dcn20_reset_release(struct dmub_srv *dmub)
@@ -190,8 +192,6 @@ void dmub_dcn20_setup_mailbox(struct dmub_srv *dmub,
 
        REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, 0x80000000);
        REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base);
-       REG_WRITE(DMCUB_INBOX1_RPTR, 0);
-       REG_WRITE(DMCUB_INBOX1_WPTR, 0);
 }
 
 uint32_t dmub_dcn20_get_inbox1_rptr(struct dmub_srv *dmub)