/// require that a property be set.
class MachineFunctionProperties {
// TODO: Add MachineVerifier checks for AllVRegsAllocated
- // TODO: Add a way to print the properties and make more useful error messages
// Possible TODO: Allow targets to extend this (perhaps by allowing the
// constructor to specify the size of the bit vector)
// Possible TODO: Allow requiring the negative (e.g. VRegsAllocated could be
return !V.Properties.test(Properties);
}
- // Print the MachineFunctionProperties in human-readable form. If OnlySet is
- // true, only print the properties that are set.
- void print(raw_ostream &ROS, bool OnlySet=false) const;
+ /// Print the MachineFunctionProperties in human-readable form.
+ void print(raw_ostream &OS) const;
private:
BitVector Properties =
void MachineFunctionInitializer::anchor() {}
-void MachineFunctionProperties::print(raw_ostream &ROS, bool OnlySet) const {
- // Leave this function even in NDEBUG as an out-of-line anchor.
-#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
- bool NeedsComma = false;
- for (BitVector::size_type i = 0; i < Properties.size(); ++i) {
- bool HasProperty = Properties[i];
- if (OnlySet && !HasProperty)
+static const char *getPropertyName(MachineFunctionProperties::Property Prop) {
+ typedef MachineFunctionProperties::Property P;
+ switch(Prop) {
+ case P::AllVRegsAllocated: return "AllVRegsAllocated";
+ case P::IsSSA: return "IsSSA";
+ case P::Legalized: return "Legalized";
+ case P::RegBankSelected: return "RegBankSelected";
+ case P::Selected: return "Selected";
+ case P::TracksLiveness: return "TracksLiveness";
+ }
+}
+
+void MachineFunctionProperties::print(raw_ostream &OS) const {
+ const char *Separator = "";
+ for (BitVector::size_type I = 0; I < Properties.size(); ++I) {
+ if (!Properties[I])
continue;
- if (NeedsComma)
- ROS << ", ";
- else
- NeedsComma = true;
- switch(static_cast<Property>(i)) {
- case Property::IsSSA:
- ROS << (HasProperty ? "SSA" : "Post SSA");
- break;
- case Property::TracksLiveness:
- ROS << (HasProperty ? "" : "not ") << "tracking liveness";
- break;
- case Property::AllVRegsAllocated:
- ROS << (HasProperty ? "AllVRegsAllocated" : "HasVRegs");
- break;
- case Property::Legalized:
- ROS << (HasProperty ? "" : "not ") << "legalized";
- break;
- case Property::RegBankSelected:
- ROS << (HasProperty ? "" : "not ") << "RegBank-selected";
- break;
- case Property::Selected:
- ROS << (HasProperty ? "" : "not ") << "selected";
- break;
- }
+ OS << Separator << getPropertyName(static_cast<Property>(I));
+ Separator = ", ";
}
-#endif
}
//===----------------------------------------------------------------------===//
void MachineFunction::print(raw_ostream &OS, const SlotIndexes *Indexes) const {
OS << "# Machine code for function " << getName() << ": ";
- OS << "Properties: <";
getProperties().print(OS);
- OS << ">\n";
// Print Frame Information
FrameInfo->print(*this, OS);