intel/vec4/ra: Define REG_CLASS_COUNT constant specifying the number of register...

Rework:
 * Jordan: 16=>20 following d33aff783d9 ("intel/fs: add support for
   sparse accesses")

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>

diff --git a/src/intel/compiler/brw_vec4_reg_allocate.cpp b/src/intel/compiler/brw_vec4_reg_allocate.cpp
index 7aaacd0..c30c685 100644 (file)
--- a/src/intel/compiler/brw_vec4_reg_allocate.cpp
+++ b/src/intel/compiler/brw_vec4_reg_allocate.cpp
@@ -27,6 +27,8 @@
 
 using namespace brw;
 
+#define REG_CLASS_COUNT 20
+
 namespace brw {
 
 static void
@@ -100,10 +102,10 @@ brw_vec4_alloc_reg_set(struct brw_compiler *compiler)
     * SEND-from-GRF sources cannot be split, so we also need classes for each
     * potential message length.
     */
-   const int class_count = MAX_VGRF_SIZE;
-   int class_sizes[MAX_VGRF_SIZE];
+   assert(REG_CLASS_COUNT == MAX_VGRF_SIZE);
+   int class_sizes[REG_CLASS_COUNT];
 
-   for (int i = 0; i < class_count; i++)
+   for (int i = 0; i < REG_CLASS_COUNT; i++)
       class_sizes[i] = i + 1;
 
 
@@ -112,12 +114,12 @@ brw_vec4_alloc_reg_set(struct brw_compiler *compiler)
    if (compiler->devinfo->ver >= 6)
       ra_set_allocate_round_robin(compiler->vec4_reg_set.regs);
    ralloc_free(compiler->vec4_reg_set.classes);
-   compiler->vec4_reg_set.classes = ralloc_array(compiler, struct ra_class *, class_count);
+   compiler->vec4_reg_set.classes = ralloc_array(compiler, struct ra_class *, REG_CLASS_COUNT);
 
    /* Now, add the registers to their classes, and add the conflicts
     * between them and the base GRF registers (and also each other).
     */
-   for (int i = 0; i < class_count; i++) {
+   for (int i = 0; i < REG_CLASS_COUNT; i++) {
       int class_reg_count = base_reg_count - (class_sizes[i] - 1);
       compiler->vec4_reg_set.classes[i] =
          ra_alloc_contig_reg_class(compiler->vec4_reg_set.regs, class_sizes[i]);