emmc: backward compatible with all HS400 clock sources [1/1]

PD#SWPL-6294

Problem:
TL1 and G12B uses clkin3,TXLX uses clkin2

Solution:
unifying the HS400 source clock name in DTS

Verify:
TL1-T962X2_X301 G12B-Reva G12B-Revb

Change-Id: I7acaf7b4392d757955f43a0b17ac1fad84f53d26
Signed-off-by: Long Yu <long.yu@amlogic.com>

diff --git a/arch/arm/boot/dts/amlogic/mesong12b.dtsi b/arch/arm/boot/dts/amlogic/mesong12b.dtsi
index 1b80185..87a5e1b 100644 (file)
--- a/arch/arm/boot/dts/amlogic/mesong12b.dtsi
+++ b/arch/arm/boot/dts/amlogic/mesong12b.dtsi
@@ -1445,10 +1445,9 @@
                clocks = <&clkc CLKID_SD_EMMC_C>,
                           <&clkc CLKID_SD_EMMC_C_P0_COMP>,
                           <&clkc CLKID_FCLK_DIV2>,
-                          <&clkc CLKID_FCLK_DIV5>,
                           <&clkc CLKID_FCLK_DIV2P5>,
                           <&xtal>;
-               clock-names = "core","clkin0","clkin1","clkin2","clkin3","xtal";
+               clock-names = "core","clkin0","clkin1","clkin2","xtal";
 
                bus-width = <8>;
                cap-sd-highspeed;

diff --git a/arch/arm/boot/dts/amlogic/mesontl1.dtsi b/arch/arm/boot/dts/amlogic/mesontl1.dtsi
index 38d98da..5dfddea 100644 (file)
--- a/arch/arm/boot/dts/amlogic/mesontl1.dtsi
+++ b/arch/arm/boot/dts/amlogic/mesontl1.dtsi
@@ -1139,10 +1139,9 @@
                clocks = <&clkc CLKID_SD_EMMC_C>,
                           <&clkc CLKID_SD_EMMC_C_P0_COMP>,
                           <&clkc CLKID_FCLK_DIV2>,
-                          <&clkc CLKID_FCLK_DIV5>,
                           <&clkc CLKID_GP0_PLL>,
                           <&xtal>;
-               clock-names = "core","clkin0","clkin1","clkin2","clkin3","xtal";
+               clock-names = "core","clkin0","clkin1","clkin2","xtal";
 
                bus-width = <8>;
                cap-sd-highspeed;

diff --git a/arch/arm64/boot/dts/amlogic/mesong12b.dtsi b/arch/arm64/boot/dts/amlogic/mesong12b.dtsi
index a979075..70fa31e 100644 (file)
--- a/arch/arm64/boot/dts/amlogic/mesong12b.dtsi
+++ b/arch/arm64/boot/dts/amlogic/mesong12b.dtsi
@@ -1445,10 +1445,9 @@
                clocks = <&clkc CLKID_SD_EMMC_C>,
                           <&clkc CLKID_SD_EMMC_C_P0_COMP>,
                           <&clkc CLKID_FCLK_DIV2>,
-                          <&clkc CLKID_FCLK_DIV5>,
                           <&clkc CLKID_FCLK_DIV2P5>,
                           <&xtal>;
-               clock-names = "core","clkin0","clkin1","clkin2","clkin3","xtal";
+               clock-names = "core","clkin0","clkin1","clkin2","xtal";
 
                bus-width = <8>;
                cap-sd-highspeed;

diff --git a/arch/arm64/boot/dts/amlogic/mesontl1.dtsi b/arch/arm64/boot/dts/amlogic/mesontl1.dtsi
index f7a4c8d..88cb7f6 100644 (file)
--- a/arch/arm64/boot/dts/amlogic/mesontl1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/mesontl1.dtsi
@@ -1120,10 +1120,9 @@
                clocks = <&clkc CLKID_SD_EMMC_C>,
                           <&clkc CLKID_SD_EMMC_C_P0_COMP>,
                           <&clkc CLKID_FCLK_DIV2>,
-                          <&clkc CLKID_FCLK_DIV5>,
                           <&clkc CLKID_GP0_PLL>,
                           <&xtal>;
-               clock-names = "core","clkin0","clkin1","clkin2","clkin3","xtal";
+               clock-names = "core","clkin0","clkin1","clkin2","xtal";
 
                bus-width = <8>;
                cap-sd-highspeed;

diff --git a/drivers/amlogic/mmc/aml_sd_emmc_v3.c b/drivers/amlogic/mmc/aml_sd_emmc_v3.c
index 08559f0..24b5aa7 100644 (file)
--- a/drivers/amlogic/mmc/aml_sd_emmc_v3.c
+++ b/drivers/amlogic/mmc/aml_sd_emmc_v3.c
@@ -231,10 +231,9 @@ static int meson_mmc_clk_set_rate_v3(struct mmc_host *mmc,
 
        if (aml_card_type_mmc(pdata)) {
                if ((clk_ios >= 200000000) && conf->ddr) {
-                       if (host->data->chip_type == MMC_CHIP_G12B)
-                               src0_clk = devm_clk_get(host->dev, "clkin3");
-                       else
-                               src0_clk = devm_clk_get(host->dev, "clkin2");
+                       src0_clk = devm_clk_get(host->dev, "clkin2");
+                       if (ret)
+                               pr_warn("not get clkin2\n");
                        ret = clk_set_parent(host->mux_parent[0], src0_clk);
                        if (ret)
                                pr_warn("set src0 as comp0 parent error\n");
@@ -245,16 +244,17 @@ static int meson_mmc_clk_set_rate_v3(struct mmc_host *mmc,
                } else if (((host->data->chip_type == MMC_CHIP_TL1)
                                || (host->data->chip_type == MMC_CHIP_G12B))
                                && (clk_ios >= 166000000)) {
-                       src0_clk = devm_clk_get(host->dev, "clkin3");
+                       src0_clk = devm_clk_get(host->dev, "clkin2");
                        if (ret)
-                               pr_warn("not get clkin3\n");
-                       if (host->data->chip_type == MMC_CHIP_TL1) {
+                               pr_warn("not get clkin2\n");
+                       if ((host->data->chip_type == MMC_CHIP_TL1)
+                               && (clk_ios <= 198000000)) {
                                ret = clk_set_rate(src0_clk, 792000000);
                                if (ret)
-                                       pr_warn("not set tl1-792\n");
+                                       pr_warn("not set tl1-gp0\n");
                        }
-                       pr_warn("set rate clkin3>>>>>>>>clk:%lu\n",
-                                       clk_get_rate(src0_clk));
+                       pr_warn("set rate clkin2>>>>>>>>clk:%lu\n",
+                                               clk_get_rate(src0_clk));
                        ret = clk_set_parent(host->mux_parent[0],
                                        src0_clk);
                        if (ret)