arm: rmobile: Move sh-i2c of the address defined to common header
authorNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Thu, 6 Nov 2014 07:03:47 +0000 (16:03 +0900)
committerNobuhiro Iwamatsu <iwamatsu@nigauri.org>
Mon, 10 Nov 2014 00:46:47 +0000 (09:46 +0900)
R-Car SoCs of rmobile have same IP of sh-i2c, and have same address.
This moves sh-i2c of the address defined to rcar-base.h as common header of
R-Car SoCs, and headers of each SoCs.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
arch/arm/include/asm/arch-rmobile/r8a7790.h
arch/arm/include/asm/arch-rmobile/r8a7791.h
arch/arm/include/asm/arch-rmobile/r8a7793.h
arch/arm/include/asm/arch-rmobile/r8a7794.h
arch/arm/include/asm/arch-rmobile/rcar-base.h
include/configs/alt.h
include/configs/gose.h
include/configs/koelsch.h

index 6ef665d..de14869 100644 (file)
 
 #include "rcar-base.h"
 
+/* SH-I2C */
+#define CONFIG_SYS_I2C_SH_BASE2        0xE6520000
+#define CONFIG_SYS_I2C_SH_BASE3        0xE60B0000
+
 #define R8A7790_CUT_ES2X       2
 #define IS_R8A7790_ES2()       \
        (rmobile_get_cpu_rev_integer() == R8A7790_CUT_ES2X)
index 592c524..26a0bd5 100644 (file)
 /*
  * R-Car (R8A7791) I/O Addresses
  */
+
+/* SH-I2C */
+#define CONFIG_SYS_I2C_SH_BASE2        0xE60B0000
+
 #define DBSC3_1_QOS_R0_BASE    0xE67A1000
 #define DBSC3_1_QOS_R1_BASE    0xE67A1100
 #define DBSC3_1_QOS_R2_BASE    0xE67A1200
index 801eaba..778812e 100644 (file)
 /*
  * R8A7793 I/O Addresses
  */
+
+/* SH-I2C */
+#define CONFIG_SYS_I2C_SH_BASE2        0xE60B0000
+
 #define DBSC3_1_QOS_R0_BASE    0xE67A1000
 #define DBSC3_1_QOS_R1_BASE    0xE67A1100
 #define DBSC3_1_QOS_R2_BASE    0xE67A1200
index 94276dd..66d5a29 100644 (file)
@@ -11,4 +11,7 @@
 
 #include "rcar-base.h"
 
+/* SH-I2C */
+#define CONFIG_SYS_I2C_SH_BASE2        0xE60B0000
+
 #endif /* __ASM_ARCH_R8A7794_H */
index 2c6e50c..7babc4e 100644 (file)
 #define SCIF4_BASE             0xE6EE0000
 #define SCIF5_BASE             0xE6EE8000
 
+/*
+ * SH-I2C
+ * Ch2 and ch3 are different address. These are defined
+ * in the header of each SoCs.
+ */
+#define CONFIG_SYS_I2C_SH_BASE0        0xE6500000
+#define CONFIG_SYS_I2C_SH_BASE1        0xE6510000
+
 #define S3C_BASE               0xE6784000
 #define S3C_INT_BASE           0xE6784A00
 #define S3C_MEDIA_BASE         0xE6784B00
index c0b403c..3f6737c 100644 (file)
 #define CONFIG_SYS_I2C_SH
 #define CONFIG_SYS_I2C_SLAVE           0x7F
 #define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS       3
-#define CONFIG_SYS_I2C_SH_BASE0                0xE6500000
 #define CONFIG_SYS_I2C_SH_SPEED0       400000
-#define CONFIG_SYS_I2C_SH_BASE1                0xE6510000
 #define CONFIG_SYS_I2C_SH_SPEED1       400000
-#define CONFIG_SYS_I2C_SH_BASE2                0xE60B0000
 #define CONFIG_SYS_I2C_SH_SPEED2       400000
 #define CONFIG_SH_I2C_DATA_HIGH                4
 #define CONFIG_SH_I2C_DATA_LOW         5
index 62837d6..974df5a 100644 (file)
 #define CONFIG_SYS_I2C_SH
 #define CONFIG_SYS_I2C_SLAVE   0x7F
 #define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS      3
-#define CONFIG_SYS_I2C_SH_BASE0                0xE6500000
 #define CONFIG_SYS_I2C_SH_SPEED0       400000
-#define CONFIG_SYS_I2C_SH_BASE1                0xE6510000
 #define CONFIG_SYS_I2C_SH_SPEED1       400000
-#define CONFIG_SYS_I2C_SH_BASE2                0xE60B0000
 #define CONFIG_SYS_I2C_SH_SPEED2       400000
 #define CONFIG_SH_I2C_DATA_HIGH        4
 #define CONFIG_SH_I2C_DATA_LOW 5
index 27ef283..f8294e9 100644 (file)
 #define CONFIG_SYS_I2C_SH
 #define CONFIG_SYS_I2C_SLAVE   0x7F
 #define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS      3
-#define CONFIG_SYS_I2C_SH_BASE0                0xE6500000
 #define CONFIG_SYS_I2C_SH_SPEED0       400000
-#define CONFIG_SYS_I2C_SH_BASE1                0xE6510000
 #define CONFIG_SYS_I2C_SH_SPEED1       400000
-#define CONFIG_SYS_I2C_SH_BASE2                0xE60B0000
 #define CONFIG_SYS_I2C_SH_SPEED2       400000
 #define CONFIG_SH_I2C_DATA_HIGH        4
 #define CONFIG_SH_I2C_DATA_LOW 5