fix: unknown CSR 'mhcr' (arch/riscv/cpu/c9xx/cpu.c)

Signed-off-by: Han Gao <gaohan@iscas.ac.cn>

diff --git a/arch/riscv/cpu/c9xx/cpu.c b/arch/riscv/cpu/c9xx/cpu.c
index ba370cfbdb80996739fe8815757fadc09ceb2e4e..8cb403ab91b55724219bba809bb5273e44caae38 100644 (file)
--- a/arch/riscv/cpu/c9xx/cpu.c
+++ b/arch/riscv/cpu/c9xx/cpu.c
@@ -125,10 +125,11 @@ void icache_enable(void)
 #ifdef CONFIG_SPL_BUILD
 #ifdef CONFIG_SPL_RISCV_MMODE
 #ifdef CONFIG_TARGET_LIGHT_C910
+// mhcr is 0x7c1
        asm volatile (
-        "csrr x29, mhcr\n\t"
+        "csrr x29, 0x7c1\n\t"
         "ori x28, x29, 0x1\n\t"
-        "csrw mhcr, x28\n\t"
+        "csrw 0x7c1, x28\n\t"
     );
 #endif
 #endif
@@ -142,7 +143,7 @@ void dcache_enable(void)
 #ifdef CONFIG_TARGET_LIGHT_C910
        asm volatile (
         "li x29, 0x11ff\n\t"
-        "csrw mhcr, x29\n\t"
+        "csrw 0x7c1, x29\n\t"
     );
 #endif
 #endif