unsigned MipsTargetInfo::getISARev() const {
return llvm::StringSwitch<unsigned>(getCPU())
.Cases("mips32", "mips64", 1)
- .Cases("mips32r2", "mips64r2", "octeon", 2)
+ .Cases("mips32r2", "mips64r2", "octeon", "octeon+", 2)
.Cases("mips32r3", "mips64r3", 3)
.Cases("mips32r5", "mips64r5", 5)
.Cases("mips32r6", "mips64r6", 6)
Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
- Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
+ if (CPU == "octeon+")
+ Builder.defineMacro("_MIPS_ARCH_OCTEONP");
+ else
+ Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
if (StringRef(CPU).startswith("octeon"))
Builder.defineMacro("__OCTEON__");
// MIPS-ARCH-OCTEON:#define __OCTEON__ 1
// MIPS-ARCH-OCTEON:#define __mips_isa_rev 2
//
+// RUN: %clang_cc1 -E -dM -ffreestanding -triple=mips64-none-none \
+// RUN: -target-cpu octeon+ < /dev/null \
+// RUN: | FileCheck -match-full-lines -check-prefix MIPS-ARCH-OCTEONP %s
+//
+// MIPS-ARCH-OCTEONP:#define _MIPS_ARCH "octeon+"
+// MIPS-ARCH-OCTEONP:#define _MIPS_ARCH_OCTEONP 1
+// MIPS-ARCH-OCTEONP:#define _MIPS_ISA _MIPS_ISA_MIPS64
+// MIPS-ARCH-OCTEONP:#define __OCTEON__ 1
+// MIPS-ARCH-OCTEONP:#define __mips_isa_rev 2
+//
// Check MIPS float ABI macros
//
// RUN: %clang_cc1 -E -dM -ffreestanding \