net: dsa: mv88e6xxx: add support for GPIO configuration

MV88E6352 and later switches support GPIO control through the "Scratch
& Misc" global2 register. (Older switches do too, though with a slightly
different register interface. Only the 6352-style is implemented here.)

Add a new file, global2_scratch.c, for operations in the Scratch & Misc
space. Additionally, add a GPIO operations structure to present an
abstract view over GPIO manipulation.

Reverse Christmas tree and unsigned has been replaced with unsigned
int by Andrew Lunn.

Signed-off-by: Brandon Streiff <brandon.streiff@ni.com>
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/dsa/mv88e6xxx/Makefile b/drivers/net/dsa/mv88e6xxx/Makefile
index 40a423c..0cd0e2b 100644 (file)
--- a/drivers/net/dsa/mv88e6xxx/Makefile
+++ b/drivers/net/dsa/mv88e6xxx/Makefile
@@ -6,6 +6,7 @@ mv88e6xxx-objs += global1_atu.o
 mv88e6xxx-objs += global1_vtu.o
 mv88e6xxx-$(CONFIG_NET_DSA_MV88E6XXX_GLOBAL2) += global2.o
 mv88e6xxx-$(CONFIG_NET_DSA_MV88E6XXX_GLOBAL2) += global2_avb.o
+mv88e6xxx-$(CONFIG_NET_DSA_MV88E6XXX_GLOBAL2) += global2_scratch.o
 mv88e6xxx-objs += phy.o
 mv88e6xxx-objs += port.o
 mv88e6xxx-$(CONFIG_NET_DSA_MV88E6XXX_PTP) += ptp.o

diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
index a795efd..41e28e2 100644 (file)
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -2480,6 +2480,7 @@ static const struct mv88e6xxx_ops mv88e6141_ops = {
        .reset = mv88e6352_g1_reset,
        .vtu_getnext = mv88e6352_g1_vtu_getnext,
        .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
+       .gpio_ops = &mv88e6352_gpio_ops,
 };
 
 static const struct mv88e6xxx_ops mv88e6161_ops = {
@@ -2610,6 +2611,7 @@ static const struct mv88e6xxx_ops mv88e6172_ops = {
        .vtu_getnext = mv88e6352_g1_vtu_getnext,
        .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
        .serdes_power = mv88e6352_serdes_power,
+       .gpio_ops = &mv88e6352_gpio_ops,
 };
 
 static const struct mv88e6xxx_ops mv88e6175_ops = {
@@ -2681,6 +2683,7 @@ static const struct mv88e6xxx_ops mv88e6176_ops = {
        .vtu_getnext = mv88e6352_g1_vtu_getnext,
        .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
        .serdes_power = mv88e6352_serdes_power,
+       .gpio_ops = &mv88e6352_gpio_ops,
 };
 
 static const struct mv88e6xxx_ops mv88e6185_ops = {
@@ -2744,6 +2747,7 @@ static const struct mv88e6xxx_ops mv88e6190_ops = {
        .vtu_getnext = mv88e6390_g1_vtu_getnext,
        .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
        .serdes_power = mv88e6390_serdes_power,
+       .gpio_ops = &mv88e6352_gpio_ops,
 };
 
 static const struct mv88e6xxx_ops mv88e6190x_ops = {
@@ -2779,6 +2783,7 @@ static const struct mv88e6xxx_ops mv88e6190x_ops = {
        .vtu_getnext = mv88e6390_g1_vtu_getnext,
        .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
        .serdes_power = mv88e6390_serdes_power,
+       .gpio_ops = &mv88e6352_gpio_ops,
 };
 
 static const struct mv88e6xxx_ops mv88e6191_ops = {
@@ -2851,6 +2856,7 @@ static const struct mv88e6xxx_ops mv88e6240_ops = {
        .vtu_getnext = mv88e6352_g1_vtu_getnext,
        .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
        .serdes_power = mv88e6352_serdes_power,
+       .gpio_ops = &mv88e6352_gpio_ops,
        .avb_ops = &mv88e6352_avb_ops,
 };
 
@@ -2888,6 +2894,7 @@ static const struct mv88e6xxx_ops mv88e6290_ops = {
        .vtu_getnext = mv88e6390_g1_vtu_getnext,
        .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
        .serdes_power = mv88e6390_serdes_power,
+       .gpio_ops = &mv88e6352_gpio_ops,
        .avb_ops = &mv88e6390_avb_ops,
 };
 
@@ -2923,6 +2930,7 @@ static const struct mv88e6xxx_ops mv88e6320_ops = {
        .reset = mv88e6352_g1_reset,
        .vtu_getnext = mv88e6185_g1_vtu_getnext,
        .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
+       .gpio_ops = &mv88e6352_gpio_ops,
        .avb_ops = &mv88e6352_avb_ops,
 };
 
@@ -2956,6 +2964,7 @@ static const struct mv88e6xxx_ops mv88e6321_ops = {
        .reset = mv88e6352_g1_reset,
        .vtu_getnext = mv88e6185_g1_vtu_getnext,
        .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
+       .gpio_ops = &mv88e6352_gpio_ops,
        .avb_ops = &mv88e6352_avb_ops,
 };
 
@@ -2993,6 +3002,7 @@ static const struct mv88e6xxx_ops mv88e6341_ops = {
        .reset = mv88e6352_g1_reset,
        .vtu_getnext = mv88e6352_g1_vtu_getnext,
        .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
+       .gpio_ops = &mv88e6352_gpio_ops,
        .avb_ops = &mv88e6390_avb_ops,
 };
 
@@ -3100,6 +3110,7 @@ static const struct mv88e6xxx_ops mv88e6352_ops = {
        .vtu_getnext = mv88e6352_g1_vtu_getnext,
        .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
        .serdes_power = mv88e6352_serdes_power,
+       .gpio_ops = &mv88e6352_gpio_ops,
        .avb_ops = &mv88e6352_avb_ops,
 };
 
@@ -3139,6 +3150,7 @@ static const struct mv88e6xxx_ops mv88e6390_ops = {
        .vtu_getnext = mv88e6390_g1_vtu_getnext,
        .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
        .serdes_power = mv88e6390_serdes_power,
+       .gpio_ops = &mv88e6352_gpio_ops,
        .avb_ops = &mv88e6390_avb_ops,
 };
 
@@ -3178,6 +3190,7 @@ static const struct mv88e6xxx_ops mv88e6390x_ops = {
        .vtu_getnext = mv88e6390_g1_vtu_getnext,
        .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
        .serdes_power = mv88e6390_serdes_power,
+       .gpio_ops = &mv88e6352_gpio_ops,
        .avb_ops = &mv88e6390_avb_ops,
 };
 
@@ -3284,6 +3297,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
                .name = "Marvell 88E6341",
                .num_databases = 4096,
                .num_ports = 6,
+               .num_gpio = 11,
                .max_vid = 4095,
                .port_base_addr = 0x10,
                .global1_addr = 0x1b,
@@ -3363,6 +3377,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
                .name = "Marvell 88E6172",
                .num_databases = 4096,
                .num_ports = 7,
+               .num_gpio = 15,
                .max_vid = 4095,
                .port_base_addr = 0x10,
                .global1_addr = 0x1b,
@@ -3403,6 +3418,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
                .name = "Marvell 88E6176",
                .num_databases = 4096,
                .num_ports = 7,
+               .num_gpio = 15,
                .max_vid = 4095,
                .port_base_addr = 0x10,
                .global1_addr = 0x1b,
@@ -3441,6 +3457,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
                .name = "Marvell 88E6190",
                .num_databases = 4096,
                .num_ports = 11,        /* 10 + Z80 */
+               .num_gpio = 16,
                .max_vid = 8191,
                .port_base_addr = 0x0,
                .global1_addr = 0x1b,
@@ -3461,6 +3478,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
                .name = "Marvell 88E6190X",
                .num_databases = 4096,
                .num_ports = 11,        /* 10 + Z80 */
+               .num_gpio = 16,
                .max_vid = 8191,
                .port_base_addr = 0x0,
                .global1_addr = 0x1b,
@@ -3502,6 +3520,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
                .name = "Marvell 88E6240",
                .num_databases = 4096,
                .num_ports = 7,
+               .num_gpio = 15,
                .max_vid = 4095,
                .port_base_addr = 0x10,
                .global1_addr = 0x1b,
@@ -3523,6 +3542,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
                .name = "Marvell 88E6290",
                .num_databases = 4096,
                .num_ports = 11,        /* 10 + Z80 */
+               .num_gpio = 16,
                .max_vid = 8191,
                .port_base_addr = 0x0,
                .global1_addr = 0x1b,
@@ -3544,6 +3564,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
                .name = "Marvell 88E6320",
                .num_databases = 4096,
                .num_ports = 7,
+               .num_gpio = 15,
                .max_vid = 4095,
                .port_base_addr = 0x10,
                .global1_addr = 0x1b,
@@ -3564,6 +3585,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
                .name = "Marvell 88E6321",
                .num_databases = 4096,
                .num_ports = 7,
+               .num_gpio = 15,
                .max_vid = 4095,
                .port_base_addr = 0x10,
                .global1_addr = 0x1b,
@@ -3583,6 +3605,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
                .name = "Marvell 88E6341",
                .num_databases = 4096,
                .num_ports = 6,
+               .num_gpio = 11,
                .max_vid = 4095,
                .port_base_addr = 0x10,
                .global1_addr = 0x1b,
@@ -3643,6 +3666,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
                .name = "Marvell 88E6352",
                .num_databases = 4096,
                .num_ports = 7,
+               .num_gpio = 15,
                .max_vid = 4095,
                .port_base_addr = 0x10,
                .global1_addr = 0x1b,
@@ -3663,6 +3687,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
                .name = "Marvell 88E6390",
                .num_databases = 4096,
                .num_ports = 11,        /* 10 + Z80 */
+               .num_gpio = 16,
                .max_vid = 8191,
                .port_base_addr = 0x0,
                .global1_addr = 0x1b,
@@ -3683,6 +3708,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
                .name = "Marvell 88E6390X",
                .num_databases = 4096,
                .num_ports = 11,        /* 10 + Z80 */
+               .num_gpio = 16,
                .max_vid = 8191,
                .port_base_addr = 0x0,
                .global1_addr = 0x1b,

diff --git a/drivers/net/dsa/mv88e6xxx/chip.h b/drivers/net/dsa/mv88e6xxx/chip.h
index 92e5fd6..5bfa1ae 100644 (file)
--- a/drivers/net/dsa/mv88e6xxx/chip.h
+++ b/drivers/net/dsa/mv88e6xxx/chip.h
@@ -41,6 +41,8 @@
 #define MV88E6XXX_MAX_PVT_SWITCHES     32
 #define MV88E6XXX_MAX_PVT_PORTS                16
 
+#define MV88E6XXX_MAX_GPIO     16
+
 enum mv88e6xxx_egress_mode {
        MV88E6XXX_EGRESS_MODE_UNMODIFIED,
        MV88E6XXX_EGRESS_MODE_UNTAGGED,
@@ -107,6 +109,7 @@ struct mv88e6xxx_info {
        const char *name;
        unsigned int num_databases;
        unsigned int num_ports;
+       unsigned int num_gpio;
        unsigned int max_vid;
        unsigned int port_base_addr;
        unsigned int global1_addr;
@@ -151,6 +154,7 @@ struct mv88e6xxx_vtu_entry {
 
 struct mv88e6xxx_bus_ops;
 struct mv88e6xxx_irq_ops;
+struct mv88e6xxx_gpio_ops;
 struct mv88e6xxx_avb_ops;
 
 struct mv88e6xxx_irq {
@@ -216,6 +220,9 @@ struct mv88e6xxx_chip {
        int atu_prob_irq;
        int vtu_prob_irq;
 
+       /* GPIO resources */
+       u8 gpio_data[2];
+
        /* This cyclecounter abstracts the switch PTP time.
         * reg_lock must be held for any operation that read()s.
         */
@@ -361,6 +368,9 @@ struct mv88e6xxx_ops {
        int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip,
                             struct mv88e6xxx_vtu_entry *entry);
 
+       /* GPIO operations */
+       const struct mv88e6xxx_gpio_ops *gpio_ops;
+
        /* Interface to the AVB/PTP registers */
        const struct mv88e6xxx_avb_ops *avb_ops;
 };
@@ -374,6 +384,24 @@ struct mv88e6xxx_irq_ops {
        void (*irq_free)(struct mv88e6xxx_chip *chip);
 };
 
+struct mv88e6xxx_gpio_ops {
+       /* Get/set data on GPIO pin */
+       int (*get_data)(struct mv88e6xxx_chip *chip, unsigned int pin);
+       int (*set_data)(struct mv88e6xxx_chip *chip, unsigned int pin,
+                       int value);
+
+       /* get/set GPIO direction */
+       int (*get_dir)(struct mv88e6xxx_chip *chip, unsigned int pin);
+       int (*set_dir)(struct mv88e6xxx_chip *chip, unsigned int pin,
+                      bool input);
+
+       /* get/set GPIO pin control */
+       int (*get_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin,
+                       int *func);
+       int (*set_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin,
+                       int func);
+};
+
 struct mv88e6xxx_avb_ops {
        /* Access port-scoped Precision Time Protocol registers */
        int (*port_ptp_read)(struct mv88e6xxx_chip *chip, int port, int addr,
@@ -423,6 +451,11 @@ static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip)
        return GENMASK(mv88e6xxx_num_ports(chip) - 1, 0);
 }
 
+static inline unsigned int mv88e6xxx_num_gpio(struct mv88e6xxx_chip *chip)
+{
+       return chip->info->num_gpio;
+}
+
 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg,

diff --git a/drivers/net/dsa/mv88e6xxx/global2.c b/drivers/net/dsa/mv88e6xxx/global2.c
index 3e7102e..5f370f1 100644 (file)
--- a/drivers/net/dsa/mv88e6xxx/global2.c
+++ b/drivers/net/dsa/mv88e6xxx/global2.c
@@ -798,6 +798,7 @@ int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip, struct mii_bus *bus,
                                                   val);
 }
 
+/* Offset 0x1B: Watchdog Control */
 static int mv88e6097_watchdog_action(struct mv88e6xxx_chip *chip, int irq)
 {
        u16 reg;

diff --git a/drivers/net/dsa/mv88e6xxx/global2.h b/drivers/net/dsa/mv88e6xxx/global2.h
index e1d4850..25f92b3 100644 (file)
--- a/drivers/net/dsa/mv88e6xxx/global2.h
+++ b/drivers/net/dsa/mv88e6xxx/global2.h
@@ -242,6 +242,35 @@
 #define MV88E6352_G2_NOEGR_POLICY      0x2000
 #define MV88E6390_G2_LAG_ID_4          0x2000
 
+/* Scratch/Misc registers accessed through MV88E6XXX_G2_SCRATCH_MISC */
+/* Offset 0x02: Misc Configuration */
+#define MV88E6352_G2_SCRATCH_MISC_CFG          0x02
+#define MV88E6352_G2_SCRATCH_MISC_CFG_NORMALSMI        0x80
+/* Offset 0x60-0x61: GPIO Configuration */
+#define MV88E6352_G2_SCRATCH_GPIO_CFG0         0x60
+#define MV88E6352_G2_SCRATCH_GPIO_CFG1         0x61
+/* Offset 0x62-0x63: GPIO Direction */
+#define MV88E6352_G2_SCRATCH_GPIO_DIR0         0x62
+#define MV88E6352_G2_SCRATCH_GPIO_DIR1         0x63
+#define MV88E6352_G2_SCRATCH_GPIO_DIR_OUT      0
+#define MV88E6352_G2_SCRATCH_GPIO_DIR_IN       1
+/* Offset 0x64-0x65: GPIO Data */
+#define MV88E6352_G2_SCRATCH_GPIO_DATA0                0x64
+#define MV88E6352_G2_SCRATCH_GPIO_DATA1                0x65
+/* Offset 0x68-0x6F: GPIO Pin Control */
+#define MV88E6352_G2_SCRATCH_GPIO_PCTL0                0x68
+#define MV88E6352_G2_SCRATCH_GPIO_PCTL1                0x69
+#define MV88E6352_G2_SCRATCH_GPIO_PCTL2                0x6A
+#define MV88E6352_G2_SCRATCH_GPIO_PCTL3                0x6B
+#define MV88E6352_G2_SCRATCH_GPIO_PCTL4                0x6C
+#define MV88E6352_G2_SCRATCH_GPIO_PCTL5                0x6D
+#define MV88E6352_G2_SCRATCH_GPIO_PCTL6                0x6E
+#define MV88E6352_G2_SCRATCH_GPIO_PCTL7                0x6F
+
+#define MV88E6352_G2_SCRATCH_GPIO_PCTL_GPIO    0
+#define MV88E6352_G2_SCRATCH_GPIO_PCTL_TRIG    1
+#define MV88E6352_G2_SCRATCH_GPIO_PCTL_EVREQ   2
+
 #ifdef CONFIG_NET_DSA_MV88E6XXX_GLOBAL2
 
 static inline int mv88e6xxx_g2_require(struct mv88e6xxx_chip *chip)
@@ -294,6 +323,8 @@ extern const struct mv88e6xxx_irq_ops mv88e6390_watchdog_ops;
 extern const struct mv88e6xxx_avb_ops mv88e6352_avb_ops;
 extern const struct mv88e6xxx_avb_ops mv88e6390_avb_ops;
 
+extern const struct mv88e6xxx_gpio_ops mv88e6352_gpio_ops;
+
 #else /* !CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 */
 
 static inline int mv88e6xxx_g2_require(struct mv88e6xxx_chip *chip)
@@ -432,6 +463,8 @@ static const struct mv88e6xxx_irq_ops mv88e6390_watchdog_ops = {};
 static const struct mv88e6xxx_avb_ops mv88e6352_avb_ops = {};
 static const struct mv88e6xxx_avb_ops mv88e6390_avb_ops = {};
 
+static const struct mv88e6xxx_gpio_ops mv88e6352_gpio_ops = {};
+
 #endif /* CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 */
 
 #endif /* _MV88E6XXX_GLOBAL2_H */

diff --git a/drivers/net/dsa/mv88e6xxx/global2_scratch.c b/drivers/net/dsa/mv88e6xxx/global2_scratch.c
new file mode 100644 (file)
index 0000000..0ff12bf
--- /dev/null
+++ b/drivers/net/dsa/mv88e6xxx/global2_scratch.c
@@ -0,0 +1,240 @@
+/*
+ * Marvell 88E6xxx Switch Global 2 Scratch & Misc Registers support
+ *
+ * Copyright (c) 2008 Marvell Semiconductor
+ *
+ * Copyright (c) 2017 National Instruments
+ *      Brandon Streiff <brandon.streiff@ni.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include "chip.h"
+#include "global2.h"
+
+/* Offset 0x1A: Scratch and Misc. Register */
+static int mv88e6xxx_g2_scratch_read(struct mv88e6xxx_chip *chip, int reg,
+                                    u8 *data)
+{
+       u16 value;
+       int err;
+
+       err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SCRATCH_MISC_MISC,
+                                reg << 8);
+       if (err)
+               return err;
+
+       err = mv88e6xxx_g2_read(chip, MV88E6XXX_G2_SCRATCH_MISC_MISC, &value);
+       if (err)
+               return err;
+
+       *data = (value & MV88E6XXX_G2_SCRATCH_MISC_DATA_MASK);
+
+       return 0;
+}
+
+static int mv88e6xxx_g2_scratch_write(struct mv88e6xxx_chip *chip, int reg,
+                                     u8 data)
+{
+       u16 value = (reg << 8) | data;
+
+       return mv88e6xxx_g2_update(chip, MV88E6XXX_G2_SCRATCH_MISC_MISC, value);
+}
+
+/**
+ * mv88e6xxx_g2_scratch_gpio_get_bit - get a bit
+ * @chip: chip private data
+ * @nr: bit index
+ * @set: is bit set?
+ */
+static int mv88e6xxx_g2_scratch_get_bit(struct mv88e6xxx_chip *chip,
+                                       int base_reg, unsigned int offset,
+                                       int *set)
+{
+       int reg = base_reg + (offset / 8);
+       u8 mask = (1 << (offset & 0x7));
+       u8 val;
+       int err;
+
+       err = mv88e6xxx_g2_scratch_read(chip, reg, &val);
+       if (err)
+               return err;
+
+       *set = !!(mask & val);
+
+       return 0;
+}
+
+/**
+ * mv88e6xxx_g2_scratch_gpio_set_bit - set (or clear) a bit
+ * @chip: chip private data
+ * @nr: bit index
+ * @set: set if true, clear if false
+ *
+ * Helper function for dealing with the direction and data registers.
+ */
+static int mv88e6xxx_g2_scratch_set_bit(struct mv88e6xxx_chip *chip,
+                                       int base_reg, unsigned int offset,
+                                       int set)
+{
+       int reg = base_reg + (offset / 8);
+       u8 mask = (1 << (offset & 0x7));
+       u8 val;
+       int err;
+
+       err = mv88e6xxx_g2_scratch_read(chip, reg, &val);
+       if (err)
+               return err;
+
+       if (set)
+               val |= mask;
+       else
+               val &= ~mask;
+
+       return mv88e6xxx_g2_scratch_write(chip, reg, val);
+}
+
+/**
+ * mv88e6352_g2_scratch_gpio_get_data - get data on gpio pin
+ * @chip: chip private data
+ * @pin: gpio index
+ *
+ * Return: 0 for low, 1 for high, negative error
+ */
+static int mv88e6352_g2_scratch_gpio_get_data(struct mv88e6xxx_chip *chip,
+                                             unsigned int pin)
+{
+       int val = 0;
+       int err;
+
+       err = mv88e6xxx_g2_scratch_get_bit(chip,
+                                          MV88E6352_G2_SCRATCH_GPIO_DATA0,
+                                          pin, &val);
+       if (err)
+               return err;
+
+       return val;
+}
+
+/**
+ * mv88e6352_g2_scratch_gpio_set_data - set data on gpio pin
+ * @chip: chip private data
+ * @pin: gpio index
+ * @value: value to set
+ */
+static int mv88e6352_g2_scratch_gpio_set_data(struct mv88e6xxx_chip *chip,
+                                             unsigned int pin, int value)
+{
+       u8 mask = (1 << (pin & 0x7));
+       int offset = (pin / 8);
+       int reg;
+
+       reg = MV88E6352_G2_SCRATCH_GPIO_DATA0 + offset;
+
+       if (value)
+               chip->gpio_data[offset] |= mask;
+       else
+               chip->gpio_data[offset] &= ~mask;
+
+       return mv88e6xxx_g2_scratch_write(chip, reg, chip->gpio_data[offset]);
+}
+
+/**
+ * mv88e6352_g2_scratch_gpio_get_dir - get direction of gpio pin
+ * @chip: chip private data
+ * @pin: gpio index
+ *
+ * Return: 0 for output, 1 for input (same as GPIOF_DIR_XXX).
+ */
+static int mv88e6352_g2_scratch_gpio_get_dir(struct mv88e6xxx_chip *chip,
+                                            unsigned int pin)
+{
+       int val = 0;
+       int err;
+
+       err = mv88e6xxx_g2_scratch_get_bit(chip,
+                                          MV88E6352_G2_SCRATCH_GPIO_DIR0,
+                                          pin, &val);
+       if (err)
+               return err;
+
+       return val;
+}
+
+/**
+ * mv88e6352_g2_scratch_gpio_set_dir - set direction of gpio pin
+ * @chip: chip private data
+ * @pin: gpio index
+ */
+static int mv88e6352_g2_scratch_gpio_set_dir(struct mv88e6xxx_chip *chip,
+                                            unsigned int pin, bool input)
+{
+       int value = (input ? MV88E6352_G2_SCRATCH_GPIO_DIR_IN :
+                            MV88E6352_G2_SCRATCH_GPIO_DIR_OUT);
+
+       return mv88e6xxx_g2_scratch_set_bit(chip,
+                                           MV88E6352_G2_SCRATCH_GPIO_DIR0,
+                                           pin, value);
+}
+
+/**
+ * mv88e6352_g2_scratch_gpio_get_pctl - get pin control setting
+ * @chip: chip private data
+ * @pin: gpio index
+ * @func: function number
+ *
+ * Note that the function numbers themselves may vary by chipset.
+ */
+static int mv88e6352_g2_scratch_gpio_get_pctl(struct mv88e6xxx_chip *chip,
+                                             unsigned int pin, int *func)
+{
+       int reg = MV88E6352_G2_SCRATCH_GPIO_PCTL0 + (pin / 2);
+       int offset = (pin & 0x1) ? 4 : 0;
+       u8 mask = (0x7 << offset);
+       int err;
+       u8 val;
+
+       err = mv88e6xxx_g2_scratch_read(chip, reg, &val);
+       if (err)
+               return err;
+
+       *func = (val & mask) >> offset;
+
+       return 0;
+}
+
+/**
+ * mv88e6352_g2_scratch_gpio_set_pctl - set pin control setting
+ * @chip: chip private data
+ * @pin: gpio index
+ * @func: function number
+ */
+static int mv88e6352_g2_scratch_gpio_set_pctl(struct mv88e6xxx_chip *chip,
+                                             unsigned int pin, int func)
+{
+       int reg = MV88E6352_G2_SCRATCH_GPIO_PCTL0 + (pin / 2);
+       int offset = (pin & 0x1) ? 4 : 0;
+       u8 mask = (0x7 << offset);
+       int err;
+       u8 val;
+
+       err = mv88e6xxx_g2_scratch_read(chip, reg, &val);
+       if (err)
+               return err;
+
+       val = (val & ~mask) | ((func & mask) << offset);
+
+       return mv88e6xxx_g2_scratch_write(chip, reg, val);
+}
+
+const struct mv88e6xxx_gpio_ops mv88e6352_gpio_ops = {
+       .get_data = mv88e6352_g2_scratch_gpio_get_data,
+       .set_data = mv88e6352_g2_scratch_gpio_set_data,
+       .get_dir = mv88e6352_g2_scratch_gpio_get_dir,
+       .set_dir = mv88e6352_g2_scratch_gpio_set_dir,
+       .get_pctl = mv88e6352_g2_scratch_gpio_get_pctl,
+       .set_pctl = mv88e6352_g2_scratch_gpio_set_pctl,
+};