ram: rk3399: Add DdrMode
authorJagan Teki <jagan@amarulasolutions.com>
Tue, 16 Jul 2019 11:57:06 +0000 (17:27 +0530)
committerKever Yang <kever.yang@rock-chips.com>
Sat, 20 Jul 2019 15:59:44 +0000 (23:59 +0800)
Add DdrMode structure with associated bit fields.

These would help to reconfigure sdram capabilities during
lpddr4 setup related configs.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
drivers/ram/rockchip/sdram_rk3399.c

index 7f41a67..dc65ae7 100644 (file)
@@ -28,6 +28,21 @@ union noc_ddrtimingc0 {
        } b;
 };
 
+union noc_ddrmode {
+       u32 d32;
+       struct {
+               unsigned autoprecharge : 1;
+               unsigned bypassfiltering : 1;
+               unsigned fawbank : 1;
+               unsigned burstsize : 2;
+               unsigned mwrsize : 2;
+               unsigned reserved2 : 1;
+               unsigned forceorder : 8;
+               unsigned forceorderstate : 8;
+               unsigned reserved3 : 8;
+       } b;
+};
+
 struct rk3399_msch_regs {
        u32 coreid;
        u32 revisionid;
@@ -48,7 +63,7 @@ struct rk3399_msch_timings {
        u32 ddrtimingb0;
        union noc_ddrtimingc0 ddrtimingc0;
        u32 devtodev0;
-       u32 ddrmode;
+       union noc_ddrmode ddrmode;
        u32 agingx0;
 };
 
index d47e290..5568ad9 100644 (file)
@@ -1114,7 +1114,7 @@ static void dram_all_config(struct dram_info *dram,
                       &ddr_msch_regs->ddrtimingc0);
                writel(noc_timing->devtodev0,
                       &ddr_msch_regs->devtodev0);
-               writel(noc_timing->ddrmode,
+               writel(noc_timing->ddrmode.d32,
                       &ddr_msch_regs->ddrmode);
 
                /* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */