ARM: dts: am335x-phycore: switch to new cpsw switch drv
authorGrygorii Strashko <grygorii.strashko@ti.com>
Sat, 12 Jun 2021 01:14:33 +0000 (04:14 +0300)
committerTony Lindgren <tony@atomide.com>
Fri, 6 Aug 2021 06:25:37 +0000 (09:25 +0300)
The dual_mac mode has been preserved the same way between legacy and new
driver, and one port devices works the same as 1 dual_mac port - it's safe
to switch drivers.

So, switch Phytec AM335x phyCORE SOM, phyBOARD-WEGA, phyBOARD-REGOR,
PCM-953 to use new cpsw switch driver. Those boards have or 2 Ext. port
wired and configured in dual_mac mode by default, or only 1 Ext. port.

Cc: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
arch/arm/boot/dts/am335x-pcm-953.dtsi
arch/arm/boot/dts/am335x-phycore-som.dtsi
arch/arm/boot/dts/am335x-regor.dtsi
arch/arm/boot/dts/am335x-wega.dtsi

index 6c547c8..124026f 100644 (file)
        };
 };
 
-&cpsw_emac1 {
+&cpsw_port2 {
        phy-handle = <&phy1>;
        phy-mode = "rgmii-id";
-       dual_emac_res_vlan = <2>;
+       ti,dual-emac-pvid = <2>;
        status = "okay";
 };
 
-&davinci_mdio {
+&davinci_mdio_sw {
        phy1: ethernet-phy@2 {
                reg = <2>;
        };
 };
 
-&mac {
-       slaves = <2>;
+&mac_sw {
        pinctrl-names = "default";
        pinctrl-0 = <&ethernet0_pins &ethernet1_pins>;
-       dual_emac;
 };
 
 /* Misc */
index 7e46b4c..f65cd13 100644 (file)
        };
 };
 
-&cpsw_emac0 {
+&cpsw_port1 {
        phy-handle = <&phy0>;
        phy-mode = "rmii";
-       dual_emac_res_vlan = <1>;
+       ti,dual-emac-pvid = <1>;
 };
 
-&davinci_mdio {
+&cpsw_port2 {
+       status = "disabled";
+};
+
+&davinci_mdio_sw {
        pinctrl-names = "default";
        pinctrl-0 = <&mdio_pins>;
-       status = "okay";
 
        phy0: ethernet-phy@0 {
                reg = <0>;
        };
 };
 
-&mac {
-       slaves = <1>;
+&mac_sw {
        pinctrl-names = "default";
        pinctrl-0 = <&ethernet0_pins>;
        status = "okay";
index 6fbf4ac..7b3966e 100644 (file)
        };
 };
 
-&cpsw_emac1 {
+&cpsw_port2 {
+       status = "okay";
        phy-handle = <&phy1>;
        phy-mode = "mii";
-       dual_emac_res_vlan = <2>;
+       ti,dual-emac-pvid = <2>;
 };
 
-&davinci_mdio {
+&davinci_mdio_sw {
        phy1: ethernet-phy@1 {
                reg = <1>;
        };
 };
 
-&mac {
-       slaves = <2>;
+&mac_sw {
        pinctrl-names = "default";
        pinctrl-0 = <&ethernet0_pins &ethernet1_pins>;
-       dual_emac = <1>;
 };
 
 /* GPIOs */
index 1359bf8..673159d 100644 (file)
        };
 };
 
-&cpsw_emac1 {
+&cpsw_port2 {
+       status = "okay";
        phy-handle = <&phy1>;
        phy-mode = "mii";
-       dual_emac_res_vlan = <2>;
+       ti,dual-emac-pvid = <2>;
 };
 
-&davinci_mdio {
+&davinci_mdio_sw {
        phy1: ethernet-phy@1 {
                reg = <1>;
        };
 };
 
-&mac {
-       slaves = <2>;
+&mac_sw {
        pinctrl-names = "default";
        pinctrl-0 = <&ethernet0_pins &ethernet1_pins>;
-       dual_emac = <1>;
 };
 
 /* MMC */