intel/compiler: Store start of ICP handles in GS thread payload struct

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18176>

diff --git a/src/intel/compiler/brw_fs.h b/src/intel/compiler/brw_fs.h
index fe741e3..2b74d1f 100644 (file)
--- a/src/intel/compiler/brw_fs.h
+++ b/src/intel/compiler/brw_fs.h
@@ -121,6 +121,7 @@ struct gs_thread_payload : public thread_payload {
 
    fs_reg urb_handles;
    fs_reg primitive_id;
+   fs_reg icp_handle_start;
 };
 
 struct fs_thread_payload : public thread_payload {

diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index ca6a2f4..2952117 100644 (file)
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -2521,8 +2521,7 @@ fs_visitor::emit_gs_input_load(const fs_reg &dst,
    /* Resort to the pull model.  Ensure the VUE handles are provided. */
    assert(gs_prog_data->base.include_vue_handles);
 
-   unsigned first_icp_handle = gs_prog_data->include_primitive_id ? 3 : 2;
-   fs_reg start = retype(brw_vec8_grf(first_icp_handle, 0), BRW_REGISTER_TYPE_UD);
+   fs_reg start = gs_payload().icp_handle_start;
    fs_reg icp_handle = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
 
    if (gs_prog_data->invocations == 1) {

diff --git a/src/intel/compiler/brw_fs_thread_payload.cpp b/src/intel/compiler/brw_fs_thread_payload.cpp
index f800eb7..7677b17 100644 (file)
--- a/src/intel/compiler/brw_fs_thread_payload.cpp
+++ b/src/intel/compiler/brw_fs_thread_payload.cpp
@@ -107,6 +107,7 @@ gs_thread_payload::gs_thread_payload(const fs_visitor &v)
    gs_prog_data->base.include_vue_handles = true;
 
    /* R3..RN: ICP Handles for each incoming vertex (when using pull model) */
+   icp_handle_start = retype(brw_vec8_grf(r, 0), BRW_REGISTER_TYPE_UD);
    r += v.nir->info.gs.vertices_in;
 
    num_regs = r;