radeonsi: implement nir_load_ring_attr_amd

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19429>

diff --git a/src/gallium/drivers/radeonsi/si_shader_internal.h b/src/gallium/drivers/radeonsi/si_shader_internal.h
index 066943810dfd749b6a26c69a1f3aa4ee124efd82..3ce257881b68b7ae269dbf235f465b62ea80b7fe 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_shader_internal.h
+++ b/src/gallium/drivers/radeonsi/si_shader_internal.h
@@ -231,6 +231,7 @@ bool si_llvm_compile_shader(struct si_screen *sscreen, struct ac_llvm_compiler *
                             struct si_shader *shader, const struct pipe_stream_output_info *so,
                             struct util_debug_callback *debug, struct nir_shader *nir,
                             bool free_nir);
+LLVMValueRef si_llvm_build_attr_ring_desc(struct si_shader_context *ctx);
 
 /* si_shader_llvm_gs.c */
 LLVMValueRef si_is_es_thread(struct si_shader_context *ctx);

diff --git a/src/gallium/drivers/radeonsi/si_shader_llvm.c b/src/gallium/drivers/radeonsi/si_shader_llvm.c
index 58b4f8fbd032c68e2e059b97c7bb40feb17dd9c9..075f8d13dbf05df6f584b30f445354f9b24a703c 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_shader_llvm.c
+++ b/src/gallium/drivers/radeonsi/si_shader_llvm.c
@@ -732,6 +732,38 @@ static LLVMValueRef si_get_num_vertices_per_prim(struct si_shader_context *ctx)
    return LLVMConstInt(ctx->ac.i32, num_vertices, false);
 }
 
+LLVMValueRef si_llvm_build_attr_ring_desc(struct si_shader_context *ctx)
+{
+   struct si_shader *shader = ctx->shader;
+
+   LLVMValueRef attr_address;
+   if (ctx->stage == MESA_SHADER_VERTEX && shader->selector->info.base.vs.blit_sgprs_amd) {
+      struct ac_llvm_pointer ring_ptr = ac_get_ptr_arg(&ctx->ac, &ctx->args, ctx->internal_bindings);
+      ring_ptr.pointee_type = ctx->ac.i32;
+      attr_address = ac_build_load_to_sgpr(&ctx->ac, ring_ptr,
+                                           LLVMConstInt(ctx->ac.i32, SI_GS_ATTRIBUTE_RING * 4, 0));
+   } else {
+      attr_address = ac_get_arg(&ctx->ac, ctx->gs_attr_address);
+   }
+
+   unsigned stride = 16 * shader->info.nr_param_exports;
+   LLVMValueRef attr_desc[4] = {
+      attr_address,
+      LLVMConstInt(ctx->ac.i32, S_008F04_BASE_ADDRESS_HI(ctx->screen->info.address32_hi) |
+                   S_008F04_STRIDE(stride) |
+                   S_008F04_SWIZZLE_ENABLE_GFX11(3) /* 16B */, 0),
+      LLVMConstInt(ctx->ac.i32, 0xffffffff, 0),
+      LLVMConstInt(ctx->ac.i32, S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
+                   S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
+                   S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
+                   S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
+                   S_008F0C_FORMAT(V_008F0C_GFX11_FORMAT_32_32_32_32_FLOAT) |
+                   S_008F0C_INDEX_STRIDE(2) /* 32 elements */, 0),
+   };
+
+   return ac_build_gather_values(&ctx->ac, attr_desc, 4);
+}
+
 static LLVMValueRef si_llvm_load_intrinsic(struct ac_shader_abi *abi, nir_intrinsic_op op)
 {
    struct si_shader_context *ctx = si_shader_context_from_abi(abi);
@@ -884,6 +916,9 @@ static LLVMValueRef si_llvm_load_intrinsic(struct ac_shader_abi *abi, nir_intrin
       return LLVMBuildTrunc(ctx->ac.builder, enabled, ctx->ac.i1, "");
    }
 
+   case nir_intrinsic_load_ring_attr_amd:
+      return si_llvm_build_attr_ring_desc(ctx);
+
    default:
       return NULL;
    }

diff --git a/src/gallium/drivers/radeonsi/si_shader_llvm_vs.c b/src/gallium/drivers/radeonsi/si_shader_llvm_vs.c
index 7e0ce7c8d75bd9d057a9efa467895599f3e31531..31ba30d5f32f860ad152e1176d1ea5680bc558bc 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_shader_llvm_vs.c
+++ b/src/gallium/drivers/radeonsi/si_shader_llvm_vs.c
@@ -743,32 +743,7 @@ void si_llvm_build_vs_exports(struct si_shader_context *ctx, LLVMValueRef num_ex
                     LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
                                   ac_get_thread_id(&ctx->ac), num_export_threads, ""), 0);
 
-      /* Get the attribute ring address and descriptor. */
-      LLVMValueRef attr_address;
-      if (ctx->stage == MESA_SHADER_VERTEX && shader->selector->info.base.vs.blit_sgprs_amd) {
-         struct ac_llvm_pointer ring_ptr = ac_get_ptr_arg(&ctx->ac, &ctx->args, ctx->internal_bindings);
-         ring_ptr.pointee_type = ctx->ac.i32;
-         attr_address = ac_build_load_to_sgpr(&ctx->ac, ring_ptr,
-                                              LLVMConstInt(ctx->ac.i32, SI_GS_ATTRIBUTE_RING * 4, 0));
-      } else {
-         attr_address = ac_get_arg(&ctx->ac, ctx->gs_attr_address);
-      }
-
-      unsigned stride = 16 * shader->info.nr_param_exports;
-      LLVMValueRef attr_desc[4] = {
-         attr_address,
-         LLVMConstInt(ctx->ac.i32, S_008F04_BASE_ADDRESS_HI(ctx->screen->info.address32_hi) |
-                                   S_008F04_STRIDE(stride) |
-                                   S_008F04_SWIZZLE_ENABLE_GFX11(3) /* 16B */, 0),
-         LLVMConstInt(ctx->ac.i32, 0xffffffff, 0),
-         LLVMConstInt(ctx->ac.i32, S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
-                                   S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
-                                   S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
-                                   S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
-                                   S_008F0C_FORMAT(V_008F0C_GFX11_FORMAT_32_32_32_32_FLOAT) |
-                                   S_008F0C_INDEX_STRIDE(2) /* 32 elements */, 0),
-      };
-      LLVMValueRef attr_rsrc = ac_build_gather_values(&ctx->ac, attr_desc, 4);
+      LLVMValueRef attr_rsrc = si_llvm_build_attr_ring_desc(ctx);
       LLVMValueRef attr_offset = LLVMBuildShl(ctx->ac.builder,
                                               si_unpack_param(ctx, ctx->args.gs_attr_offset, 0, 15),
                                               LLVMConstInt(ctx->ac.i32, 9, 0), ""); /* 512B increments */