return false;
}
+static SDValue performReinterpretCastCombine(SDNode *N) {
+ SDValue LeafOp = SDValue(N, 0);
+ SDValue Op = N->getOperand(0);
+ while (Op.getOpcode() == AArch64ISD::REINTERPRET_CAST &&
+ LeafOp.getValueType() != Op.getValueType())
+ Op = Op->getOperand(0);
+ if (LeafOp.getValueType() == Op.getValueType())
+ return Op;
+ return SDValue();
+}
+
static SDValue performSVEAndCombine(SDNode *N,
TargetLowering::DAGCombinerInfo &DCI) {
if (DCI.isBeforeLegalizeOps())
return DAG.getNode(Opc, DL, N->getValueType(0), And);
}
+ // If both sides of AND operations are i1 splat_vectors then
+ // we can produce just i1 splat_vector as the result.
+ if (isAllActivePredicate(DAG, N->getOperand(0)))
+ return N->getOperand(1);
+ if (isAllActivePredicate(DAG, N->getOperand(1)))
+ return N->getOperand(0);
+
if (!EnableCombineMGatherIntrinsics)
return SDValue();
return performUzpCombine(N, DAG);
case AArch64ISD::SETCC_MERGE_ZERO:
return performSetccMergeZeroCombine(N, DCI);
+ case AArch64ISD::REINTERPRET_CAST:
+ return performReinterpretCastCombine(N);
case AArch64ISD::GLD1_MERGE_ZERO:
case AArch64ISD::GLD1_SCALED_MERGE_ZERO:
case AArch64ISD::GLD1_UXTW_MERGE_ZERO:
--- /dev/null
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s | FileCheck %s
+
+target triple = "aarch64-unknown-linux-gnu"
+
+; Ensure that a no-op 'and' get removed with vector splat of 1 or ptrue with proper constant
+
+define <vscale x 16 x i1> @fold_away_ptrue_and_ptrue() #0 {
+; CHECK-LABEL: fold_away_ptrue_and_ptrue:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: ret
+entry:
+ %0 = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
+ %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %0)
+ %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
+ %and = and <vscale x 16 x i1> %2, %1
+ ret <vscale x 16 x i1> %and
+}
+
+define <vscale x 16 x i1> @fold_away_ptrue_and_splat_predicate() #0 {
+; CHECK-LABEL: fold_away_ptrue_and_splat_predicate:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: ret
+entry:
+ %ins = insertelement <vscale x 4 x i1> undef, i1 1, i32 0
+ %splat = shufflevector <vscale x 4 x i1> %ins, <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
+ %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %splat)
+ %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
+ %and = and <vscale x 16 x i1> %0, %1
+ ret <vscale x 16 x i1> %and
+}
+
+; Ensure that one AND operation remain for inactive lanes zeroing with 2 x i1 type (llvm.aarch64.sve.convert.to.svbool.nxv2i1).
+define <vscale x 16 x i1> @fold_away_ptrue_and_convert_to() #0 {
+; CHECK-LABEL: fold_away_ptrue_and_convert_to:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: ptrue p1.d
+; CHECK-NEXT: and p0.b, p1/z, p1.b, p0.b
+; CHECK-NEXT: ret
+entry:
+ %0 = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
+ %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %0)
+ %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
+ %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %2)
+ %4 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %3)
+ %and = and <vscale x 16 x i1> %4, %1
+ ret <vscale x 16 x i1> %and
+}
+
+define <vscale x 16 x i1> @fold_away_two_similar() #0 {
+; CHECK-LABEL: fold_away_two_similar:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: ret
+entry:
+ %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
+ %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
+ %and = and <vscale x 16 x i1> %0, %1
+ ret <vscale x 16 x i1> %and
+}
+
+declare <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 immarg)
+
+declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>)
+
+declare <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 immarg)
+
+declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>)
+
+declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>)
+
+
+attributes #0 = { "target-features"="+sve" }