/* DEVICE_CFG1 */
#define RSEL(x) (((x) & 0x3) << 3)
#define RSEL_MASK RSEL(0x3)
+#define AUXOUTSRC(x) (((x) & 0x3) << 1)
+#define AUXOUTSRC_MASK AUXOUTSRC(0x3)
#define ENDEV1 (0x1)
/* DEVICE_CFG2 */
struct clk_init_data init;
const char *name = np->name;
static const char *parent_names[CLK_MAX];
+ u32 aux_out = 0;
int ch = 0; /* it uses ch0 only at this point */
int rate;
int ret;
of_property_read_string(np, "clock-output-names", &name);
+ of_property_read_u32(np, "cirrus,aux-output-source", &aux_out);
+ ret = cs2000_bset(priv, DEVICE_CFG1,
+ AUXOUTSRC_MASK, AUXOUTSRC(aux_out));
+ if (ret < 0)
+ return ret;
+
/*
* set default rate as 1/1.
* otherwise .set_rate which setup ratio