* more details.
*
*/
-
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/of_address.h>
},
.n = {
.reg_off = HHI_GP1_PLL_CNTL0,
- .shift = 9,
+ .shift = 10,
.width = 5,
},
.od = {
.reg_off = HHI_GP1_PLL_CNTL0,
.shift = 16,
- .width = 2,
+ .width = 3,
},
.rate_table = tl1_pll_rate_table,
.rate_count = ARRAY_SIZE(tl1_pll_rate_table),
* post-dividers and should be modelled with their respective PLLs via the
* forthcoming coordinated clock rates feature
*/
-static u32 mux_table_cpu_p[] = { 0, 1, 2 };
+static u32 mux_table_cpu_p[] = { 0, 1, 2, 3 };
static u32 mux_table_cpu_px[] = { 0, 1 };
static struct meson_cpu_mux_divider tl1_cpu_fclk_p = {
.reg = (void *)HHI_SYS_CPU_CLK_CNTL0,
.name = "cpu_fixedpll_p",
.ops = &meson_fclk_cpu_ops,
.parent_names = (const char *[]){ "xtal", "fclk_div2",
- "fclk_div3"},
- .num_parents = 3,
+ "fclk_div3", "gp1_pll"},
+ .num_parents = 4,
.flags = (CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED),
},
};
},
};
+
+/* dsu clocks */
+static const char * const dsu_fixed_source_sel_parent_names[] = {
+ "xtal", "fclk_div2", "fclk_div3", "gp1_pll"
+};
+
+/* fixed sel0 */
+static struct clk_mux tl1_dsu_fixed_source_sel0 = {
+ .reg = (void *)HHI_SYS_CPU_CLK_CNTL5,
+ .mask = 0x3,
+ .shift = 0,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "dsu_fixed_source_sel0",
+ .ops = &clk_mux_ops,
+ .parent_names = dsu_fixed_source_sel_parent_names,
+ .num_parents = ARRAY_SIZE(dsu_fixed_source_sel_parent_names),
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_divider tl1_dsu_fixed_source_div0 = {
+ .reg = (void *)HHI_SYS_CPU_CLK_CNTL5,
+ .shift = 4,
+ .width = 6,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "dsu_fixed_source_div0",
+ .ops = &clk_divider_ops,
+ .parent_names = (const char *[]){ "dsu_fixed_source_sel0" },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_mux tl1_dsu_fixed_sel0 = {
+ .reg = (void *)HHI_SYS_CPU_CLK_CNTL5,
+ .mask = 0x1,
+ .shift = 2,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "dsu_fixed_sel0",
+ .ops = &clk_mux_ops,
+ .parent_names = (const char *[]){ "dsu_fixed_source_sel0",
+ "dsu_fixed_source_div0" },
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
+ },
+};
+
+/* fixed sel1 */
+static struct clk_mux tl1_dsu_fixed_source_sel1 = {
+ .reg = (void *)HHI_SYS_CPU_CLK_CNTL5,
+ .mask = 0x3,
+ .shift = 16,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "dsu_fixed_source_sel1",
+ .ops = &clk_mux_ops,
+ .parent_names = dsu_fixed_source_sel_parent_names,
+ .num_parents = ARRAY_SIZE(dsu_fixed_source_sel_parent_names),
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_divider tl1_dsu_fixed_source_div1 = {
+ .reg = (void *)HHI_SYS_CPU_CLK_CNTL5,
+ .shift = 20,
+ .width = 6,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "dsu_fixed_source_div1",
+ .ops = &clk_divider_ops,
+ .parent_names = (const char *[]){ "dsu_fixed_source_sel1" },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_mux tl1_dsu_fixed_sel1 = {
+ .reg = (void *)HHI_SYS_CPU_CLK_CNTL5,
+ .mask = 0x1,
+ .shift = 18,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "dsu_fixed_sel1",
+ .ops = &clk_mux_ops,
+ .parent_names = (const char *[]){ "dsu_fixed_source_sel1",
+ "dsu_fixed_source_div1" },
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
+ },
+};
+
+/* dsu pre clock parent 0 */
+static struct clk_mux tl1_dsu_pre0_clk = {
+ .reg = (void *)HHI_SYS_CPU_CLK_CNTL5,
+ .mask = 0x1,
+ .shift = 10,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "dsu_pre0_clk",
+ .ops = &clk_mux_ops,
+ .parent_names = (const char *[]){ "dsu_fixed_sel0",
+ "dsu_fixed_sel1" },
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
+ },
+};
+
+static struct clk_mux tl1_dsu_pre_clk = {
+ .reg = (void *)HHI_SYS_CPU_CLK_CNTL5,
+ .mask = 0x1,
+ .shift = 11,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "dsu_pre_clk",
+ .ops = &clk_mux_ops,
+ .parent_names = (const char *[]){ "dsu_pre0_clk", "sys_pll" },
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
+ },
+};
+
+static struct clk_mux tl1_dsu_clk = {
+ .reg = (void *)HHI_SYS_CPU_CLK_CNTL6,
+ .mask = 0x1,
+ .shift = 27,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "dsu_clk",
+ .ops = &clk_mux_ops,
+ .parent_names = (const char *[]){ "cpu_clk", "dsu_pre_clk" },
+ .num_parents = 2,
+ },
+};
+
static u32 mux_table_clk81[] = { 6, 5, 7 };
static struct clk_mux tl1_mpeg_clk_sel = {
[CLKID_CPU_FCLK_P] = &tl1_cpu_fclk_p.hw,
[CLKID_CPU_CLK] = &tl1_cpu_clk.mux.hw,
+ [CLKID_DSU_SOURCE_SEL0] = &tl1_dsu_fixed_source_sel0.hw,
+ [CLKID_DSU_SOURCE_DIV0] = &tl1_dsu_fixed_source_div0.hw,
+ [CLKID_DSU_SEL0] = &tl1_dsu_fixed_sel0.hw,
+ [CLKID_DSU_SOURCE_SEL1] = &tl1_dsu_fixed_source_sel1.hw,
+ [CLKID_DSU_SOURCE_DIV1] = &tl1_dsu_fixed_source_div1.hw,
+ [CLKID_DSU_SEL1] = &tl1_dsu_fixed_sel1.hw,
+ [CLKID_DSU_PRE_PARENT0] = &tl1_dsu_pre0_clk.hw,
+ [CLKID_DSU_PRE_CLK] = &tl1_dsu_pre_clk.hw,
+ [CLKID_DSU_CLK] = &tl1_dsu_clk.hw,
};
/* Convenience tables to populate base addresses in .probe */
tl1_cpu_clk.mux.reg = clk_base
+ (unsigned long)tl1_cpu_clk.mux.reg;
+ /* Populate the base address for DSU clk */
+ tl1_dsu_fixed_source_sel0.reg = clk_base
+ + (unsigned long)tl1_dsu_fixed_source_sel0.reg;
+ tl1_dsu_fixed_source_div0.reg = clk_base
+ + (unsigned long)tl1_dsu_fixed_source_div0.reg;
+ tl1_dsu_fixed_sel0.reg = clk_base
+ + (unsigned long)tl1_dsu_fixed_sel0.reg;
+
+ tl1_dsu_fixed_source_sel1.reg = clk_base
+ + (unsigned long)tl1_dsu_fixed_source_sel1.reg;
+ tl1_dsu_fixed_source_div1.reg = clk_base
+ + (unsigned long)tl1_dsu_fixed_source_div1.reg;
+ tl1_dsu_fixed_sel1.reg = clk_base
+ + (unsigned long)tl1_dsu_fixed_sel1.reg;
+
+ tl1_dsu_pre0_clk.reg = clk_base
+ + (unsigned long)tl1_dsu_pre0_clk.reg;
+ tl1_dsu_pre_clk.reg = clk_base
+ + (unsigned long)tl1_dsu_pre_clk.reg;
+ tl1_dsu_clk.reg = clk_base
+ + (unsigned long)tl1_dsu_clk.reg;
+
/* Populate base address for gates */
for (i = 0; i < ARRAY_SIZE(tl1_clk_gates); i++)
tl1_clk_gates[i]->reg = clk_base +
/*register all clks*/
for (clkid = 0; clkid < CLOCK_GATE; clkid++) {
if (tl1_clk_hws[clkid]) {
- clks[clkid] = clk_register(NULL, tl1_clk_hws[clkid]);
- WARN_ON(IS_ERR(clks[clkid]));
+ clks[clkid] = clk_register(NULL, tl1_clk_hws[clkid]);
+ WARN_ON(IS_ERR(clks[clkid]));
}
}
meson_tl1_gpu_init();
meson_tl1_misc_init();
+ /* now cpu clock parent is sys pll , that is to say register
+ * sys pll notify clock, why not register tl1_sys_pll.hw derectly?
+ */
parent_hw = clk_hw_get_parent(&tl1_cpu_clk.mux.hw);
parent_clk = parent_hw->clk;
ret = clk_notifier_register(parent_clk, &tl1_cpu_clk.clk_nb);
goto iounmap;
}
+ /* set sys pll as dsu_pre's parent*/
+ /*clk_set_parent(tl1_dsu_pre_clk.hw.clk, tl1_sys_pll.hw.clk);*/
+ /* set tl1_dsu_pre0_clk to 1.5G, gp1 pll is 1.5G */
+ /*clk_set_rate(tl1_dsu_pre0_clk.hw.clk, 1500000000);*/
+ /*set tl1_dsu_pre0_clk as dsu_pre's parent */
+ /*clk_set_parent(tl1_dsu_pre_clk.hw.clk, tl1_dsu_pre0_clk.hw.clk);*/
+ /*set dsu pre clk to 1GHZ*/
+ clk_set_rate(tl1_dsu_pre_clk.hw.clk, 1000000000);
+ clk_prepare_enable(tl1_dsu_pre_clk.hw.clk);
+
ret = of_clk_add_provider(np, of_clk_src_onecell_get,
&clk_data);
if (ret < 0) {
#define CLKID_MPLL1 15
#define CLKID_MPLL2 16
#define CLKID_MPLL3 17
-#define CLKID_CPU_FCLK_P00 18
-#define CLKID_CPU_FCLK_P01 19
-#define CLKID_CPU_FCLK_P0 20
-#define CLKID_CPU_FCLK_P10 21
-#define CLKID_CPU_FCLK_P11 22
-#define CLKID_CPU_FCLK_P1 23
-#define CLKID_CPU_FCLK_P 24
-#define CLKID_CPU_CLK 25
+#define CLKID_CPU_FCLK_P 18
+#define CLKID_CPU_CLK 19
+#define CLKID_DSU_SOURCE_SEL0 20
+#define CLKID_DSU_SOURCE_DIV0 21
+#define CLKID_DSU_SEL0 22
+#define CLKID_DSU_SOURCE_SEL1 23
+#define CLKID_DSU_SOURCE_DIV1 24
+#define CLKID_DSU_SEL1 25
+#define CLKID_DSU_PRE_PARENT0 26
+#define CLKID_DSU_PRE_CLK 27
+#define CLKID_DSU_CLK 28
/*#define CLKID_ADC_PLL 24*/
-#define CLKID_PCIE_PLL 26
-#define CLKID_VIPNANOQ 27
-#define CLKID_PCIE1 28
-#define CLKID_PCIE0PHY 29
-#define CLKID_PCIE1PHY 30
-#define CLKID_PARSER1 31
-#define CLKID_HDCP22_PCLK 32
-#define CLKID_HDMITX_PCLK 33
-#define CLKID_HDMITX_AXI_PCLK 34
-#define CLKID_DSPB 35
-#define CLKID_DSPA 36
+#define CLKID_PCIE_PLL 29
+#define CLKID_VIPNANOQ 30
+#define CLKID_PCIE1 31
+#define CLKID_PCIE0PHY 32
+#define CLKID_PCIE1PHY 33
+#define CLKID_PARSER1 34
+#define CLKID_HDCP22_PCLK 35
+#define CLKID_HDMITX_PCLK 36
+#define CLKID_HDMITX_AXI_PCLK 37
+#define CLKID_DSPB 38
+#define CLKID_DSPA 39
/* dsp clocks */
-#define CLKID_DSPA_MUX_A 37
-#define CLKID_DSPA_DIV_A 38
-#define CLKID_DSPA_GATE_A 39
-#define CLKID_DSPA_MUX_B 40
-#define CLKID_DSPA_DIV_B 41
-#define CLKID_DSPA_GATE_B 42
-#define CLKID_DSPA_MUX 43
-#define CLKID_DSPB_MUX_A 44
-#define CLKID_DSPB_DIV_A 45
-#define CLKID_DSPB_GATE_A 46
-#define CLKID_DSPB_MUX_B 47
-#define CLKID_DSPB_DIV_B 48
-#define CLKID_DSPB_GATE_B 49
-#define CLKID_DSPB_MUX 50
-#define CLKID_PCIE0_GATE 51
-#define CLKID_PCIE1_GATE 52
-#define CLKID_PCIE0 53
-#define CLKID_PCIE01_ENABLE 54
+#define CLKID_DSPA_MUX_A 40
+#define CLKID_DSPA_DIV_A 41
+#define CLKID_DSPA_GATE_A 42
+#define CLKID_DSPA_MUX_B 43
+#define CLKID_DSPA_DIV_B 44
+#define CLKID_DSPA_GATE_B 45
+#define CLKID_DSPA_MUX 46
+#define CLKID_DSPB_MUX_A 47
+#define CLKID_DSPB_DIV_A 48
+#define CLKID_DSPB_GATE_A 49
+#define CLKID_DSPB_MUX_B 50
+#define CLKID_DSPB_DIV_B 51
+#define CLKID_DSPB_GATE_B 52
+#define CLKID_DSPB_MUX 53
+#define CLKID_PCIE0_GATE 54
+#define CLKID_PCIE1_GATE 55
+#define CLKID_PCIE0 56
+#define CLKID_PCIE01_ENABLE 57
/*HHI_GCLK_MPEG0: 0x50*/
-#define GATE_BASE0 55
+#define GATE_BASE0 58
#define CLKID_DDR (GATE_BASE0 + 0)
#define CLKID_DOS (GATE_BASE0 + 1)
projects / platform / kernel / linux-amlogic.git / commitdiff