clk: samsung: exynos5433: Fix wrong registers of PCLK_GSCL_SMMU clocks

This fixes register assignment in the CLK_PCLK_SMMU_GSCL{1,2}
clocks definition.

Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
index 23dd651..707a814 100644 (file)
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -3411,11 +3411,11 @@ static struct samsung_gate_clock gscl_gate_clks[] __initdata = {
 
        /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 */
        GATE(CLK_PCLK_SMMU_GSCL1, "pclk_smmu_gscl1", "mout_aclk_gscl_111_user",
-               ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
+               ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0),
 
        /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 */
        GATE(CLK_PCLK_SMMU_GSCL2, "pclk_smmu_gscl2", "mout_aclk_gscl_111_user",
-               ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
+               ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0),
 };
 
 static struct samsung_cmu_info gscl_cmu_info __initdata = {