env->pvr.regs[10] = 0x0e000000; /* virtex 6 */
/* setup pvr to match kernel setting */
- env->pvr.regs[5] |= PVR5_DCACHE_WRITEBACK_MASK;
env->pvr.regs[0] |= PVR0_ENDI;
env->pvr.regs[0] = (env->pvr.regs[0] & ~PVR0_VERSION_MASK) | (0x14 << 8);
env->pvr.regs[4] = 0xc56b8000;
* root instructions
*/
object_property_set_int(OBJECT(cpu), 1, "use-fpu", &error_abort);
+ object_property_set_bool(OBJECT(cpu), true, "dcache-writeback",
+ &error_abort);
object_property_set_bool(OBJECT(cpu), true, "realized", &error_abort);
/* Attach emulated BRAM through the LMB. */
env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
(cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0);
+ env->pvr.regs[5] |= cpu->cfg.dcache_writeback ?
+ PVR5_DCACHE_WRITEBACK_MASK : 0;
+
env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */
env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);
*/
DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2),
DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true),
+ DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
+ false),
DEFINE_PROP_END_OF_LIST(),
};