drm/i915/dg2: Wait for SNPS PHY calibration during display init

Initialization of the PHY is handled by the hardware/firmware, but the
driver should wait up to 25ms for the PHY to report that its calibration
has completed.

Bspec: 49189
Bspec: 50107
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210723174239.1551352-28-matthew.d.roper@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 81efc77bada08f08319f2dcc89683e09c515aef8..39cb55f3a6487873ef53afc5e8863ab4ed5e259d 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -18,6 +18,7 @@
 #include "intel_pm.h"
 #include "intel_pps.h"
 #include "intel_sideband.h"
+#include "intel_snps_phy.h"
 #include "intel_tc.h"
 #include "intel_vga.h"
 
@@ -5901,6 +5902,10 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
        if (DISPLAY_VER(dev_priv) >= 12)
                tgl_bw_buddy_init(dev_priv);
 
+       /* 8. Ensure PHYs have completed calibration and adaptation */
+       if (IS_DG2(dev_priv))
+               intel_snps_phy_wait_for_calibration(dev_priv);
+
        if (resume && intel_dmc_has_payload(dev_priv))
                intel_dmc_load_program(dev_priv);
 

diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c
index 77759bda98a489a0f54311f96b26752cbb8e29a7..f0c30d3d2dfbba2fbf9bce04ba6cc8e7222331a1 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
@@ -21,6 +21,21 @@
  * since it is not handled by the shared DPLL framework as on other platforms.
  */
 
+void intel_snps_phy_wait_for_calibration(struct drm_i915_private *dev_priv)
+{
+       enum phy phy;
+
+       for_each_phy_masked(phy, ~0) {
+               if (!intel_phy_is_snps(dev_priv, phy))
+                       continue;
+
+               if (intel_de_wait_for_clear(dev_priv, ICL_PHY_MISC(phy),
+                                           DG2_PHY_DP_TX_ACK_MASK, 25))
+                       DRM_ERROR("SNPS PHY %c failed to calibrate after 25ms.\n",
+                                 phy);
+       }
+}
+
 static const u32 dg2_ddi_translations[] = {
        /* VS 0, pre-emph 0 */
        REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 26),

diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.h b/drivers/gpu/drm/i915/display/intel_snps_phy.h
index 3ce92d424f66c2f0b459fcd249ddd922d9c867fc..6aa33ff729ec9580211e5b865b6d6ca08dfd46a4 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_snps_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_snps_phy.h
@@ -8,10 +8,13 @@
 
 #include <linux/types.h>
 
+struct drm_i915_private;
 struct intel_encoder;
 struct intel_crtc_state;
 struct intel_mpllb_state;
 
+void intel_snps_phy_wait_for_calibration(struct drm_i915_private *dev_priv);
+
 int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state,
                           struct intel_encoder *encoder);
 void intel_mpllb_enable(struct intel_encoder *encoder,

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4b0ce34ef9bb341172bee0dd0540ecfbd68b146d..7306832921f89d4d4289e46dae08c48f06edb807 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -12434,6 +12434,7 @@ enum skl_power_gate {
                                                 _ICL_PHY_MISC_B)
 #define  ICL_PHY_MISC_MUX_DDID                 (1 << 28)
 #define  ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN      (1 << 23)
+#define  DG2_PHY_DP_TX_ACK_MASK                        REG_GENMASK(23, 20)
 
 /* Icelake Display Stream Compression Registers */
 #define DSCA_PICTURE_PARAMETER_SET_0           _MMIO(0x6B200)