MIPS: Netlogic: Split XLP L1 i-cache among threads

Since we now use r4k cache code for Netlogic XLP, it is
better to split L1 icache among the active threads, so that
threads won't step on each other while flushing icache.

The L1 dcache is already split among the threads in the core.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/4787/
Signed-off-by: John Crispin <blogic@openwrt.org>

diff --git a/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
index 7b63a6b..6d2e58a 100644 (file)
--- a/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
@@ -46,6 +46,8 @@
 #define CPU_BLOCKID_FPU                9
 #define CPU_BLOCKID_MAP                10
 
+#define ICU_DEFEATURE          0x100
+
 #define LSU_DEFEATURE          0x304
 #define LSU_DEBUG_ADDR         0x305
 #define LSU_DEBUG_DATA0                0x306

diff --git a/arch/mips/netlogic/common/smpboot.S b/arch/mips/netlogic/common/smpboot.S
index a0b7487..d772a87 100644 (file)
--- a/arch/mips/netlogic/common/smpboot.S
+++ b/arch/mips/netlogic/common/smpboot.S
@@ -69,6 +69,12 @@
 #endif
        mtcr    t1, t0
 
+       li      t0, ICU_DEFEATURE
+       mfcr    t1, t0
+       ori     t1, 0x1000      /* Enable Icache partitioning */
+       mtcr    t1, t0
+
+
 #ifdef XLP_AX_WORKAROUND
        li      t0, SCHED_DEFEATURE
        lui     t1, 0x0100      /* Disable BRU accepting ALU ops */