intel_scu_ipcutil: re-arch IPC ioctl struct

BZ: 33355

Userspace IPC ioctl is using self defined command and struct, it will
cause inconsistent problem if ethier kernel or userspace side is making
some changes. Correct way should be exporting the kernel ioctl command
and struct to the userspace with kernel header file to keep them
consisent. This patch fixes this problem.

Change-Id: Icdc6e51f254279fba980935610e837bf6208f12b
Signed-off-by: Shijie Zhang <shijie.zhang@intel.com>
Reviewed-on: http://android.intel.com:8080/46003
Reviewed-by: Chen, Jie D <jie.d.chen@intel.com>
Reviewed-by: Li, Ning <ning.li@intel.com>
Reviewed-by: Du, Alek <alek.du@intel.com>
Tested-by: Wang, Zhifeng <zhifeng.wang@intel.com>
Reviewed-by: buildbot <buildbot@intel.com>
Tested-by: buildbot <buildbot@intel.com>

diff --git a/arch/x86/include/asm/intel_scu_ipcutil.h b/arch/x86/include/asm/intel_scu_ipcutil.h
index bc2b871..3dc3b19 100644 (file)
--- a/arch/x86/include/asm/intel_scu_ipcutil.h
+++ b/arch/x86/include/asm/intel_scu_ipcutil.h
@@ -1,12 +1,47 @@
 #ifndef _ASM_X86_INTEL_SCU_IPCUTIL_H_
 #define _ASM_X86_INTEL_SCU_IPCUTIL_H_
 
+#include <linux/types.h>
+
+/* ioctl commnds */
+#define INTEL_SCU_IPC_REGISTER_READ    0
+#define INTEL_SCU_IPC_REGISTER_WRITE   1
+#define INTEL_SCU_IPC_REGISTER_UPDATE  2
+#define INTEL_SCU_IPC_FW_UPDATE                0xA2
+#define INTEL_SCU_IPC_MEDFIELD_FW_UPDATE       0xA3
+#define INTEL_SCU_IPC_FW_REVISION_GET  0xB0
+#define INTEL_SCU_IPC_READ_RR_FROM_OSNIB       0xC1
+#define INTEL_SCU_IPC_WRITE_RR_TO_OSNIB        0xC2
+#define INTEL_SCU_IPC_READ_VBATTCRIT   0xC4
+#define INTEL_SCU_IPC_WRITE_ALARM_FLAG_TO_OSNIB        0xC5
+#define INTEL_SCU_IPC_OSC_CLK_CNTL     0xC6
+
+struct scu_ipc_data {
+       __u32   count;  /* No. of registers */
+       __u16   addr[5]; /* Register addresses */
+       __u8    data[5]; /* Register data */
+       __u8    mask; /* Valid for read-modify-write */
+};
+
+struct scu_ipc_version {
+       __u32   count;  /* length of version info */
+       __u8    data[16]; /* version data */
+};
+
+struct osc_clk_t {
+       __u32   id; /* clock id */
+       __u32   khz; /* clock frequency */
+};
+
+
 /* Penwell has 4 osc clocks */
 #define OSC_CLK_AUDIO  0       /* Audio */
 #define OSC_CLK_CAM0   1       /* Primary camera */
 #define OSC_CLK_CAM1   2       /* Secondary camera */
 #define OSC_CLK_DISP   3       /* Display buffer */
 
+#ifdef __KERNEL__
+
 int intel_scu_ipc_osc_clk(u8 clk, unsigned int khz);
 
 enum clk0_mode {
@@ -32,3 +67,5 @@ int intel_scu_ipc_write_osnib_rr(u8 rr);
 int intel_scu_ipc_read_osnib_rr(u8 *rr);
 
 #endif
+
+#endif

diff --git a/drivers/platform/x86/intel_scu_ipcutil.c b/drivers/platform/x86/intel_scu_ipcutil.c
index f196ebb..08becd3 100644 (file)
--- a/drivers/platform/x86/intel_scu_ipcutil.c
+++ b/drivers/platform/x86/intel_scu_ipcutil.c
@@ -35,19 +35,6 @@
 
 #define MAX_FW_SIZE 264192
 
-/* ioctl commnds */
-#define INTEL_SCU_IPC_REGISTER_READ    0
-#define INTEL_SCU_IPC_REGISTER_WRITE   1
-#define INTEL_SCU_IPC_REGISTER_UPDATE  2
-#define INTEL_SCU_IPC_FW_UPDATE                0xA2
-#define INTEL_SCU_IPC_MEDFIELD_FW_UPDATE       0xA3
-#define INTEL_SCU_IPC_FW_REVISION_GET  0xB0
-#define INTEL_SCU_IPC_READ_RR_FROM_OSNIB       0xC1
-#define INTEL_SCU_IPC_WRITE_RR_TO_OSNIB        0xC2
-#define INTEL_SCU_IPC_READ_VBATTCRIT   0xC4
-#define INTEL_SCU_IPC_WRITE_ALARM_FLAG_TO_OSNIB 0xC5
-#define INTEL_SCU_IPC_OSC_CLK_CNTL 0xC6
-
 #define OSHOB_PMIT_OFFSET              0x0000002c
 #define OSNIB_RR_OFFSET                        OSNIB_OFFSET
 #define OSNIB_WD_OFFSET                        (OSNIB_OFFSET + 1)
@@ -66,23 +53,6 @@
 
 #define DUMP_OSNIB
 
-struct scu_ipc_data {
-       u32     count;  /* No. of registers */
-       u16     addr[5]; /* Register addresses */
-       u8      data[5]; /* Register data */
-       u8      mask; /* Valid for read-modify-write */
-};
-
-struct scu_ipc_version {
-       u32     count;  /* length of version info */
-       u8      data[16]; /* version data */
-};
-
-struct osc_clk_t {
-       unsigned int id; /* clock id */
-       unsigned int khz; /* clock frequency */
-};
-
 /* Mode for Audio clock */
 static DEFINE_MUTEX(osc_clk0_lock);
 static unsigned int osc_clk0_mode;