clk: mediatek: Add MT8186 ipesys clock support

Add MT8186 ipesys clock controller which provides clock gate
control for Image Process Engine.

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Miles Chen <miles.chen@mediatek.com>
Link: https://lore.kernel.org/r/20220409132251.31725-16-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 6902da6..caf2ce9 100644 (file)
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -75,7 +75,7 @@ obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-mcu.o clk-mt8186-topckgen.o clk-mt
                                   clk-mt8186-apmixedsys.o clk-mt8186-imp_iic_wrap.o \
                                   clk-mt8186-mfg.o clk-mt8186-mm.o clk-mt8186-wpe.o \
                                   clk-mt8186-img.o clk-mt8186-vdec.o clk-mt8186-venc.o \
-                                  clk-mt8186-cam.o clk-mt8186-mdp.o
+                                  clk-mt8186-cam.o clk-mt8186-mdp.o clk-mt8186-ipe.o
 obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
 obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
 obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o

diff --git a/drivers/clk/mediatek/clk-mt8186-ipe.c b/drivers/clk/mediatek/clk-mt8186-ipe.c
new file mode 100644 (file)
index 0000000..8fca148
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8186-ipe.c
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2022 MediaTek Inc.
+// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/clock/mt8186-clk.h>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+
+static const struct mtk_gate_regs ipe_cg_regs = {
+       .set_ofs = 0x4,
+       .clr_ofs = 0x8,
+       .sta_ofs = 0x0,
+};
+
+#define GATE_IPE(_id, _name, _parent, _shift)                  \
+       GATE_MTK(_id, _name, _parent, &ipe_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+static const struct mtk_gate ipe_clks[] = {
+       GATE_IPE(CLK_IPE_LARB19, "ipe_larb19", "top_ipe", 0),
+       GATE_IPE(CLK_IPE_LARB20, "ipe_larb20", "top_ipe", 1),
+       GATE_IPE(CLK_IPE_SMI_SUBCOM, "ipe_smi_subcom", "top_ipe", 2),
+       GATE_IPE(CLK_IPE_FD, "ipe_fd", "top_ipe", 3),
+       GATE_IPE(CLK_IPE_FE, "ipe_fe", "top_ipe", 4),
+       GATE_IPE(CLK_IPE_RSC, "ipe_rsc", "top_ipe", 5),
+       GATE_IPE(CLK_IPE_DPE, "ipe_dpe", "top_ipe", 6),
+       GATE_IPE(CLK_IPE_GALS_IPE, "ipe_gals_ipe", "top_img1", 8),
+};
+
+static const struct mtk_clk_desc ipe_desc = {
+       .clks = ipe_clks,
+       .num_clks = ARRAY_SIZE(ipe_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8186_ipe[] = {
+       {
+               .compatible = "mediatek,mt8186-ipesys",
+               .data = &ipe_desc,
+       }, {
+               /* sentinel */
+       }
+};
+
+static struct platform_driver clk_mt8186_ipe_drv = {
+       .probe = mtk_clk_simple_probe,
+       .remove = mtk_clk_simple_remove,
+       .driver = {
+               .name = "clk-mt8186-ipe",
+               .of_match_table = of_match_clk_mt8186_ipe,
+       },
+};
+builtin_platform_driver(clk_mt8186_ipe_drv);