clk:starfive:Modify the definitions instead of numbers in vout clock tree
authorxingyu.wu <xingyu.wu@starfivetech.com>
Tue, 24 May 2022 07:07:03 +0000 (15:07 +0800)
committerxingyu.wu <xingyu.wu@starfivetech.com>
Tue, 24 May 2022 07:07:10 +0000 (15:07 +0800)
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
drivers/clk/starfive/clk-starfive-jh7110-vout.c

index 4bd1036..4729738 100755 (executable)
@@ -29,41 +29,45 @@ static const struct jh7110_clk_data jh7110_clk_vout_data[] __initconst = {
        JH7110__DIV(JH7110_TX_ESC, "tx_esc", 31, JH7110_DISP_AHB),
        //dc8200
        JH7110_GATE(JH7110_U0_DC8200_CLK_AXI, "u0_dc8200_clk_axi",
-                       0, JH7110_DISP_AXI),
+                       GATE_FLAG_NORMAL, JH7110_DISP_AXI),
        JH7110_GATE(JH7110_U0_DC8200_CLK_CORE, "u0_dc8200_clk_core",
-                       0, JH7110_DISP_AXI),
+                       GATE_FLAG_NORMAL, JH7110_DISP_AXI),
        JH7110_GATE(JH7110_U0_DC8200_CLK_AHB, "u0_dc8200_clk_ahb",
-                       0, JH7110_DISP_AHB),
-       JH7110_GMUX(JH7110_U0_DC8200_CLK_PIX0, "u0_dc8200_clk_pix0", 0, 2,
+                       GATE_FLAG_NORMAL, JH7110_DISP_AHB),
+       JH7110_GMUX(JH7110_U0_DC8200_CLK_PIX0, "u0_dc8200_clk_pix0",
+                       GATE_FLAG_NORMAL, PARENT_NUMS_2,
                        JH7110_DC8200_PIX0,
                        JH7110_HDMITX0_PIXELCLK),
-       JH7110_GMUX(JH7110_U0_DC8200_CLK_PIX1, "u0_dc8200_clk_pix1", 0, 2,
+       JH7110_GMUX(JH7110_U0_DC8200_CLK_PIX1, "u0_dc8200_clk_pix1",
+                       GATE_FLAG_NORMAL, PARENT_NUMS_2,
                        JH7110_DC8200_PIX0,
                        JH7110_HDMITX0_PIXELCLK),
        
-       JH7110_GMUX(JH7110_DOM_VOUT_TOP_LCD_CLK, "dom_vout_top_lcd_clk", 0, 2,
+       JH7110_GMUX(JH7110_DOM_VOUT_TOP_LCD_CLK, "dom_vout_top_lcd_clk",
+                       GATE_FLAG_NORMAL, PARENT_NUMS_2,
                        JH7110_U0_DC8200_CLK_PIX0_OUT,
                        JH7110_U0_DC8200_CLK_PIX1_OUT),
        //dsiTx
        JH7110_GATE(JH7110_U0_CDNS_DSITX_CLK_APB, "u0_cdns_dsiTx_clk_apb",
-                       0, JH7110_DSI_SYS),
+                       GATE_FLAG_NORMAL, JH7110_DSI_SYS),
        JH7110_GATE(JH7110_U0_CDNS_DSITX_CLK_SYS, "u0_cdns_dsiTx_clk_sys",
-                       0, JH7110_DSI_SYS),
-       JH7110_GMUX(JH7110_U0_CDNS_DSITX_CLK_DPI, "u0_cdns_dsiTx_clk_api", 0, 2,
+                       GATE_FLAG_NORMAL, JH7110_DSI_SYS),
+       JH7110_GMUX(JH7110_U0_CDNS_DSITX_CLK_DPI, "u0_cdns_dsiTx_clk_api",
+                       GATE_FLAG_NORMAL, PARENT_NUMS_2,
                        JH7110_DC8200_PIX0,
                        JH7110_HDMITX0_PIXELCLK),
        JH7110_GATE(JH7110_U0_CDNS_DSITX_CLK_TXESC, "u0_cdns_dsiTx_clk_txesc",
-                       0, JH7110_TX_ESC),
+                       GATE_FLAG_NORMAL, JH7110_TX_ESC),
        //mipitx DPHY
        JH7110_GATE(JH7110_U0_MIPITX_DPHY_CLK_TXESC, "u0_mipitx_dphy_clk_txesc",
-                       0, JH7110_TX_ESC),
+                       GATE_FLAG_NORMAL, JH7110_TX_ESC),
        //hdmi
        JH7110_GATE(JH7110_U0_HDMI_TX_CLK_MCLK, "u0_hdmi_tx_clk_mclk",
-                       0, JH7110_HDMITX0_MCLK),
+                       GATE_FLAG_NORMAL, JH7110_HDMITX0_MCLK),
        JH7110_GATE(JH7110_U0_HDMI_TX_CLK_BCLK, "u0_hdmi_tx_clk_bclk",
-                       0, JH7110_HDMITX0_SCK),
+                       GATE_FLAG_NORMAL, JH7110_HDMITX0_SCK),
        JH7110_GATE(JH7110_U0_HDMI_TX_CLK_SYS, "u0_hdmi_tx_clk_sys",
-                       0, JH7110_DISP_APB),
+                       GATE_FLAG_NORMAL, JH7110_DISP_APB),
 };
 
 static struct clk_hw *jh7110_vout_clk_get(struct of_phandle_args *clkspec,