config GENERIC_SMP_IDLE_THREAD
bool
-config HAVE_GENERIC_INIT_TASK
+# Select if arch init_task initializer is different to init/init_task.c
+config ARCH_INIT_TASK
bool
config HAVE_REGS_AND_STACK_ACCESS_API
select ARCH_WANT_OPTIONAL_GPIOLIB
select ARCH_HAVE_NMI_SAFE_CMPXCHG
select GENERIC_SMP_IDLE_THREAD
- select HAVE_GENERIC_INIT_TASK
help
The Alpha is a 64-bit general-purpose processor designed and
marketed by the Digital Equipment Corporation of blessed memory,
select GENERIC_PCI_IOMAP
select HAVE_BPF_JIT if NET
select GENERIC_SMP_IDLE_THREAD
- select HAVE_GENERIC_INIT_TASK
help
The ARM series is a line of low-power-consumption RISC chip designs
licensed by ARM Ltd and targeted at embedded applications and
select HARDIRQS_SW_RESEND
select GENERIC_IRQ_SHOW
select ARCH_HAVE_NMI_SAFE_CMPXCHG
- select HAVE_GENERIC_INIT_TASK
help
AVR32 is a high-performance 32-bit RISC microprocessor core,
designed for cost-sensitive embedded applications, with particular
select IRQ_PER_CPU if SMP
select HAVE_NMI_WATCHDOG if NMI_WATCHDOG
select GENERIC_SMP_IDLE_THREAD
- select HAVE_GENERIC_INIT_TASK
config GENERIC_CSUM
def_bool y
select HAVE_ARCH_TRACEHOOK
select HAVE_DMA_API_DEBUG
select HAVE_GENERIC_HARDIRQS
- select HAVE_GENERIC_INIT_TASK
select HAVE_MEMBLOCK
select SPARSE_IRQ
select IRQ_DOMAIN
select GENERIC_IRQ_SHOW
select GENERIC_IOMAP
select GENERIC_SMP_IDLE_THREAD if ETRAX_ARCH_V32
- select HAVE_GENERIC_INIT_TASK
config HZ
int
select GENERIC_IRQ_SHOW
select ARCH_HAVE_NMI_SAFE_CMPXCHG
select GENERIC_CPU_DEVICES
- select HAVE_GENERIC_INIT_TASK
config ZONE_DMA
bool
select HAVE_GENERIC_HARDIRQS
select GENERIC_IRQ_SHOW
select GENERIC_CPU_DEVICES
- select HAVE_GENERIC_INIT_TASK
config SYMBOL_PREFIX
string
select NO_IOPORT
select GENERIC_IOMAP
select GENERIC_SMP_IDLE_THREAD
- select HAVE_GENERIC_INIT_TASK
# mostly generic routines, with some accelerated ones
---help---
Qualcomm Hexagon is a processor architecture designed for high
select ARCH_HAVE_NMI_SAFE_CMPXCHG
select GENERIC_IOMAP
select GENERIC_SMP_IDLE_THREAD
+ select ARCH_INIT_TASK
default y
help
The Itanium Processor Family is Intel's 64-bit successor to
select GENERIC_IRQ_PROBE
select GENERIC_IRQ_SHOW
select GENERIC_ATOMIC64
- select HAVE_GENERIC_INIT_TASK
config SBUS
bool
select ARCH_HAVE_NMI_SAFE_CMPXCHG if RMW_INSNS
select GENERIC_CPU_DEVICES
select FPU if MMU
- select HAVE_GENERIC_INIT_TASK
config RWSEM_GENERIC_SPINLOCK
bool
select GENERIC_PCI_IOMAP
select GENERIC_CPU_DEVICES
select GENERIC_ATOMIC64
- select HAVE_GENERIC_INIT_TASK
config SWAP
def_bool n
select HAVE_MEMBLOCK_NODE_MAP
select ARCH_DISCARD_MEMBLOCK
select GENERIC_SMP_IDLE_THREAD
- select HAVE_GENERIC_INIT_TASK
menu "Machine selection"
select HAVE_ARCH_TRACEHOOK
select HAVE_ARCH_KGDB
select HAVE_NMI_WATCHDOG if MN10300_WD_TIMER
- select HAVE_GENERIC_INIT_TASK
config AM33_2
def_bool n
select GENERIC_IOMAP
select GENERIC_CPU_DEVICES
select GENERIC_ATOMIC64
- select HAVE_GENERIC_INIT_TASK
config MMU
def_bool y
select IRQ_PER_CPU
select ARCH_HAVE_NMI_SAFE_CMPXCHG
select GENERIC_SMP_IDLE_THREAD
- select HAVE_GENERIC_INIT_TASK
help
The PA-RISC microprocessor is designed by Hewlett-Packard and used
select HAVE_ARCH_JUMP_LABEL
select ARCH_HAVE_NMI_SAFE_CMPXCHG
select GENERIC_SMP_IDLE_THREAD
- select HAVE_GENERIC_INIT_TASK
config EARLY_PRINTK
bool
select ARCH_INLINE_WRITE_UNLOCK_IRQ
select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE
select GENERIC_SMP_IDLE_THREAD
- select HAVE_GENERIC_INIT_TASK
config SCHED_OMIT_FRAME_POINTER
def_bool y
select HAVE_MEMBLOCK_NODE_MAP
select ARCH_DISCARD_MEMBLOCK
select GENERIC_CPU_DEVICES
- select HAVE_GENERIC_INIT_TASK
choice
prompt "System type"
select GENERIC_ATOMIC64
select GENERIC_IRQ_SHOW
select GENERIC_SMP_IDLE_THREAD
- select HAVE_GENERIC_INIT_TASK
help
The SuperH is a RISC processor targeted for use in embedded systems
and consumer electronics; it was also used in the Sega Dreamcast
select GENERIC_PCI_IOMAP
select HAVE_NMI_WATCHDOG if SPARC64
select GENERIC_SMP_IDLE_THREAD
- select HAVE_GENERIC_INIT_TASK
config SPARC32
def_bool !64BIT
select GENERIC_IRQ_SHOW
select SYS_HYPERVISOR
select ARCH_HAVE_NMI_SAFE_CMPXCHG
- select HAVE_GENERIC_INIT_TASK
# FIXME: investigate whether we need/want these options.
# select HAVE_IOREMAP_PROT
select GENERIC_IRQ_SHOW
select GENERIC_CPU_DEVICES
select GENERIC_IO
- select HAVE_GENERIC_INIT_TASK
config MMU
bool
select GENERIC_IRQ_SHOW
select ARCH_WANT_FRAME_POINTERS
select GENERIC_IOMAP
- select HAVE_GENERIC_INIT_TASK
help
UniCore-32 is 32-bit Instruction Set Architecture,
including a series of low-power-consumption RISC chip
select GENERIC_IOMAP
select DCACHE_WORD_ACCESS if !DEBUG_PAGEALLOC
select GENERIC_SMP_IDLE_THREAD
- select HAVE_GENERIC_INIT_TASK
config INSTRUCTION_DECODER
def_bool (KPROBES || PERF_EVENTS)
select HAVE_GENERIC_HARDIRQS
select GENERIC_IRQ_SHOW
select GENERIC_CPU_DEVICES
- select HAVE_GENERIC_INIT_TASK
help
Xtensa processors are 32-bit RISC machines designed by Tensilica
primarily for embedded systems. These processors are both
obj-$(CONFIG_BLK_DEV_INITRD) += initramfs.o
endif
obj-$(CONFIG_GENERIC_CALIBRATE_DELAY) += calibrate.o
-obj-$(CONFIG_HAVE_GENERIC_INIT_TASK) += init_task.o
+
+ifneq ($(CONFIG_ARCH_INIT_TASK),y)
+obj-y += init_task.o
+endif
mounts-y := do_mounts.o
mounts-$(CONFIG_BLK_DEV_RAM) += do_mounts_rd.o
projects / profile / ivi / kernel-adaptation-intel-automotive.git / commitdiff